2 * (C) Copyright 2002-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Configuration settings for the PCIPPC-2 board.
30 /* ------------------------------------------------------------------------- */
33 * board/config.h - configuration options, board specific
40 * High Level Configuration Options
44 #define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
46 #define CONFIG_BOARD_EARLY_INIT_F 1
47 #define CONFIG_MISC_INIT_R 1
49 #define CONFIG_CONS_INDEX 1
50 #define CONFIG_BAUDRATE 9600
51 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
53 #define CONFIG_PREBOOT ""
54 #define CONFIG_BOOTDELAY 5
56 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
57 CONFIG_BOOTP_BOOTFILESIZE)
59 #define CONFIG_MAC_PARTITION
60 #define CONFIG_DOS_PARTITION
62 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
74 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
76 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
78 #include <cmd_confdefs.h>
80 #define CFG_NAND_LEGACY
83 * Miscellaneous configurable options
85 #define CFG_LONGHELP /* undef to save memory */
86 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
88 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
89 #ifdef CFG_HUSH_PARSER
90 #define CFG_PROMPT_HUSH_PS2 "> "
92 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
96 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
98 #define CFG_MAXARGS 64 /* max number of command args */
99 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
100 #define CFG_LOAD_ADDR 0x00100000 /* Default load address */
102 /*-----------------------------------------------------------------------
103 * Start addresses for the final memory configuration
104 * (Set up by the startup code)
105 * Please note that CFG_SDRAM_BASE _must_ start at 0
107 #define CFG_SDRAM_BASE 0x00000000
108 #define CFG_FLASH_BASE 0xFFF00000
109 #define CFG_FLASH_MAX_SIZE 0x00100000
110 /* Maximum amount of RAM.
112 #define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */
114 #define CFG_RESET_ADDRESS 0xFFF00100
116 #define CFG_MONITOR_BASE TEXT_BASE
118 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
119 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
121 #if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
122 CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
128 #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
129 #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
131 /*-----------------------------------------------------------------------
132 * Definitions for initial stack pointer and data area
135 /* Size in bytes reserved for initial data
137 #define CFG_GBL_DATA_SIZE 128
139 #define CFG_INIT_RAM_ADDR 0x40000000
140 #define CFG_INIT_RAM_END 0x8000
141 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
142 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
144 #define CFG_INIT_RAM_LOCK
147 * Temporary buffer for serial data until the real serial driver
148 * is initialised (memtest will destroy this buffer)
150 #define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR
151 #define CFG_SCONSOLE_SIZE 0x0002000
155 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
156 #define CFG_DBAT0U (CFG_SDRAM_BASE | \
157 BATU_BL_256M | BATU_VS | BATU_VP)
160 #define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \
161 BATL_PP_10 | BATL_MEMCOHERENCE)
162 #define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \
163 BATU_BL_256M | BATU_VS | BATU_VP)
165 /* Init RAM in the CPU DCache (no backing memory)
167 #define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \
168 BATL_PP_10 | BATL_MEMCOHERENCE)
169 #define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \
170 BATU_BL_128K | BATU_VS | BATU_VP)
172 /* I/O and PCI memory at 0xf0000000
174 #define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
175 #define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
177 #define CFG_IBAT0L CFG_DBAT0L
178 #define CFG_IBAT0U CFG_DBAT0U
179 #define CFG_IBAT1L CFG_DBAT1L
180 #define CFG_IBAT1U CFG_DBAT1U
181 #define CFG_IBAT2L CFG_DBAT2L
182 #define CFG_IBAT2U CFG_DBAT2U
183 #define CFG_IBAT3L CFG_DBAT3L
184 #define CFG_IBAT3U CFG_DBAT3U
187 * Low Level Configuration Settings
188 * (address mappings, register initial values, etc.)
189 * You should know what you are doing if you make changes here.
190 * For the detail description refer to the PCIPPC2 user's manual.
193 #define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */
194 #define CFG_CPU_CLK 300000000
195 #define CFG_BUS_CLK 100000000
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization.
202 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
204 /*-----------------------------------------------------------------------
207 #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
208 #define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
210 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
211 #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
214 * Note: environment is not EMBEDDED in the U-Boot code.
215 * It's stored in flash separately.
217 #define CFG_ENV_IS_IN_FLASH 1
218 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000)
219 #define CFG_ENV_SIZE 0x1000 /* Size of the Environment */
220 #define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
222 /*-----------------------------------------------------------------------
223 * Cache Configuration
225 #define CFG_CACHELINE_SIZE 32
226 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
227 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
234 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
235 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
236 #define L2_ENABLE (L2_INIT | L2CR_L2E)
239 * Internal Definitions
243 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
244 #define BOOTFLAG_WARM 0x02 /* Software reboot */
246 /*-----------------------------------------------------------------------
247 * Disk-On-Chip configuration
250 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
252 #define CFG_DOC_SUPPORT_2000
253 #undef CFG_DOC_SUPPORT_MILLENNIUM
255 /*-----------------------------------------------------------------------
258 #define CONFIG_RTC_MK48T59
260 #define CONFIG_WATCHDOG
262 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
264 #define CONFIG_EEPRO100
265 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
268 #endif /* __CONFIG_H */