1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
20 /* Set 1M boot space */
21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
23 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 /* High Level Configuration Options */
28 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
31 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
35 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
36 #define CONFIG_PCIE1 /* PCIE controller 1 */
37 #define CONFIG_PCIE2 /* PCIE controller 2 */
38 #define CONFIG_PCIE3 /* PCIE controller 3 */
40 #define CONFIG_SYS_SRIO
41 #define CONFIG_SRIO1 /* SRIO port 1 */
42 #define CONFIG_SRIO2 /* SRIO port 2 */
43 #define CONFIG_SRIO_PCIE_BOOT_MASTER
44 #define CONFIG_SYS_DPAA_RMAN /* RMan */
46 #if defined(CONFIG_SPIFLASH)
47 #elif defined(CONFIG_SDCARD)
48 #define CONFIG_FSL_FIXED_MMC_LOCATION
52 unsigned long get_board_sys_clk(void);
53 #include <linux/stringify.h>
55 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
58 * These can be toggled for performance analysis, otherwise use default.
60 #define CONFIG_SYS_CACHE_STASHING
61 #define CONFIG_BACKSIDE_L2_CACHE
62 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
63 #define CONFIG_BTB /* toggle branch predition */
65 #define CONFIG_ENABLE_36BIT_PHYS
67 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
70 * Config the L3 Cache as L3 SRAM
72 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
73 #ifdef CONFIG_PHYS_64BIT
74 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
75 CONFIG_RAMBOOT_TEXT_BASE)
77 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
79 #define CONFIG_SYS_L3_SIZE (1024 << 10)
80 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
82 #ifdef CONFIG_PHYS_64BIT
83 #define CONFIG_SYS_DCSRBAR 0xf0000000
84 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
88 #define CONFIG_SYS_I2C_EEPROM_NXID
89 #define CONFIG_SYS_EEPROM_BUS_NUM 0
94 #define CONFIG_VERY_BIG_RAM
95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
99 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
101 #define CONFIG_SYS_SPD_BUS_NUM 0
102 #define SPD_EEPROM_ADDRESS 0x52
103 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
106 * Local Bus Definitions
109 /* Set the local bus clock 1/8 of platform clock */
110 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
113 * This board doesn't have a promjet connector.
114 * However, it uses commone corenet board LAW and TLB.
115 * It is necessary to use the same start address with proper offset.
117 #define CONFIG_SYS_FLASH_BASE 0xe0000000
118 #ifdef CONFIG_PHYS_64BIT
119 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
121 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
124 #define CONFIG_SYS_FLASH_BR_PRELIM \
125 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
127 #define CONFIG_SYS_FLASH_OR_PRELIM \
128 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
129 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
131 #define CONFIG_FSL_CPLD
132 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
133 #ifdef CONFIG_PHYS_64BIT
134 #define CPLD_BASE_PHYS 0xfffdf0000ull
136 #define CPLD_BASE_PHYS CPLD_BASE
139 #define PIXIS_LBMAP_SWITCH 7
140 #define PIXIS_LBMAP_MASK 0xf0
141 #define PIXIS_LBMAP_SHIFT 4
142 #define PIXIS_LBMAP_ALTBANK 0x40
144 #define CONFIG_SYS_FLASH_QUIET_TEST
145 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
147 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
148 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
149 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
150 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
152 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
154 #if defined(CONFIG_RAMBOOT_PBL)
155 #define CONFIG_SYS_RAMBOOT
159 #ifdef CONFIG_NAND_FSL_ELBC
160 #define CONFIG_SYS_NAND_BASE 0xffa00000
161 #ifdef CONFIG_PHYS_64BIT
162 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
164 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
167 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
168 #define CONFIG_SYS_MAX_NAND_DEVICE 1
170 /* NAND flash config */
171 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
172 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
173 | BR_PS_8 /* Port Size = 8 bit */ \
174 | BR_MS_FCM /* MSEL = FCM */ \
176 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
177 | OR_FCM_PGS /* Large Page*/ \
184 #endif /* CONFIG_NAND_FSL_ELBC */
186 #define CONFIG_SYS_FLASH_EMPTY_INFO
187 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
189 #define CONFIG_HWCONFIG
191 /* define to use L1 as initial stack */
192 #define CONFIG_L1_INIT_RAM
193 #define CONFIG_SYS_INIT_RAM_LOCK
194 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
195 #ifdef CONFIG_PHYS_64BIT
196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
198 /* The assembler doesn't like typecast */
199 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
200 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
201 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
203 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
204 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
205 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
207 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
209 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
210 GENERATED_GBL_DATA_SIZE)
211 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
213 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
215 /* Serial Port - controlled on board with jumper J8
219 #define CONFIG_SYS_NS16550_SERIAL
220 #define CONFIG_SYS_NS16550_REG_SIZE 1
221 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
223 #define CONFIG_SYS_BAUDRATE_TABLE \
224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
228 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
229 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
237 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
238 #ifdef CONFIG_PHYS_64BIT
239 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
241 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
243 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
245 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
246 #ifdef CONFIG_PHYS_64BIT
247 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
249 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
251 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
254 * for slave u-boot IMAGE instored in master memory space,
255 * PHYS must be aligned based on the SIZE
257 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
258 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
259 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
260 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
262 * for slave UCODE and ENV instored in master memory space,
263 * PHYS must be aligned based on the SIZE
265 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
266 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
267 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
269 /* slave core release by master*/
270 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
271 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
274 * SRIO_PCIE_BOOT - SLAVE
276 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
277 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
278 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
279 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
283 * eSPI - Enhanced SPI
288 * Memory space is mapped 1-1, but I/O space must start from 0.
291 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
292 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
293 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
294 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
295 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
297 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
298 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
299 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
300 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
301 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
303 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
304 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
305 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
306 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
307 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
310 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
311 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
312 #ifdef CONFIG_PHYS_64BIT
313 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
315 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
317 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
318 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
319 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
320 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
321 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
322 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
323 CONFIG_SYS_BMAN_CENA_SIZE)
324 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
325 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
326 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
327 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
328 #ifdef CONFIG_PHYS_64BIT
329 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
331 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
333 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
334 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
335 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
336 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
337 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
338 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
339 CONFIG_SYS_QMAN_CENA_SIZE)
340 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
341 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
343 #define CONFIG_SYS_DPAA_FMAN
344 #define CONFIG_SYS_DPAA_PME
345 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
348 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
349 #endif /* CONFIG_PCI */
352 #define CONFIG_FSL_SATA_V2
354 #ifdef CONFIG_FSL_SATA_V2
355 #define CONFIG_SYS_SATA_MAX_DEVICE 2
357 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
358 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
360 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
361 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
366 #ifdef CONFIG_FMAN_ENET
367 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
368 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
369 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
370 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
371 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
373 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
374 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
375 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
376 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
378 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
380 #define CONFIG_SYS_TBIPA_VALUE 8
381 #define CONFIG_ETHPRIME "FM1@DTSEC1"
387 #define CONFIG_LOADS_ECHO /* echo on for serial download */
388 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
393 #define CONFIG_HAS_FSL_DR_USB
394 #define CONFIG_HAS_FSL_MPH_USB
396 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
397 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
401 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
402 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
406 * Miscellaneous configurable options
410 * For booting Linux, the board info and command line data
411 * have to be in the first 64 MB of memory, since this is
412 * the maximum mapped by the Linux kernel during initialization.
414 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
415 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
418 * Environment Configuration
420 #define CONFIG_ROOTPATH "/opt/nfsroot"
421 #define CONFIG_BOOTFILE "uImage"
422 #define CONFIG_UBOOTPATH u-boot.bin
424 #define __USB_PHY_TYPE utmi
426 #define CONFIG_EXTRA_ENV_SETTINGS \
427 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
428 "bank_intlv=cs0_cs1\0" \
430 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
431 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
432 "tftpflash=tftpboot $loadaddr $uboot && " \
433 "protect off $ubootaddr +$filesize && " \
434 "erase $ubootaddr +$filesize && " \
435 "cp.b $loadaddr $ubootaddr $filesize && " \
436 "protect on $ubootaddr +$filesize && " \
437 "cmp.b $loadaddr $ubootaddr $filesize\0" \
438 "consoledev=ttyS0\0" \
439 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
440 "usb_dr_mode=host\0" \
441 "ramdiskaddr=2000000\0" \
442 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
443 "fdtaddr=1e00000\0" \
444 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
447 #include <asm/fsl_secure_boot.h>
449 #endif /* __CONFIG_H */