include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  29
  30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  32 #endif
  33
  34 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  35 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  36 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  37 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  38 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  39
  40 #define CONFIG_SYS_SRIO
  41 #define CONFIG_SRIO1                    /* SRIO port 1 */
  42 #define CONFIG_SRIO2                    /* SRIO port 2 */
  43 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  44 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  45
  46 #ifndef __ASSEMBLY__
  47 #include <linux/stringify.h>
  48 #endif
  49
  50 /*
  51  * These can be toggled for performance analysis, otherwise use default.
  52  */
  53 #define CONFIG_SYS_CACHE_STASHING
  54 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  55
  56 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  57
  58 /*
  59  *  Config the L3 Cache as L3 SRAM
  60  */
  61 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  62 #ifdef CONFIG_PHYS_64BIT
  63 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  64                 CONFIG_RAMBOOT_TEXT_BASE)
  65 #else
  66 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  67 #endif
  68 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  69 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  70
  71 #ifdef CONFIG_PHYS_64BIT
  72 #define CONFIG_SYS_DCSRBAR              0xf0000000
  73 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  74 #endif
  75
  76 /* EEPROM */
  77 #define CONFIG_SYS_I2C_EEPROM_NXID
  78 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  79
  80 /*
  81  * DDR Setup
  82  */
  83 #define CONFIG_VERY_BIG_RAM
  84 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  85 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  86
  87 #define SPD_EEPROM_ADDRESS      0x52
  88 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  89
  90 /*
  91  * Local Bus Definitions
  92  */
  93
  94 /* Set the local bus clock 1/8 of platform clock */
  95 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  96
  97 /*
  98  * This board doesn't have a promjet connector.
  99  * However, it uses commone corenet board LAW and TLB.
 100  * It is necessary to use the same start address with proper offset.
 101  */
 102 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 103 #ifdef CONFIG_PHYS_64BIT
 104 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 105 #else
 106 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 107 #endif
 108
 109 #define CONFIG_SYS_FLASH_BR_PRELIM \
 110                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 111                 BR_PS_16 | BR_V)
 112 #define CONFIG_SYS_FLASH_OR_PRELIM \
 113                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 114                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 115
 116 #define CONFIG_FSL_CPLD
 117 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 118 #ifdef CONFIG_PHYS_64BIT
 119 #define CPLD_BASE_PHYS          0xfffdf0000ull
 120 #else
 121 #define CPLD_BASE_PHYS          CPLD_BASE
 122 #endif
 123
 124 #define PIXIS_LBMAP_SWITCH      7
 125 #define PIXIS_LBMAP_MASK        0xf0
 126 #define PIXIS_LBMAP_SHIFT       4
 127 #define PIXIS_LBMAP_ALTBANK     0x40
 128
 129 #define CONFIG_SYS_FLASH_QUIET_TEST
 130 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 131
 132 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 133 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 134 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 135
 136 #if defined(CONFIG_RAMBOOT_PBL)
 137 #define CONFIG_SYS_RAMBOOT
 138 #endif
 139
 140 /* Nand Flash */
 141 #ifdef CONFIG_NAND_FSL_ELBC
 142 #define CONFIG_SYS_NAND_BASE            0xffa00000
 143 #ifdef CONFIG_PHYS_64BIT
 144 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 145 #else
 146 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 147 #endif
 148
 149 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 150 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 151
 152 /* NAND flash config */
 153 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 154                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 155                                | BR_PS_8               /* Port Size = 8 bit */ \
 156                                | BR_MS_FCM             /* MSEL = FCM */ \
 157                                | BR_V)                 /* valid */
 158 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 159                                | OR_FCM_PGS            /* Large Page*/ \
 160                                | OR_FCM_CSCT \
 161                                | OR_FCM_CST \
 162                                | OR_FCM_CHT \
 163                                | OR_FCM_SCY_1 \
 164                                | OR_FCM_TRLX \
 165                                | OR_FCM_EHTR)
 166 #endif /* CONFIG_NAND_FSL_ELBC */
 167
 168 #define CONFIG_SYS_FLASH_EMPTY_INFO
 169 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 170
 171 #define CONFIG_HWCONFIG
 172
 173 /* define to use L1 as initial stack */
 174 #define CONFIG_L1_INIT_RAM
 175 #define CONFIG_SYS_INIT_RAM_LOCK
 176 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 177 #ifdef CONFIG_PHYS_64BIT
 178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 180 /* The assembler doesn't like typecast */
 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 182         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 183           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 184 #else
 185 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 186 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 187 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 188 #endif
 189 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 190
 191 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 192
 193 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 194
 195 /* Serial Port - controlled on board with jumper J8
 196  * open - index 2
 197  * shorted - index 1
 198  */
 199 #define CONFIG_SYS_NS16550_SERIAL
 200 #define CONFIG_SYS_NS16550_REG_SIZE     1
 201 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 202
 203 #define CONFIG_SYS_BAUDRATE_TABLE       \
 204         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 205
 206 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 207 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 208 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 209 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 210
 211 /* I2C */
 212
 213
 214 /*
 215  * RapidIO
 216  */
 217 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 218 #ifdef CONFIG_PHYS_64BIT
 219 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 220 #else
 221 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 222 #endif
 223 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 224
 225 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 226 #ifdef CONFIG_PHYS_64BIT
 227 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 228 #else
 229 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 230 #endif
 231 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 232
 233 /*
 234  * for slave u-boot IMAGE instored in master memory space,
 235  * PHYS must be aligned based on the SIZE
 236  */
 237 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 238 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 239 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 240 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 241 /*
 242  * for slave UCODE and ENV instored in master memory space,
 243  * PHYS must be aligned based on the SIZE
 244  */
 245 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 246 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 247 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 248
 249 /* slave core release by master*/
 250 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 251 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 252
 253 /*
 254  * SRIO_PCIE_BOOT - SLAVE
 255  */
 256 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 257 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 258 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 259                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 260 #endif
 261
 262 /*
 263  * eSPI - Enhanced SPI
 264  */
 265
 266 /*
 267  * General PCI
 268  * Memory space is mapped 1-1, but I/O space must start from 0.
 269  */
 270
 271 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 272 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 273 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 274 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 275 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 276
 277 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 278 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 279 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 280 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 281 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 282
 283 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 284 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 285 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 286 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 287 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 288
 289 /* Qman/Bman */
 290 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 291 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 292 #ifdef CONFIG_PHYS_64BIT
 293 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 294 #else
 295 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 296 #endif
 297 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 298 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 299 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 300 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 301 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 302 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 303                                         CONFIG_SYS_BMAN_CENA_SIZE)
 304 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 305 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 306 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 307 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 308 #ifdef CONFIG_PHYS_64BIT
 309 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 310 #else
 311 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 312 #endif
 313 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 314 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 315 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 316 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 317 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 318 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 319                                         CONFIG_SYS_QMAN_CENA_SIZE)
 320 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 321 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 322
 323 #define CONFIG_SYS_DPAA_FMAN
 324 #define CONFIG_SYS_DPAA_PME
 325 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 326
 327 #ifdef CONFIG_PCI
 328 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 329 #endif  /* CONFIG_PCI */
 330
 331 #ifdef CONFIG_FMAN_ENET
 332 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 333 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 334 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 335 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 336 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 337
 338 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 339 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 340 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 341 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 342
 343 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 344
 345 #define CONFIG_SYS_TBIPA_VALUE  8
 346 #endif
 347
 348 /*
 349  * Environment
 350  */
 351 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 352 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 353
 354 #ifdef CONFIG_MMC
 355 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 356 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 357 #endif
 358
 359 /*
 360  * Miscellaneous configurable options
 361  */
 362
 363 /*
 364  * For booting Linux, the board info and command line data
 365  * have to be in the first 64 MB of memory, since this is
 366  * the maximum mapped by the Linux kernel during initialization.
 367  */
 368 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 369 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 370
 371 /*
 372  * Environment Configuration
 373  */
 374 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 375 #define CONFIG_UBOOTPATH        u-boot.bin
 376
 377 #define __USB_PHY_TYPE  utmi
 378
 379 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 380         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 381         "bank_intlv=cs0_cs1\0"                                  \
 382         "netdev=eth0\0"                                         \
 383         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 384         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 385         "tftpflash=tftpboot $loadaddr $uboot && "               \
 386         "protect off $ubootaddr +$filesize && "                 \
 387         "erase $ubootaddr +$filesize && "                       \
 388         "cp.b $loadaddr $ubootaddr $filesize && "               \
 389         "protect on $ubootaddr +$filesize && "                  \
 390         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 391         "consoledev=ttyS0\0"                                    \
 392         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 393         "usb_dr_mode=host\0"                                    \
 394         "ramdiskaddr=2000000\0"                                 \
 395         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 396         "fdtaddr=1e00000\0"                                     \
 397         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 398         "bdev=sda3\0"
 399
 400 #include <asm/fsl_secure_boot.h>
 401
 402 #endif  /* __CONFIG_H */