1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
20 /* Set 1M boot space */
21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
23 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 /* High Level Configuration Options */
29 #ifndef CONFIG_RESET_VECTOR_ADDRESS
30 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
33 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
35 #define CONFIG_SYS_SRIO
36 #define CONFIG_SRIO1 /* SRIO port 1 */
37 #define CONFIG_SRIO2 /* SRIO port 2 */
38 #define CONFIG_SRIO_PCIE_BOOT_MASTER
39 #define CONFIG_SYS_DPAA_RMAN /* RMan */
42 #include <linux/stringify.h>
46 * These can be toggled for performance analysis, otherwise use default.
48 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
50 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
53 * Config the L3 Cache as L3 SRAM
55 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
56 #ifdef CONFIG_PHYS_64BIT
57 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
58 CONFIG_RAMBOOT_TEXT_BASE)
60 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
62 #define CONFIG_SYS_L3_SIZE (1024 << 10)
63 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
65 #ifdef CONFIG_PHYS_64BIT
66 #define CONFIG_SYS_DCSRBAR 0xf0000000
67 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
73 #define CONFIG_VERY_BIG_RAM
74 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
75 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
77 #define SPD_EEPROM_ADDRESS 0x52
78 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
81 * Local Bus Definitions
84 /* Set the local bus clock 1/8 of platform clock */
85 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
88 * This board doesn't have a promjet connector.
89 * However, it uses commone corenet board LAW and TLB.
90 * It is necessary to use the same start address with proper offset.
92 #define CONFIG_SYS_FLASH_BASE 0xe0000000
93 #ifdef CONFIG_PHYS_64BIT
94 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
96 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
99 #define CONFIG_FSL_CPLD
100 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
101 #ifdef CONFIG_PHYS_64BIT
102 #define CPLD_BASE_PHYS 0xfffdf0000ull
104 #define CPLD_BASE_PHYS CPLD_BASE
107 #define PIXIS_LBMAP_SWITCH 7
108 #define PIXIS_LBMAP_MASK 0xf0
109 #define PIXIS_LBMAP_SHIFT 4
110 #define PIXIS_LBMAP_ALTBANK 0x40
112 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
115 #ifdef CONFIG_NAND_FSL_ELBC
116 #define CONFIG_SYS_NAND_BASE 0xffa00000
117 #ifdef CONFIG_PHYS_64BIT
118 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
120 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
123 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
124 #define CONFIG_SYS_MAX_NAND_DEVICE 1
126 /* NAND flash config */
127 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
128 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
129 | BR_PS_8 /* Port Size = 8 bit */ \
130 | BR_MS_FCM /* MSEL = FCM */ \
132 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
133 | OR_FCM_PGS /* Large Page*/ \
140 #endif /* CONFIG_NAND_FSL_ELBC */
142 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
144 #define CONFIG_HWCONFIG
146 /* define to use L1 as initial stack */
147 #define CONFIG_L1_INIT_RAM
148 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
149 #ifdef CONFIG_PHYS_64BIT
150 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
151 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
152 /* The assembler doesn't like typecast */
153 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
154 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
155 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
157 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
161 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
163 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
165 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
167 /* Serial Port - controlled on board with jumper J8
171 #define CONFIG_SYS_NS16550_SERIAL
172 #define CONFIG_SYS_NS16550_REG_SIZE 1
173 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
175 #define CONFIG_SYS_BAUDRATE_TABLE \
176 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
180 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
181 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
189 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
190 #ifdef CONFIG_PHYS_64BIT
191 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
193 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
195 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
197 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
198 #ifdef CONFIG_PHYS_64BIT
199 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
201 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
203 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
206 * for slave u-boot IMAGE instored in master memory space,
207 * PHYS must be aligned based on the SIZE
209 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
210 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
211 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
212 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
214 * for slave UCODE and ENV instored in master memory space,
215 * PHYS must be aligned based on the SIZE
217 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
218 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
219 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
221 /* slave core release by master*/
222 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
223 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
226 * SRIO_PCIE_BOOT - SLAVE
228 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
229 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
230 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
231 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
235 * eSPI - Enhanced SPI
240 * Memory space is mapped 1-1, but I/O space must start from 0.
243 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
244 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
245 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
246 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
247 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
249 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
250 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
251 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
252 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
253 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
255 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
256 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
257 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
258 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
259 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
262 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
263 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
264 #ifdef CONFIG_PHYS_64BIT
265 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
267 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
269 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
270 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
271 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
272 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
273 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
274 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
275 CONFIG_SYS_BMAN_CENA_SIZE)
276 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
277 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
278 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
279 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
280 #ifdef CONFIG_PHYS_64BIT
281 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
283 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
285 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
286 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
287 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
288 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
289 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
290 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
291 CONFIG_SYS_QMAN_CENA_SIZE)
292 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
293 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
295 #define CONFIG_SYS_DPAA_FMAN
296 #define CONFIG_SYS_DPAA_PME
298 #ifdef CONFIG_FMAN_ENET
299 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
300 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
301 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
302 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
303 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
305 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
306 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
307 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
308 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
310 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
312 #define CONFIG_SYS_TBIPA_VALUE 8
318 #define CONFIG_LOADS_ECHO /* echo on for serial download */
319 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
322 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
326 * Miscellaneous configurable options
330 * For booting Linux, the board info and command line data
331 * have to be in the first 64 MB of memory, since this is
332 * the maximum mapped by the Linux kernel during initialization.
334 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
337 * Environment Configuration
339 #define CONFIG_ROOTPATH "/opt/nfsroot"
340 #define CONFIG_UBOOTPATH u-boot.bin
342 #define __USB_PHY_TYPE utmi
344 #define CONFIG_EXTRA_ENV_SETTINGS \
345 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
346 "bank_intlv=cs0_cs1\0" \
348 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
349 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
350 "tftpflash=tftpboot $loadaddr $uboot && " \
351 "protect off $ubootaddr +$filesize && " \
352 "erase $ubootaddr +$filesize && " \
353 "cp.b $loadaddr $ubootaddr $filesize && " \
354 "protect on $ubootaddr +$filesize && " \
355 "cmp.b $loadaddr $ubootaddr $filesize\0" \
356 "consoledev=ttyS0\0" \
357 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
358 "usb_dr_mode=host\0" \
359 "ramdiskaddr=2000000\0" \
360 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
361 "fdtaddr=1e00000\0" \
362 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
365 #include <asm/fsl_secure_boot.h>
367 #endif /* __CONFIG_H */