include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  29
  30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  32 #endif
  33
  34 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  35 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  36 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  37 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  38 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  39 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  40
  41 #define CONFIG_SYS_SRIO
  42 #define CONFIG_SRIO1                    /* SRIO port 1 */
  43 #define CONFIG_SRIO2                    /* SRIO port 2 */
  44 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  45 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  46
  47 #if defined(CONFIG_SPIFLASH)
  48 #elif defined(CONFIG_SDCARD)
  49         #define CONFIG_FSL_FIXED_MMC_LOCATION
  50 #endif
  51
  52 #ifndef __ASSEMBLY__
  53 unsigned long get_board_sys_clk(unsigned long dummy);
  54 #include <linux/stringify.h>
  55 #endif
  56 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  57
  58 /*
  59  * These can be toggled for performance analysis, otherwise use default.
  60  */
  61 #define CONFIG_SYS_CACHE_STASHING
  62 #define CONFIG_BACKSIDE_L2_CACHE
  63 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  64 #define CONFIG_BTB                      /* toggle branch predition */
  65
  66 #define CONFIG_ENABLE_36BIT_PHYS
  67
  68 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  69
  70 /*
  71  *  Config the L3 Cache as L3 SRAM
  72  */
  73 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  74 #ifdef CONFIG_PHYS_64BIT
  75 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  76                 CONFIG_RAMBOOT_TEXT_BASE)
  77 #else
  78 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  79 #endif
  80 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  81 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  82
  83 #ifdef CONFIG_PHYS_64BIT
  84 #define CONFIG_SYS_DCSRBAR              0xf0000000
  85 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  86 #endif
  87
  88 /* EEPROM */
  89 #define CONFIG_SYS_I2C_EEPROM_NXID
  90 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  91
  92 /*
  93  * DDR Setup
  94  */
  95 #define CONFIG_VERY_BIG_RAM
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  97 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  98
  99 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 100 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 101
 102 #define CONFIG_SYS_SPD_BUS_NUM  0
 103 #define SPD_EEPROM_ADDRESS      0x52
 104 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 105
 106 /*
 107  * Local Bus Definitions
 108  */
 109
 110 /* Set the local bus clock 1/8 of platform clock */
 111 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 112
 113 /*
 114  * This board doesn't have a promjet connector.
 115  * However, it uses commone corenet board LAW and TLB.
 116  * It is necessary to use the same start address with proper offset.
 117  */
 118 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 119 #ifdef CONFIG_PHYS_64BIT
 120 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 121 #else
 122 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 123 #endif
 124
 125 #define CONFIG_SYS_FLASH_BR_PRELIM \
 126                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 127                 BR_PS_16 | BR_V)
 128 #define CONFIG_SYS_FLASH_OR_PRELIM \
 129                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 130                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 131
 132 #define CONFIG_FSL_CPLD
 133 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 134 #ifdef CONFIG_PHYS_64BIT
 135 #define CPLD_BASE_PHYS          0xfffdf0000ull
 136 #else
 137 #define CPLD_BASE_PHYS          CPLD_BASE
 138 #endif
 139
 140 #define PIXIS_LBMAP_SWITCH      7
 141 #define PIXIS_LBMAP_MASK        0xf0
 142 #define PIXIS_LBMAP_SHIFT       4
 143 #define PIXIS_LBMAP_ALTBANK     0x40
 144
 145 #define CONFIG_SYS_FLASH_QUIET_TEST
 146 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 147
 148 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 149 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 150 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 151 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 152
 153 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 154
 155 #if defined(CONFIG_RAMBOOT_PBL)
 156 #define CONFIG_SYS_RAMBOOT
 157 #endif
 158
 159 /* Nand Flash */
 160 #ifdef CONFIG_NAND_FSL_ELBC
 161 #define CONFIG_SYS_NAND_BASE            0xffa00000
 162 #ifdef CONFIG_PHYS_64BIT
 163 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 164 #else
 165 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 166 #endif
 167
 168 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 169 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 170
 171 /* NAND flash config */
 172 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 173                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 174                                | BR_PS_8               /* Port Size = 8 bit */ \
 175                                | BR_MS_FCM             /* MSEL = FCM */ \
 176                                | BR_V)                 /* valid */
 177 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 178                                | OR_FCM_PGS            /* Large Page*/ \
 179                                | OR_FCM_CSCT \
 180                                | OR_FCM_CST \
 181                                | OR_FCM_CHT \
 182                                | OR_FCM_SCY_1 \
 183                                | OR_FCM_TRLX \
 184                                | OR_FCM_EHTR)
 185 #endif /* CONFIG_NAND_FSL_ELBC */
 186
 187 #define CONFIG_SYS_FLASH_EMPTY_INFO
 188 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 189
 190 #define CONFIG_HWCONFIG
 191
 192 /* define to use L1 as initial stack */
 193 #define CONFIG_L1_INIT_RAM
 194 #define CONFIG_SYS_INIT_RAM_LOCK
 195 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 196 #ifdef CONFIG_PHYS_64BIT
 197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 199 /* The assembler doesn't like typecast */
 200 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 201         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 202           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 203 #else
 204 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 205 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 206 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 207 #endif
 208 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 209
 210 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 211                                         GENERATED_GBL_DATA_SIZE)
 212 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 213
 214 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 215
 216 /* Serial Port - controlled on board with jumper J8
 217  * open - index 2
 218  * shorted - index 1
 219  */
 220 #define CONFIG_SYS_NS16550_SERIAL
 221 #define CONFIG_SYS_NS16550_REG_SIZE     1
 222 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 223
 224 #define CONFIG_SYS_BAUDRATE_TABLE       \
 225         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 226
 227 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 228 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 229 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 230 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 231
 232 /* I2C */
 233
 234
 235 /*
 236  * RapidIO
 237  */
 238 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 239 #ifdef CONFIG_PHYS_64BIT
 240 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 241 #else
 242 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 243 #endif
 244 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 245
 246 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 247 #ifdef CONFIG_PHYS_64BIT
 248 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 249 #else
 250 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 251 #endif
 252 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 253
 254 /*
 255  * for slave u-boot IMAGE instored in master memory space,
 256  * PHYS must be aligned based on the SIZE
 257  */
 258 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 259 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 260 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 261 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 262 /*
 263  * for slave UCODE and ENV instored in master memory space,
 264  * PHYS must be aligned based on the SIZE
 265  */
 266 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 267 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 268 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 269
 270 /* slave core release by master*/
 271 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 272 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 273
 274 /*
 275  * SRIO_PCIE_BOOT - SLAVE
 276  */
 277 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 278 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 279 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 280                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 281 #endif
 282
 283 /*
 284  * eSPI - Enhanced SPI
 285  */
 286
 287 /*
 288  * General PCI
 289  * Memory space is mapped 1-1, but I/O space must start from 0.
 290  */
 291
 292 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 293 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 294 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 295 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 296 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 297
 298 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 299 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 300 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 301 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 302 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 303
 304 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 305 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 306 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 307 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 308 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 309
 310 /* Qman/Bman */
 311 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 312 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 313 #ifdef CONFIG_PHYS_64BIT
 314 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 315 #else
 316 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 317 #endif
 318 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 319 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 320 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 321 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 322 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 323 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 324                                         CONFIG_SYS_BMAN_CENA_SIZE)
 325 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 326 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 327 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 328 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 329 #ifdef CONFIG_PHYS_64BIT
 330 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 331 #else
 332 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 333 #endif
 334 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 335 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 336 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 337 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 338 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 339 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 340                                         CONFIG_SYS_QMAN_CENA_SIZE)
 341 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 342 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 343
 344 #define CONFIG_SYS_DPAA_FMAN
 345 #define CONFIG_SYS_DPAA_PME
 346 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 347
 348 #ifdef CONFIG_PCI
 349 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 350 #endif  /* CONFIG_PCI */
 351
 352 /* SATA */
 353 #define CONFIG_FSL_SATA_V2
 354
 355 #ifdef CONFIG_FSL_SATA_V2
 356 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 357 #define CONFIG_SATA1
 358 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 359 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 360 #define CONFIG_SATA2
 361 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 362 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 363
 364 #define CONFIG_LBA48
 365 #endif
 366
 367 #ifdef CONFIG_FMAN_ENET
 368 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 369 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 370 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 371 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 372 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 373
 374 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 375 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 376 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 377 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 378
 379 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 380
 381 #define CONFIG_SYS_TBIPA_VALUE  8
 382 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 383 #endif
 384
 385 /*
 386  * Environment
 387  */
 388 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 389 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 390
 391 /*
 392 * USB
 393 */
 394 #define CONFIG_HAS_FSL_DR_USB
 395 #define CONFIG_HAS_FSL_MPH_USB
 396
 397 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 398 #define CONFIG_USB_EHCI_FSL
 399 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 400 #endif
 401
 402 #ifdef CONFIG_MMC
 403 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 404 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 405 #endif
 406
 407 /*
 408  * Miscellaneous configurable options
 409  */
 410
 411 /*
 412  * For booting Linux, the board info and command line data
 413  * have to be in the first 64 MB of memory, since this is
 414  * the maximum mapped by the Linux kernel during initialization.
 415  */
 416 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 417 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 418
 419 /*
 420  * Environment Configuration
 421  */
 422 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 423 #define CONFIG_BOOTFILE         "uImage"
 424 #define CONFIG_UBOOTPATH        u-boot.bin
 425
 426 #define __USB_PHY_TYPE  utmi
 427
 428 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 429         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 430         "bank_intlv=cs0_cs1\0"                                  \
 431         "netdev=eth0\0"                                         \
 432         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 433         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 434         "tftpflash=tftpboot $loadaddr $uboot && "               \
 435         "protect off $ubootaddr +$filesize && "                 \
 436         "erase $ubootaddr +$filesize && "                       \
 437         "cp.b $loadaddr $ubootaddr $filesize && "               \
 438         "protect on $ubootaddr +$filesize && "                  \
 439         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 440         "consoledev=ttyS0\0"                                    \
 441         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 442         "usb_dr_mode=host\0"                                    \
 443         "ramdiskaddr=2000000\0"                                 \
 444         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 445         "fdtaddr=1e00000\0"                                     \
 446         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 447         "bdev=sda3\0"
 448
 449 #include <asm/fsl_secure_boot.h>
 450
 451 #endif  /* __CONFIG_H */