include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  29
  30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  32 #endif
  33
  34 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  35 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  36 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  37 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  38 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  39
  40 #define CONFIG_SYS_SRIO
  41 #define CONFIG_SRIO1                    /* SRIO port 1 */
  42 #define CONFIG_SRIO2                    /* SRIO port 2 */
  43 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  44 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  45
  46 #if defined(CONFIG_SPIFLASH)
  47 #elif defined(CONFIG_SDCARD)
  48         #define CONFIG_FSL_FIXED_MMC_LOCATION
  49 #endif
  50
  51 #ifndef __ASSEMBLY__
  52 #include <linux/stringify.h>
  53 #endif
  54
  55 /*
  56  * These can be toggled for performance analysis, otherwise use default.
  57  */
  58 #define CONFIG_SYS_CACHE_STASHING
  59 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  60
  61 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  62
  63 /*
  64  *  Config the L3 Cache as L3 SRAM
  65  */
  66 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  67 #ifdef CONFIG_PHYS_64BIT
  68 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  69                 CONFIG_RAMBOOT_TEXT_BASE)
  70 #else
  71 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  72 #endif
  73 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  74 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  75
  76 #ifdef CONFIG_PHYS_64BIT
  77 #define CONFIG_SYS_DCSRBAR              0xf0000000
  78 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  79 #endif
  80
  81 /* EEPROM */
  82 #define CONFIG_SYS_I2C_EEPROM_NXID
  83 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  84
  85 /*
  86  * DDR Setup
  87  */
  88 #define CONFIG_VERY_BIG_RAM
  89 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  90 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  91
  92 #define SPD_EEPROM_ADDRESS      0x52
  93 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  94
  95 /*
  96  * Local Bus Definitions
  97  */
  98
  99 /* Set the local bus clock 1/8 of platform clock */
 100 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 101
 102 /*
 103  * This board doesn't have a promjet connector.
 104  * However, it uses commone corenet board LAW and TLB.
 105  * It is necessary to use the same start address with proper offset.
 106  */
 107 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 108 #ifdef CONFIG_PHYS_64BIT
 109 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 110 #else
 111 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 112 #endif
 113
 114 #define CONFIG_SYS_FLASH_BR_PRELIM \
 115                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 116                 BR_PS_16 | BR_V)
 117 #define CONFIG_SYS_FLASH_OR_PRELIM \
 118                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 119                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 120
 121 #define CONFIG_FSL_CPLD
 122 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 123 #ifdef CONFIG_PHYS_64BIT
 124 #define CPLD_BASE_PHYS          0xfffdf0000ull
 125 #else
 126 #define CPLD_BASE_PHYS          CPLD_BASE
 127 #endif
 128
 129 #define PIXIS_LBMAP_SWITCH      7
 130 #define PIXIS_LBMAP_MASK        0xf0
 131 #define PIXIS_LBMAP_SHIFT       4
 132 #define PIXIS_LBMAP_ALTBANK     0x40
 133
 134 #define CONFIG_SYS_FLASH_QUIET_TEST
 135 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 136
 137 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 138 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 139 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 140
 141 #if defined(CONFIG_RAMBOOT_PBL)
 142 #define CONFIG_SYS_RAMBOOT
 143 #endif
 144
 145 /* Nand Flash */
 146 #ifdef CONFIG_NAND_FSL_ELBC
 147 #define CONFIG_SYS_NAND_BASE            0xffa00000
 148 #ifdef CONFIG_PHYS_64BIT
 149 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 150 #else
 151 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 152 #endif
 153
 154 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 155 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 156
 157 /* NAND flash config */
 158 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 159                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 160                                | BR_PS_8               /* Port Size = 8 bit */ \
 161                                | BR_MS_FCM             /* MSEL = FCM */ \
 162                                | BR_V)                 /* valid */
 163 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 164                                | OR_FCM_PGS            /* Large Page*/ \
 165                                | OR_FCM_CSCT \
 166                                | OR_FCM_CST \
 167                                | OR_FCM_CHT \
 168                                | OR_FCM_SCY_1 \
 169                                | OR_FCM_TRLX \
 170                                | OR_FCM_EHTR)
 171 #endif /* CONFIG_NAND_FSL_ELBC */
 172
 173 #define CONFIG_SYS_FLASH_EMPTY_INFO
 174 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 175
 176 #define CONFIG_HWCONFIG
 177
 178 /* define to use L1 as initial stack */
 179 #define CONFIG_L1_INIT_RAM
 180 #define CONFIG_SYS_INIT_RAM_LOCK
 181 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 182 #ifdef CONFIG_PHYS_64BIT
 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 185 /* The assembler doesn't like typecast */
 186 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 187         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 188           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 189 #else
 190 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 192 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 193 #endif
 194 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 195
 196 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 197
 198 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 199
 200 /* Serial Port - controlled on board with jumper J8
 201  * open - index 2
 202  * shorted - index 1
 203  */
 204 #define CONFIG_SYS_NS16550_SERIAL
 205 #define CONFIG_SYS_NS16550_REG_SIZE     1
 206 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 207
 208 #define CONFIG_SYS_BAUDRATE_TABLE       \
 209         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 210
 211 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 212 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 213 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 214 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 215
 216 /* I2C */
 217
 218
 219 /*
 220  * RapidIO
 221  */
 222 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 223 #ifdef CONFIG_PHYS_64BIT
 224 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 225 #else
 226 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 227 #endif
 228 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 229
 230 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 231 #ifdef CONFIG_PHYS_64BIT
 232 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 233 #else
 234 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 235 #endif
 236 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 237
 238 /*
 239  * for slave u-boot IMAGE instored in master memory space,
 240  * PHYS must be aligned based on the SIZE
 241  */
 242 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 243 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 244 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 245 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 246 /*
 247  * for slave UCODE and ENV instored in master memory space,
 248  * PHYS must be aligned based on the SIZE
 249  */
 250 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 251 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 252 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 253
 254 /* slave core release by master*/
 255 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 256 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 257
 258 /*
 259  * SRIO_PCIE_BOOT - SLAVE
 260  */
 261 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 262 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 263 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 264                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 265 #endif
 266
 267 /*
 268  * eSPI - Enhanced SPI
 269  */
 270
 271 /*
 272  * General PCI
 273  * Memory space is mapped 1-1, but I/O space must start from 0.
 274  */
 275
 276 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 277 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 278 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 279 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 280 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 281
 282 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 283 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 284 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 285 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 286 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 287
 288 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 289 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 290 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 291 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 292 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 293
 294 /* Qman/Bman */
 295 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 296 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 297 #ifdef CONFIG_PHYS_64BIT
 298 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 299 #else
 300 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 301 #endif
 302 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 303 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 304 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 305 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 306 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 307 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 308                                         CONFIG_SYS_BMAN_CENA_SIZE)
 309 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 310 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 311 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 312 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 313 #ifdef CONFIG_PHYS_64BIT
 314 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 315 #else
 316 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 317 #endif
 318 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 319 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 320 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 321 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 322 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 323 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 324                                         CONFIG_SYS_QMAN_CENA_SIZE)
 325 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 326 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 327
 328 #define CONFIG_SYS_DPAA_FMAN
 329 #define CONFIG_SYS_DPAA_PME
 330 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 331
 332 #ifdef CONFIG_PCI
 333 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 334 #endif  /* CONFIG_PCI */
 335
 336 #ifdef CONFIG_FMAN_ENET
 337 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 338 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 339 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 340 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 341 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 342
 343 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 344 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 345 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 346 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 347
 348 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 349
 350 #define CONFIG_SYS_TBIPA_VALUE  8
 351 #endif
 352
 353 /*
 354  * Environment
 355  */
 356 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 357 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 358
 359 #ifdef CONFIG_MMC
 360 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 361 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 362 #endif
 363
 364 /*
 365  * Miscellaneous configurable options
 366  */
 367
 368 /*
 369  * For booting Linux, the board info and command line data
 370  * have to be in the first 64 MB of memory, since this is
 371  * the maximum mapped by the Linux kernel during initialization.
 372  */
 373 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 374 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 375
 376 /*
 377  * Environment Configuration
 378  */
 379 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 380 #define CONFIG_UBOOTPATH        u-boot.bin
 381
 382 #define __USB_PHY_TYPE  utmi
 383
 384 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 385         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 386         "bank_intlv=cs0_cs1\0"                                  \
 387         "netdev=eth0\0"                                         \
 388         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 389         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 390         "tftpflash=tftpboot $loadaddr $uboot && "               \
 391         "protect off $ubootaddr +$filesize && "                 \
 392         "erase $ubootaddr +$filesize && "                       \
 393         "cp.b $loadaddr $ubootaddr $filesize && "               \
 394         "protect on $ubootaddr +$filesize && "                  \
 395         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 396         "consoledev=ttyS0\0"                                    \
 397         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 398         "usb_dr_mode=host\0"                                    \
 399         "ramdiskaddr=2000000\0"                                 \
 400         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 401         "fdtaddr=1e00000\0"                                     \
 402         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 403         "bdev=sda3\0"
 404
 405 #include <asm/fsl_secure_boot.h>
 406
 407 #endif  /* __CONFIG_H */