include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28
  29 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  30 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  31 #endif
  32
  33 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  34
  35 #define CONFIG_SYS_SRIO
  36 #define CONFIG_SRIO1                    /* SRIO port 1 */
  37 #define CONFIG_SRIO2                    /* SRIO port 2 */
  38 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  39 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  40
  41 #ifndef __ASSEMBLY__
  42 #include <linux/stringify.h>
  43 #endif
  44
  45 /*
  46  * These can be toggled for performance analysis, otherwise use default.
  47  */
  48 #define CONFIG_SYS_CACHE_STASHING
  49 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  50
  51 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  52
  53 /*
  54  *  Config the L3 Cache as L3 SRAM
  55  */
  56 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  57 #ifdef CONFIG_PHYS_64BIT
  58 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  59                 CONFIG_RAMBOOT_TEXT_BASE)
  60 #else
  61 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  62 #endif
  63 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  64 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  65
  66 #ifdef CONFIG_PHYS_64BIT
  67 #define CONFIG_SYS_DCSRBAR              0xf0000000
  68 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  69 #endif
  70
  71 /* EEPROM */
  72 #define CONFIG_SYS_I2C_EEPROM_NXID
  73 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  74
  75 /*
  76  * DDR Setup
  77  */
  78 #define CONFIG_VERY_BIG_RAM
  79 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  80 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  81
  82 #define SPD_EEPROM_ADDRESS      0x52
  83 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  84
  85 /*
  86  * Local Bus Definitions
  87  */
  88
  89 /* Set the local bus clock 1/8 of platform clock */
  90 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  91
  92 /*
  93  * This board doesn't have a promjet connector.
  94  * However, it uses commone corenet board LAW and TLB.
  95  * It is necessary to use the same start address with proper offset.
  96  */
  97 #define CONFIG_SYS_FLASH_BASE           0xe0000000
  98 #ifdef CONFIG_PHYS_64BIT
  99 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 100 #else
 101 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 102 #endif
 103
 104 #define CONFIG_SYS_FLASH_BR_PRELIM \
 105                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 106                 BR_PS_16 | BR_V)
 107 #define CONFIG_SYS_FLASH_OR_PRELIM \
 108                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 109                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 110
 111 #define CONFIG_FSL_CPLD
 112 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 113 #ifdef CONFIG_PHYS_64BIT
 114 #define CPLD_BASE_PHYS          0xfffdf0000ull
 115 #else
 116 #define CPLD_BASE_PHYS          CPLD_BASE
 117 #endif
 118
 119 #define PIXIS_LBMAP_SWITCH      7
 120 #define PIXIS_LBMAP_MASK        0xf0
 121 #define PIXIS_LBMAP_SHIFT       4
 122 #define PIXIS_LBMAP_ALTBANK     0x40
 123
 124 #define CONFIG_SYS_FLASH_QUIET_TEST
 125 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 126
 127 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 128 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 129 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 130
 131 /* Nand Flash */
 132 #ifdef CONFIG_NAND_FSL_ELBC
 133 #define CONFIG_SYS_NAND_BASE            0xffa00000
 134 #ifdef CONFIG_PHYS_64BIT
 135 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 136 #else
 137 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 138 #endif
 139
 140 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 141 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 142
 143 /* NAND flash config */
 144 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 145                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 146                                | BR_PS_8               /* Port Size = 8 bit */ \
 147                                | BR_MS_FCM             /* MSEL = FCM */ \
 148                                | BR_V)                 /* valid */
 149 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 150                                | OR_FCM_PGS            /* Large Page*/ \
 151                                | OR_FCM_CSCT \
 152                                | OR_FCM_CST \
 153                                | OR_FCM_CHT \
 154                                | OR_FCM_SCY_1 \
 155                                | OR_FCM_TRLX \
 156                                | OR_FCM_EHTR)
 157 #endif /* CONFIG_NAND_FSL_ELBC */
 158
 159 #define CONFIG_SYS_FLASH_EMPTY_INFO
 160 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 161
 162 #define CONFIG_HWCONFIG
 163
 164 /* define to use L1 as initial stack */
 165 #define CONFIG_L1_INIT_RAM
 166 #define CONFIG_SYS_INIT_RAM_LOCK
 167 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 168 #ifdef CONFIG_PHYS_64BIT
 169 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 171 /* The assembler doesn't like typecast */
 172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 173         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 174           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 175 #else
 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 177 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 179 #endif
 180 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 181
 182 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 183
 184 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 185
 186 /* Serial Port - controlled on board with jumper J8
 187  * open - index 2
 188  * shorted - index 1
 189  */
 190 #define CONFIG_SYS_NS16550_SERIAL
 191 #define CONFIG_SYS_NS16550_REG_SIZE     1
 192 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 193
 194 #define CONFIG_SYS_BAUDRATE_TABLE       \
 195         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 196
 197 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 198 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 199 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 200 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 201
 202 /* I2C */
 203
 204
 205 /*
 206  * RapidIO
 207  */
 208 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 209 #ifdef CONFIG_PHYS_64BIT
 210 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 211 #else
 212 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 213 #endif
 214 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 215
 216 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 217 #ifdef CONFIG_PHYS_64BIT
 218 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 219 #else
 220 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 221 #endif
 222 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 223
 224 /*
 225  * for slave u-boot IMAGE instored in master memory space,
 226  * PHYS must be aligned based on the SIZE
 227  */
 228 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 229 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 230 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 231 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 232 /*
 233  * for slave UCODE and ENV instored in master memory space,
 234  * PHYS must be aligned based on the SIZE
 235  */
 236 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 237 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 238 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 239
 240 /* slave core release by master*/
 241 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 242 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 243
 244 /*
 245  * SRIO_PCIE_BOOT - SLAVE
 246  */
 247 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 248 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 249 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 250                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 251 #endif
 252
 253 /*
 254  * eSPI - Enhanced SPI
 255  */
 256
 257 /*
 258  * General PCI
 259  * Memory space is mapped 1-1, but I/O space must start from 0.
 260  */
 261
 262 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 263 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 264 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 265 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 266 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 267
 268 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 269 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 270 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 271 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 272 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 273
 274 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 275 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 276 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 277 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 278 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 279
 280 /* Qman/Bman */
 281 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 282 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 283 #ifdef CONFIG_PHYS_64BIT
 284 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 285 #else
 286 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 287 #endif
 288 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 289 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 290 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 291 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 292 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 293 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 294                                         CONFIG_SYS_BMAN_CENA_SIZE)
 295 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 296 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 297 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 298 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 299 #ifdef CONFIG_PHYS_64BIT
 300 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 301 #else
 302 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 303 #endif
 304 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 305 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 306 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 307 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 308 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 309 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 310                                         CONFIG_SYS_QMAN_CENA_SIZE)
 311 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 312 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 313
 314 #define CONFIG_SYS_DPAA_FMAN
 315 #define CONFIG_SYS_DPAA_PME
 316 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 317
 318 #ifdef CONFIG_FMAN_ENET
 319 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 320 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 321 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 322 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 323 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 324
 325 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 326 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 327 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 328 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 329
 330 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 331
 332 #define CONFIG_SYS_TBIPA_VALUE  8
 333 #endif
 334
 335 /*
 336  * Environment
 337  */
 338 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 339 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 340
 341 #ifdef CONFIG_MMC
 342 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 343 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 344 #endif
 345
 346 /*
 347  * Miscellaneous configurable options
 348  */
 349
 350 /*
 351  * For booting Linux, the board info and command line data
 352  * have to be in the first 64 MB of memory, since this is
 353  * the maximum mapped by the Linux kernel during initialization.
 354  */
 355 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 356
 357 /*
 358  * Environment Configuration
 359  */
 360 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 361 #define CONFIG_UBOOTPATH        u-boot.bin
 362
 363 #define __USB_PHY_TYPE  utmi
 364
 365 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 366         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 367         "bank_intlv=cs0_cs1\0"                                  \
 368         "netdev=eth0\0"                                         \
 369         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 370         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 371         "tftpflash=tftpboot $loadaddr $uboot && "               \
 372         "protect off $ubootaddr +$filesize && "                 \
 373         "erase $ubootaddr +$filesize && "                       \
 374         "cp.b $loadaddr $ubootaddr $filesize && "               \
 375         "protect on $ubootaddr +$filesize && "                  \
 376         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 377         "consoledev=ttyS0\0"                                    \
 378         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 379         "usb_dr_mode=host\0"                                    \
 380         "ramdiskaddr=2000000\0"                                 \
 381         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 382         "fdtaddr=1e00000\0"                                     \
 383         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 384         "bdev=sda3\0"
 385
 386 #include <asm/fsl_secure_boot.h>
 387
 388 #endif  /* __CONFIG_H */