include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  29
  30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  32 #endif
  33
  34 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  35 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  36 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  37 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  38 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  39
  40 #define CONFIG_SYS_SRIO
  41 #define CONFIG_SRIO1                    /* SRIO port 1 */
  42 #define CONFIG_SRIO2                    /* SRIO port 2 */
  43 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  44 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  45
  46 #if defined(CONFIG_SPIFLASH)
  47 #elif defined(CONFIG_SDCARD)
  48         #define CONFIG_FSL_FIXED_MMC_LOCATION
  49 #endif
  50
  51 #ifndef __ASSEMBLY__
  52 #include <linux/stringify.h>
  53 #endif
  54
  55 /*
  56  * These can be toggled for performance analysis, otherwise use default.
  57  */
  58 #define CONFIG_SYS_CACHE_STASHING
  59 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  60
  61 #define CONFIG_ENABLE_36BIT_PHYS
  62
  63 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  64
  65 /*
  66  *  Config the L3 Cache as L3 SRAM
  67  */
  68 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  69 #ifdef CONFIG_PHYS_64BIT
  70 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  71                 CONFIG_RAMBOOT_TEXT_BASE)
  72 #else
  73 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  74 #endif
  75 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  76 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  77
  78 #ifdef CONFIG_PHYS_64BIT
  79 #define CONFIG_SYS_DCSRBAR              0xf0000000
  80 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  81 #endif
  82
  83 /* EEPROM */
  84 #define CONFIG_SYS_I2C_EEPROM_NXID
  85 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  86
  87 /*
  88  * DDR Setup
  89  */
  90 #define CONFIG_VERY_BIG_RAM
  91 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  92 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  93
  94 #define CONFIG_SYS_SPD_BUS_NUM  0
  95 #define SPD_EEPROM_ADDRESS      0x52
  96 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  97
  98 /*
  99  * Local Bus Definitions
 100  */
 101
 102 /* Set the local bus clock 1/8 of platform clock */
 103 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 104
 105 /*
 106  * This board doesn't have a promjet connector.
 107  * However, it uses commone corenet board LAW and TLB.
 108  * It is necessary to use the same start address with proper offset.
 109  */
 110 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 111 #ifdef CONFIG_PHYS_64BIT
 112 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 113 #else
 114 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 115 #endif
 116
 117 #define CONFIG_SYS_FLASH_BR_PRELIM \
 118                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 119                 BR_PS_16 | BR_V)
 120 #define CONFIG_SYS_FLASH_OR_PRELIM \
 121                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 122                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 123
 124 #define CONFIG_FSL_CPLD
 125 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 126 #ifdef CONFIG_PHYS_64BIT
 127 #define CPLD_BASE_PHYS          0xfffdf0000ull
 128 #else
 129 #define CPLD_BASE_PHYS          CPLD_BASE
 130 #endif
 131
 132 #define PIXIS_LBMAP_SWITCH      7
 133 #define PIXIS_LBMAP_MASK        0xf0
 134 #define PIXIS_LBMAP_SHIFT       4
 135 #define PIXIS_LBMAP_ALTBANK     0x40
 136
 137 #define CONFIG_SYS_FLASH_QUIET_TEST
 138 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 139
 140 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 141 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 142 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 143
 144 #if defined(CONFIG_RAMBOOT_PBL)
 145 #define CONFIG_SYS_RAMBOOT
 146 #endif
 147
 148 /* Nand Flash */
 149 #ifdef CONFIG_NAND_FSL_ELBC
 150 #define CONFIG_SYS_NAND_BASE            0xffa00000
 151 #ifdef CONFIG_PHYS_64BIT
 152 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 153 #else
 154 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 155 #endif
 156
 157 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 158 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 159
 160 /* NAND flash config */
 161 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 162                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 163                                | BR_PS_8               /* Port Size = 8 bit */ \
 164                                | BR_MS_FCM             /* MSEL = FCM */ \
 165                                | BR_V)                 /* valid */
 166 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 167                                | OR_FCM_PGS            /* Large Page*/ \
 168                                | OR_FCM_CSCT \
 169                                | OR_FCM_CST \
 170                                | OR_FCM_CHT \
 171                                | OR_FCM_SCY_1 \
 172                                | OR_FCM_TRLX \
 173                                | OR_FCM_EHTR)
 174 #endif /* CONFIG_NAND_FSL_ELBC */
 175
 176 #define CONFIG_SYS_FLASH_EMPTY_INFO
 177 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 178
 179 #define CONFIG_HWCONFIG
 180
 181 /* define to use L1 as initial stack */
 182 #define CONFIG_L1_INIT_RAM
 183 #define CONFIG_SYS_INIT_RAM_LOCK
 184 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 185 #ifdef CONFIG_PHYS_64BIT
 186 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 187 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 188 /* The assembler doesn't like typecast */
 189 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 190         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 191           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 192 #else
 193 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 196 #endif
 197 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 198
 199 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 200                                         GENERATED_GBL_DATA_SIZE)
 201 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 202
 203 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 204
 205 /* Serial Port - controlled on board with jumper J8
 206  * open - index 2
 207  * shorted - index 1
 208  */
 209 #define CONFIG_SYS_NS16550_SERIAL
 210 #define CONFIG_SYS_NS16550_REG_SIZE     1
 211 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 212
 213 #define CONFIG_SYS_BAUDRATE_TABLE       \
 214         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 215
 216 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 217 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 218 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 219 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 220
 221 /* I2C */
 222
 223
 224 /*
 225  * RapidIO
 226  */
 227 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 228 #ifdef CONFIG_PHYS_64BIT
 229 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 230 #else
 231 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 232 #endif
 233 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 234
 235 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 236 #ifdef CONFIG_PHYS_64BIT
 237 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 238 #else
 239 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 240 #endif
 241 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 242
 243 /*
 244  * for slave u-boot IMAGE instored in master memory space,
 245  * PHYS must be aligned based on the SIZE
 246  */
 247 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 248 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 249 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 250 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 251 /*
 252  * for slave UCODE and ENV instored in master memory space,
 253  * PHYS must be aligned based on the SIZE
 254  */
 255 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 256 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 257 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 258
 259 /* slave core release by master*/
 260 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 261 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 262
 263 /*
 264  * SRIO_PCIE_BOOT - SLAVE
 265  */
 266 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 267 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 268 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 269                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 270 #endif
 271
 272 /*
 273  * eSPI - Enhanced SPI
 274  */
 275
 276 /*
 277  * General PCI
 278  * Memory space is mapped 1-1, but I/O space must start from 0.
 279  */
 280
 281 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 282 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 283 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 284 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 285 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 286
 287 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 288 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 289 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 290 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 291 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 292
 293 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 294 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 295 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 296 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 297 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 298
 299 /* Qman/Bman */
 300 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 301 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 302 #ifdef CONFIG_PHYS_64BIT
 303 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 304 #else
 305 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 306 #endif
 307 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 308 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 309 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 310 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 311 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 312 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 313                                         CONFIG_SYS_BMAN_CENA_SIZE)
 314 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 315 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 316 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 317 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 318 #ifdef CONFIG_PHYS_64BIT
 319 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 320 #else
 321 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 322 #endif
 323 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 324 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 325 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 326 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 327 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 328 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 329                                         CONFIG_SYS_QMAN_CENA_SIZE)
 330 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 331 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 332
 333 #define CONFIG_SYS_DPAA_FMAN
 334 #define CONFIG_SYS_DPAA_PME
 335 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 336
 337 #ifdef CONFIG_PCI
 338 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 339 #endif  /* CONFIG_PCI */
 340
 341 /* SATA */
 342 #define CONFIG_FSL_SATA_V2
 343
 344 #ifdef CONFIG_FSL_SATA_V2
 345 #define CONFIG_SATA1
 346 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 347 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 348 #define CONFIG_SATA2
 349 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 350 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 351
 352 #define CONFIG_LBA48
 353 #endif
 354
 355 #ifdef CONFIG_FMAN_ENET
 356 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 357 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 358 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 359 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 360 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 361
 362 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 363 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 364 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 365 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 366
 367 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 368
 369 #define CONFIG_SYS_TBIPA_VALUE  8
 370 #endif
 371
 372 /*
 373  * Environment
 374  */
 375 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 376 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 377
 378 /*
 379 * USB
 380 */
 381 #define CONFIG_HAS_FSL_DR_USB
 382 #define CONFIG_HAS_FSL_MPH_USB
 383
 384 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 385 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 386 #endif
 387
 388 #ifdef CONFIG_MMC
 389 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 390 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 391 #endif
 392
 393 /*
 394  * Miscellaneous configurable options
 395  */
 396
 397 /*
 398  * For booting Linux, the board info and command line data
 399  * have to be in the first 64 MB of memory, since this is
 400  * the maximum mapped by the Linux kernel during initialization.
 401  */
 402 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 403 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 404
 405 /*
 406  * Environment Configuration
 407  */
 408 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 409 #define CONFIG_UBOOTPATH        u-boot.bin
 410
 411 #define __USB_PHY_TYPE  utmi
 412
 413 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 414         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 415         "bank_intlv=cs0_cs1\0"                                  \
 416         "netdev=eth0\0"                                         \
 417         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 418         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 419         "tftpflash=tftpboot $loadaddr $uboot && "               \
 420         "protect off $ubootaddr +$filesize && "                 \
 421         "erase $ubootaddr +$filesize && "                       \
 422         "cp.b $loadaddr $ubootaddr $filesize && "               \
 423         "protect on $ubootaddr +$filesize && "                  \
 424         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 425         "consoledev=ttyS0\0"                                    \
 426         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 427         "usb_dr_mode=host\0"                                    \
 428         "ramdiskaddr=2000000\0"                                 \
 429         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 430         "fdtaddr=1e00000\0"                                     \
 431         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 432         "bdev=sda3\0"
 433
 434 #include <asm/fsl_secure_boot.h>
 435
 436 #endif  /* __CONFIG_H */