Merge branch 'master' of git://git.denx.de/u-boot-usb
[platform/kernel/u-boot.git] / include / configs / P2041RDB.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * P2041 RDB board configuration file
9  * Also supports P2040 RDB
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #define CONFIG_P2041RDB
15 #define CONFIG_PHYS_64BIT
16 #define CONFIG_SYS_GENERIC_BOARD
17 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_PPC_P2041
19
20 #ifdef CONFIG_RAMBOOT_PBL
21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
23 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
24 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
25 #endif
26
27 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
28 /* Set 1M boot space */
29 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
30 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
31                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
33 #define CONFIG_SYS_NO_FLASH
34 #endif
35
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE
38 #define CONFIG_E500                     /* BOOKE e500 family */
39 #define CONFIG_E500MC                   /* BOOKE e500mc family */
40 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
41 #define CONFIG_MP                       /* support multiple processors */
42
43 #ifndef CONFIG_SYS_TEXT_BASE
44 #define CONFIG_SYS_TEXT_BASE    0xeff40000
45 #endif
46
47 #ifndef CONFIG_RESET_VECTOR_ADDRESS
48 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
49 #endif
50
51 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
52 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
53 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
54 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
55 #define CONFIG_PCI                      /* Enable PCI/PCIE */
56 #define CONFIG_PCIE1                    /* PCIE controler 1 */
57 #define CONFIG_PCIE2                    /* PCIE controler 2 */
58 #define CONFIG_PCIE3                    /* PCIE controler 3 */
59 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
60 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
61
62 #define CONFIG_SYS_SRIO
63 #define CONFIG_SRIO1                    /* SRIO port 1 */
64 #define CONFIG_SRIO2                    /* SRIO port 2 */
65 #define CONFIG_SRIO_PCIE_BOOT_MASTER
66 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
67
68 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
69
70 #define CONFIG_ENV_OVERWRITE
71
72 #ifdef CONFIG_SYS_NO_FLASH
73 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
74 #define CONFIG_ENV_IS_NOWHERE
75 #endif
76 #else
77 #define CONFIG_FLASH_CFI_DRIVER
78 #define CONFIG_SYS_FLASH_CFI
79 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
80 #endif
81
82 #if defined(CONFIG_SPIFLASH)
83         #define CONFIG_SYS_EXTRA_ENV_RELOC
84         #define CONFIG_ENV_IS_IN_SPI_FLASH
85         #define CONFIG_ENV_SPI_BUS              0
86         #define CONFIG_ENV_SPI_CS               0
87         #define CONFIG_ENV_SPI_MAX_HZ           10000000
88         #define CONFIG_ENV_SPI_MODE             0
89         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
90         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
91         #define CONFIG_ENV_SECT_SIZE            0x10000
92 #elif defined(CONFIG_SDCARD)
93         #define CONFIG_SYS_EXTRA_ENV_RELOC
94         #define CONFIG_ENV_IS_IN_MMC
95         #define CONFIG_FSL_FIXED_MMC_LOCATION
96         #define CONFIG_SYS_MMC_ENV_DEV          0
97         #define CONFIG_ENV_SIZE                 0x2000
98         #define CONFIG_ENV_OFFSET               (512 * 1658)
99 #elif defined(CONFIG_NAND)
100 #define CONFIG_SYS_EXTRA_ENV_RELOC
101 #define CONFIG_ENV_IS_IN_NAND
102 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
103 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
104 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
105 #define CONFIG_ENV_IS_IN_REMOTE
106 #define CONFIG_ENV_ADDR         0xffe20000
107 #define CONFIG_ENV_SIZE         0x2000
108 #elif defined(CONFIG_ENV_IS_NOWHERE)
109 #define CONFIG_ENV_SIZE         0x2000
110 #else
111         #define CONFIG_ENV_IS_IN_FLASH
112         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
113                         - CONFIG_ENV_SECT_SIZE)
114         #define CONFIG_ENV_SIZE         0x2000
115         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
116 #endif
117
118 #ifndef __ASSEMBLY__
119 unsigned long get_board_sys_clk(unsigned long dummy);
120 #endif
121 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
122
123 /*
124  * These can be toggled for performance analysis, otherwise use default.
125  */
126 #define CONFIG_SYS_CACHE_STASHING
127 #define CONFIG_BACKSIDE_L2_CACHE
128 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
129 #define CONFIG_BTB                      /* toggle branch predition */
130
131 #define CONFIG_ENABLE_36BIT_PHYS
132
133 #ifdef CONFIG_PHYS_64BIT
134 #define CONFIG_ADDR_MAP
135 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
136 #endif
137
138 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
139 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
140 #define CONFIG_SYS_MEMTEST_END          0x00400000
141 #define CONFIG_SYS_ALT_MEMTEST
142 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
143
144 /*
145  *  Config the L3 Cache as L3 SRAM
146  */
147 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
148 #ifdef CONFIG_PHYS_64BIT
149 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
150                 CONFIG_RAMBOOT_TEXT_BASE)
151 #else
152 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
153 #endif
154 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
155 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
156
157 #ifdef CONFIG_PHYS_64BIT
158 #define CONFIG_SYS_DCSRBAR              0xf0000000
159 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
160 #endif
161
162 /* EEPROM */
163 #define CONFIG_ID_EEPROM
164 #define CONFIG_SYS_I2C_EEPROM_NXID
165 #define CONFIG_SYS_EEPROM_BUS_NUM       0
166 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
167 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
168
169 /*
170  * DDR Setup
171  */
172 #define CONFIG_VERY_BIG_RAM
173 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
174 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
175
176 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
177 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
178
179 #define CONFIG_DDR_SPD
180 #define CONFIG_SYS_FSL_DDR3
181
182 #define CONFIG_SYS_SPD_BUS_NUM  0
183 #define SPD_EEPROM_ADDRESS      0x52
184 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
185
186 /*
187  * Local Bus Definitions
188  */
189
190 /* Set the local bus clock 1/8 of platform clock */
191 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
192
193 /*
194  * This board doesn't have a promjet connector.
195  * However, it uses commone corenet board LAW and TLB.
196  * It is necessary to use the same start address with proper offset.
197  */
198 #define CONFIG_SYS_FLASH_BASE           0xe0000000
199 #ifdef CONFIG_PHYS_64BIT
200 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
201 #else
202 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
203 #endif
204
205 #define CONFIG_SYS_FLASH_BR_PRELIM \
206                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
207                 BR_PS_16 | BR_V)
208 #define CONFIG_SYS_FLASH_OR_PRELIM \
209                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
210                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
211
212 #define CONFIG_FSL_CPLD
213 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
214 #ifdef CONFIG_PHYS_64BIT
215 #define CPLD_BASE_PHYS          0xfffdf0000ull
216 #else
217 #define CPLD_BASE_PHYS          CPLD_BASE
218 #endif
219
220 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
221 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
222
223 #define PIXIS_LBMAP_SWITCH      7
224 #define PIXIS_LBMAP_MASK        0xf0
225 #define PIXIS_LBMAP_SHIFT       4
226 #define PIXIS_LBMAP_ALTBANK     0x40
227
228 #define CONFIG_SYS_FLASH_QUIET_TEST
229 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
230
231 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
232 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
233 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
234 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
235
236 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
237
238 #if defined(CONFIG_RAMBOOT_PBL)
239 #define CONFIG_SYS_RAMBOOT
240 #endif
241
242 #define CONFIG_NAND_FSL_ELBC
243 /* Nand Flash */
244 #ifdef CONFIG_NAND_FSL_ELBC
245 #define CONFIG_SYS_NAND_BASE            0xffa00000
246 #ifdef CONFIG_PHYS_64BIT
247 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
248 #else
249 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
250 #endif
251
252 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
253 #define CONFIG_SYS_MAX_NAND_DEVICE      1
254 #define CONFIG_MTD_NAND_VERIFY_WRITE
255 #define CONFIG_CMD_NAND
256 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
257
258 /* NAND flash config */
259 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
260                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
261                                | BR_PS_8               /* Port Size = 8 bit */ \
262                                | BR_MS_FCM             /* MSEL = FCM */ \
263                                | BR_V)                 /* valid */
264 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
265                                | OR_FCM_PGS            /* Large Page*/ \
266                                | OR_FCM_CSCT \
267                                | OR_FCM_CST \
268                                | OR_FCM_CHT \
269                                | OR_FCM_SCY_1 \
270                                | OR_FCM_TRLX \
271                                | OR_FCM_EHTR)
272
273 #ifdef CONFIG_NAND
274 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
275 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
276 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
277 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
278 #else
279 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
280 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
281 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
282 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
283 #endif
284 #else
285 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
286 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
287 #endif /* CONFIG_NAND_FSL_ELBC */
288
289 #define CONFIG_SYS_FLASH_EMPTY_INFO
290 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
291 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
292
293 #define CONFIG_BOARD_EARLY_INIT_F
294 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
295 #define CONFIG_MISC_INIT_R
296
297 #define CONFIG_HWCONFIG
298
299 /* define to use L1 as initial stack */
300 #define CONFIG_L1_INIT_RAM
301 #define CONFIG_SYS_INIT_RAM_LOCK
302 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
303 #ifdef CONFIG_PHYS_64BIT
304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
306 /* The assembler doesn't like typecast */
307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
308         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
309           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
310 #else
311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
314 #endif
315 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
316
317 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
318                                         GENERATED_GBL_DATA_SIZE)
319 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
320
321 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
322 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
323
324 /* Serial Port - controlled on board with jumper J8
325  * open - index 2
326  * shorted - index 1
327  */
328 #define CONFIG_CONS_INDEX       1
329 #define CONFIG_SYS_NS16550
330 #define CONFIG_SYS_NS16550_SERIAL
331 #define CONFIG_SYS_NS16550_REG_SIZE     1
332 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
333
334 #define CONFIG_SYS_BAUDRATE_TABLE       \
335         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
336
337 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
338 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
339 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
340 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
341
342 /* Use the HUSH parser */
343 #define CONFIG_SYS_HUSH_PARSER
344
345 /* pass open firmware flat tree */
346 #define CONFIG_OF_LIBFDT
347 #define CONFIG_OF_BOARD_SETUP
348 #define CONFIG_OF_STDOUT_VIA_ALIAS
349
350 /* new uImage format support */
351 #define CONFIG_FIT
352 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
353
354 /* I2C */
355 #define CONFIG_SYS_I2C
356 #define CONFIG_SYS_I2C_FSL
357 #define CONFIG_SYS_FSL_I2C_SPEED        400000
358 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
359 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
360 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
361 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
362 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
363
364 /*
365  * RapidIO
366  */
367 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
368 #ifdef CONFIG_PHYS_64BIT
369 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
370 #else
371 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
372 #endif
373 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
374
375 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
376 #ifdef CONFIG_PHYS_64BIT
377 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
378 #else
379 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
380 #endif
381 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
382
383 /*
384  * for slave u-boot IMAGE instored in master memory space,
385  * PHYS must be aligned based on the SIZE
386  */
387 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
388 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
389 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
390 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
391 /*
392  * for slave UCODE and ENV instored in master memory space,
393  * PHYS must be aligned based on the SIZE
394  */
395 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
396 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
397 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
398
399 /* slave core release by master*/
400 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
401 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
402
403 /*
404  * SRIO_PCIE_BOOT - SLAVE
405  */
406 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
407 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
408 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
409                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
410 #endif
411
412 /*
413  * eSPI - Enhanced SPI
414  */
415 #define CONFIG_FSL_ESPI
416 #define CONFIG_SPI_FLASH
417 #define CONFIG_SPI_FLASH_SPANSION
418 #define CONFIG_CMD_SF
419 #define CONFIG_SF_DEFAULT_SPEED         10000000
420 #define CONFIG_SF_DEFAULT_MODE          0
421
422 /*
423  * General PCI
424  * Memory space is mapped 1-1, but I/O space must start from 0.
425  */
426
427 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
428 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
429 #ifdef CONFIG_PHYS_64BIT
430 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
431 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
432 #else
433 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
434 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
435 #endif
436 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
437 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
438 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
439 #ifdef CONFIG_PHYS_64BIT
440 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
441 #else
442 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
443 #endif
444 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
445
446 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
447 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
448 #ifdef CONFIG_PHYS_64BIT
449 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
450 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
451 #else
452 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
453 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
454 #endif
455 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
456 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
457 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
458 #ifdef CONFIG_PHYS_64BIT
459 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
460 #else
461 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
462 #endif
463 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
464
465 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
466 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
467 #ifdef CONFIG_PHYS_64BIT
468 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
469 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
470 #else
471 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
472 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
473 #endif
474 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
475 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
476 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
477 #ifdef CONFIG_PHYS_64BIT
478 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
479 #else
480 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
481 #endif
482 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
483
484 /* Qman/Bman */
485 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
486 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
487 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
488 #ifdef CONFIG_PHYS_64BIT
489 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
490 #else
491 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
492 #endif
493 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
494 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
495 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
496 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
497 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
498 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
499                                         CONFIG_SYS_BMAN_CENA_SIZE)
500 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
501 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
502 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
503 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
504 #ifdef CONFIG_PHYS_64BIT
505 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
506 #else
507 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
508 #endif
509 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
510 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
511 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
512 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
513 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
514 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
515                                         CONFIG_SYS_QMAN_CENA_SIZE)
516 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
517 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
518
519 #define CONFIG_SYS_DPAA_FMAN
520 #define CONFIG_SYS_DPAA_PME
521 /* Default address of microcode for the Linux Fman driver */
522 #if defined(CONFIG_SPIFLASH)
523 /*
524  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
525  * env, so we got 0x110000.
526  */
527 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
528 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
529 #elif defined(CONFIG_SDCARD)
530 /*
531  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
532  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
533  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
534  */
535 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
536 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
537 #elif defined(CONFIG_NAND)
538 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
539 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
540 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
541 /*
542  * Slave has no ucode locally, it can fetch this from remote. When implementing
543  * in two corenet boards, slave's ucode could be stored in master's memory
544  * space, the address can be mapped from slave TLB->slave LAW->
545  * slave SRIO or PCIE outbound window->master inbound window->
546  * master LAW->the ucode address in master's memory space.
547  */
548 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
549 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
550 #else
551 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
552 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
553 #endif
554 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
555 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
556
557 #ifdef CONFIG_SYS_DPAA_FMAN
558 #define CONFIG_FMAN_ENET
559 #define CONFIG_PHYLIB_10G
560 #define CONFIG_PHY_VITESSE
561 #define CONFIG_PHY_TERANETICS
562 #endif
563
564 #ifdef CONFIG_PCI
565 #define CONFIG_PCI_INDIRECT_BRIDGE
566 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
567 #define CONFIG_E1000
568
569 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
570 #define CONFIG_DOS_PARTITION
571 #endif  /* CONFIG_PCI */
572
573 /* SATA */
574 #define CONFIG_FSL_SATA_V2
575
576 #ifdef CONFIG_FSL_SATA_V2
577 #define CONFIG_FSL_SATA
578 #define CONFIG_LIBATA
579
580 #define CONFIG_SYS_SATA_MAX_DEVICE      2
581 #define CONFIG_SATA1
582 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
583 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
584 #define CONFIG_SATA2
585 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
586 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
587
588 #define CONFIG_LBA48
589 #define CONFIG_CMD_SATA
590 #define CONFIG_DOS_PARTITION
591 #define CONFIG_CMD_EXT2
592 #endif
593
594 #ifdef CONFIG_FMAN_ENET
595 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
596 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
597 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
598 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
599 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
600
601 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
602 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
603 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
604 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
605
606 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
607
608 #define CONFIG_SYS_TBIPA_VALUE  8
609 #define CONFIG_MII              /* MII PHY management */
610 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
611 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
612 #endif
613
614 /*
615  * Environment
616  */
617 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
618 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
619
620 /*
621  * Command line configuration.
622  */
623 #include <config_cmd_default.h>
624
625 #define CONFIG_CMD_DHCP
626 #define CONFIG_CMD_ELF
627 #define CONFIG_CMD_ERRATA
628 #define CONFIG_CMD_GREPENV
629 #define CONFIG_CMD_IRQ
630 #define CONFIG_CMD_I2C
631 #define CONFIG_CMD_MII
632 #define CONFIG_CMD_PING
633 #define CONFIG_CMD_SETEXPR
634
635 #ifdef CONFIG_PCI
636 #define CONFIG_CMD_PCI
637 #define CONFIG_CMD_NET
638 #endif
639
640 /*
641 * USB
642 */
643 #define CONFIG_HAS_FSL_DR_USB
644 #define CONFIG_HAS_FSL_MPH_USB
645
646 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
647 #define CONFIG_CMD_USB
648 #define CONFIG_USB_STORAGE
649 #define CONFIG_USB_EHCI
650 #define CONFIG_USB_EHCI_FSL
651 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
652 #endif
653
654 #define CONFIG_CMD_EXT2
655
656 #define CONFIG_MMC
657
658 #ifdef CONFIG_MMC
659 #define CONFIG_FSL_ESDHC
660 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
661 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
662 #define CONFIG_CMD_MMC
663 #define CONFIG_GENERIC_MMC
664 #define CONFIG_CMD_EXT2
665 #define CONFIG_CMD_FAT
666 #define CONFIG_DOS_PARTITION
667 #endif
668
669 /* Hash command with SHA acceleration supported in hardware */
670 #ifdef CONFIG_FSL_CAAM
671 #define CONFIG_CMD_HASH
672 #define CONFIG_SHA_HW_ACCEL
673 #endif
674
675 /*
676  * Miscellaneous configurable options
677  */
678 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
679 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
680 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
681 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
682 #ifdef CONFIG_CMD_KGDB
683 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
684 #else
685 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
686 #endif
687 /* Print Buffer Size */
688 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
689                                 sizeof(CONFIG_SYS_PROMPT)+16)
690 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
691 /* Boot Argument Buffer Size */
692 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
693
694 /*
695  * For booting Linux, the board info and command line data
696  * have to be in the first 64 MB of memory, since this is
697  * the maximum mapped by the Linux kernel during initialization.
698  */
699 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
700 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
701
702 #ifdef CONFIG_CMD_KGDB
703 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
704 #endif
705
706 /*
707  * Environment Configuration
708  */
709 #define CONFIG_ROOTPATH         "/opt/nfsroot"
710 #define CONFIG_BOOTFILE         "uImage"
711 #define CONFIG_UBOOTPATH        u-boot.bin
712
713 /* default location for tftp and bootm */
714 #define CONFIG_LOADADDR         1000000
715
716 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
717
718 #define CONFIG_BAUDRATE 115200
719
720 #define __USB_PHY_TYPE  utmi
721
722 #define CONFIG_EXTRA_ENV_SETTINGS                               \
723         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
724         "bank_intlv=cs0_cs1\0"                                  \
725         "netdev=eth0\0"                                         \
726         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
727         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
728         "tftpflash=tftpboot $loadaddr $uboot && "               \
729         "protect off $ubootaddr +$filesize && "                 \
730         "erase $ubootaddr +$filesize && "                       \
731         "cp.b $loadaddr $ubootaddr $filesize && "               \
732         "protect on $ubootaddr +$filesize && "                  \
733         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
734         "consoledev=ttyS0\0"                                    \
735         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
736         "usb_dr_mode=host\0"                                    \
737         "ramdiskaddr=2000000\0"                                 \
738         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
739         "fdtaddr=c00000\0"                                      \
740         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
741         "bdev=sda3\0"
742
743 #define CONFIG_HDBOOT                                   \
744         "setenv bootargs root=/dev/$bdev rw "           \
745         "console=$consoledev,$baudrate $othbootargs;"   \
746         "tftp $loadaddr $bootfile;"                     \
747         "tftp $fdtaddr $fdtfile;"                       \
748         "bootm $loadaddr - $fdtaddr"
749
750 #define CONFIG_NFSBOOTCOMMAND                   \
751         "setenv bootargs root=/dev/nfs rw "     \
752         "nfsroot=$serverip:$rootpath "          \
753         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
754         "console=$consoledev,$baudrate $othbootargs;"   \
755         "tftp $loadaddr $bootfile;"             \
756         "tftp $fdtaddr $fdtfile;"               \
757         "bootm $loadaddr - $fdtaddr"
758
759 #define CONFIG_RAMBOOTCOMMAND                           \
760         "setenv bootargs root=/dev/ram rw "             \
761         "console=$consoledev,$baudrate $othbootargs;"   \
762         "tftp $ramdiskaddr $ramdiskfile;"               \
763         "tftp $loadaddr $bootfile;"                     \
764         "tftp $fdtaddr $fdtfile;"                       \
765         "bootm $loadaddr $ramdiskaddr $fdtaddr"
766
767 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
768
769 #include <asm/fsl_secure_boot.h>
770
771 #ifdef CONFIG_SECURE_BOOT
772 #define CONFIG_CMD_BLOB
773 #endif
774
775 #endif  /* __CONFIG_H */