1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
20 /* Set 1M boot space */
21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
23 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 /* High Level Configuration Options */
28 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
31 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
35 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
36 #define CONFIG_PCIE1 /* PCIE controller 1 */
37 #define CONFIG_PCIE2 /* PCIE controller 2 */
38 #define CONFIG_PCIE3 /* PCIE controller 3 */
39 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
41 #define CONFIG_SYS_SRIO
42 #define CONFIG_SRIO1 /* SRIO port 1 */
43 #define CONFIG_SRIO2 /* SRIO port 2 */
44 #define CONFIG_SRIO_PCIE_BOOT_MASTER
45 #define CONFIG_SYS_DPAA_RMAN /* RMan */
47 #if defined(CONFIG_SPIFLASH)
48 #elif defined(CONFIG_SDCARD)
49 #define CONFIG_FSL_FIXED_MMC_LOCATION
53 unsigned long get_board_sys_clk(unsigned long dummy);
54 #include <linux/stringify.h>
56 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
59 * These can be toggled for performance analysis, otherwise use default.
61 #define CONFIG_SYS_CACHE_STASHING
62 #define CONFIG_BACKSIDE_L2_CACHE
63 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
64 #define CONFIG_BTB /* toggle branch predition */
66 #define CONFIG_ENABLE_36BIT_PHYS
68 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
71 * Config the L3 Cache as L3 SRAM
73 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
74 #ifdef CONFIG_PHYS_64BIT
75 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
76 CONFIG_RAMBOOT_TEXT_BASE)
78 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
80 #define CONFIG_SYS_L3_SIZE (1024 << 10)
81 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
83 #ifdef CONFIG_PHYS_64BIT
84 #define CONFIG_SYS_DCSRBAR 0xf0000000
85 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
89 #define CONFIG_SYS_I2C_EEPROM_NXID
90 #define CONFIG_SYS_EEPROM_BUS_NUM 0
95 #define CONFIG_VERY_BIG_RAM
96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
100 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
102 #define CONFIG_SYS_SPD_BUS_NUM 0
103 #define SPD_EEPROM_ADDRESS 0x52
104 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
107 * Local Bus Definitions
110 /* Set the local bus clock 1/8 of platform clock */
111 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
114 * This board doesn't have a promjet connector.
115 * However, it uses commone corenet board LAW and TLB.
116 * It is necessary to use the same start address with proper offset.
118 #define CONFIG_SYS_FLASH_BASE 0xe0000000
119 #ifdef CONFIG_PHYS_64BIT
120 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
122 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
125 #define CONFIG_SYS_FLASH_BR_PRELIM \
126 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
128 #define CONFIG_SYS_FLASH_OR_PRELIM \
129 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
130 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
132 #define CONFIG_FSL_CPLD
133 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
134 #ifdef CONFIG_PHYS_64BIT
135 #define CPLD_BASE_PHYS 0xfffdf0000ull
137 #define CPLD_BASE_PHYS CPLD_BASE
140 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
141 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
143 #define PIXIS_LBMAP_SWITCH 7
144 #define PIXIS_LBMAP_MASK 0xf0
145 #define PIXIS_LBMAP_SHIFT 4
146 #define PIXIS_LBMAP_ALTBANK 0x40
148 #define CONFIG_SYS_FLASH_QUIET_TEST
149 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
151 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
152 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
153 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
154 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
158 #if defined(CONFIG_RAMBOOT_PBL)
159 #define CONFIG_SYS_RAMBOOT
163 #ifdef CONFIG_NAND_FSL_ELBC
164 #define CONFIG_SYS_NAND_BASE 0xffa00000
165 #ifdef CONFIG_PHYS_64BIT
166 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
168 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
171 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
172 #define CONFIG_SYS_MAX_NAND_DEVICE 1
174 /* NAND flash config */
175 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
176 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
177 | BR_PS_8 /* Port Size = 8 bit */ \
178 | BR_MS_FCM /* MSEL = FCM */ \
180 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
181 | OR_FCM_PGS /* Large Page*/ \
189 #ifdef CONFIG_MTD_RAW_NAND
190 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
191 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
192 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
193 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
195 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
196 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
197 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
198 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
201 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
202 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
203 #endif /* CONFIG_NAND_FSL_ELBC */
205 #define CONFIG_SYS_FLASH_EMPTY_INFO
206 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
207 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
209 #define CONFIG_HWCONFIG
211 /* define to use L1 as initial stack */
212 #define CONFIG_L1_INIT_RAM
213 #define CONFIG_SYS_INIT_RAM_LOCK
214 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
215 #ifdef CONFIG_PHYS_64BIT
216 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
217 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
218 /* The assembler doesn't like typecast */
219 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
220 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
221 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
223 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
224 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
227 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
229 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
230 GENERATED_GBL_DATA_SIZE)
231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
235 /* Serial Port - controlled on board with jumper J8
239 #define CONFIG_SYS_NS16550_SERIAL
240 #define CONFIG_SYS_NS16550_REG_SIZE 1
241 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
243 #define CONFIG_SYS_BAUDRATE_TABLE \
244 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
246 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
247 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
248 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
249 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
257 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
258 #ifdef CONFIG_PHYS_64BIT
259 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
261 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
263 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
265 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
266 #ifdef CONFIG_PHYS_64BIT
267 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
269 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
271 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
274 * for slave u-boot IMAGE instored in master memory space,
275 * PHYS must be aligned based on the SIZE
277 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
278 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
279 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
280 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
282 * for slave UCODE and ENV instored in master memory space,
283 * PHYS must be aligned based on the SIZE
285 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
286 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
287 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
289 /* slave core release by master*/
290 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
291 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
294 * SRIO_PCIE_BOOT - SLAVE
296 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
297 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
298 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
299 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
303 * eSPI - Enhanced SPI
308 * Memory space is mapped 1-1, but I/O space must start from 0.
311 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
312 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
313 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
314 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
315 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
317 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
318 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
319 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
320 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
321 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
323 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
324 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
325 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
326 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
327 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
330 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
331 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
332 #ifdef CONFIG_PHYS_64BIT
333 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
335 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
337 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
338 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
339 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
340 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
341 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
342 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
343 CONFIG_SYS_BMAN_CENA_SIZE)
344 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
345 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
346 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
347 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
348 #ifdef CONFIG_PHYS_64BIT
349 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
351 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
353 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
354 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
355 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
356 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
357 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
358 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
359 CONFIG_SYS_QMAN_CENA_SIZE)
360 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
361 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
363 #define CONFIG_SYS_DPAA_FMAN
364 #define CONFIG_SYS_DPAA_PME
365 /* Default address of microcode for the Linux Fman driver */
366 #if defined(CONFIG_SPIFLASH)
368 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
369 * env, so we got 0x110000.
371 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
372 #elif defined(CONFIG_SDCARD)
374 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
375 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
376 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
378 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
379 #elif defined(CONFIG_MTD_RAW_NAND)
380 #define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
381 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
383 * Slave has no ucode locally, it can fetch this from remote. When implementing
384 * in two corenet boards, slave's ucode could be stored in master's memory
385 * space, the address can be mapped from slave TLB->slave LAW->
386 * slave SRIO or PCIE outbound window->master inbound window->
387 * master LAW->the ucode address in master's memory space.
389 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
391 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
393 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
394 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
397 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
398 #endif /* CONFIG_PCI */
401 #define CONFIG_FSL_SATA_V2
403 #ifdef CONFIG_FSL_SATA_V2
404 #define CONFIG_SYS_SATA_MAX_DEVICE 2
406 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
407 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
409 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
410 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
415 #ifdef CONFIG_FMAN_ENET
416 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
417 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
418 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
419 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
420 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
422 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
423 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
424 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
425 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
427 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
429 #define CONFIG_SYS_TBIPA_VALUE 8
430 #define CONFIG_ETHPRIME "FM1@DTSEC1"
436 #define CONFIG_LOADS_ECHO /* echo on for serial download */
437 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
442 #define CONFIG_HAS_FSL_DR_USB
443 #define CONFIG_HAS_FSL_MPH_USB
445 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
446 #define CONFIG_USB_EHCI_FSL
447 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
451 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
452 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
456 * Miscellaneous configurable options
460 * For booting Linux, the board info and command line data
461 * have to be in the first 64 MB of memory, since this is
462 * the maximum mapped by the Linux kernel during initialization.
464 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
465 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
468 * Environment Configuration
470 #define CONFIG_ROOTPATH "/opt/nfsroot"
471 #define CONFIG_BOOTFILE "uImage"
472 #define CONFIG_UBOOTPATH u-boot.bin
474 #define __USB_PHY_TYPE utmi
476 #define CONFIG_EXTRA_ENV_SETTINGS \
477 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
478 "bank_intlv=cs0_cs1\0" \
480 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
481 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
482 "tftpflash=tftpboot $loadaddr $uboot && " \
483 "protect off $ubootaddr +$filesize && " \
484 "erase $ubootaddr +$filesize && " \
485 "cp.b $loadaddr $ubootaddr $filesize && " \
486 "protect on $ubootaddr +$filesize && " \
487 "cmp.b $loadaddr $ubootaddr $filesize\0" \
488 "consoledev=ttyS0\0" \
489 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
490 "usb_dr_mode=host\0" \
491 "ramdiskaddr=2000000\0" \
492 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
493 "fdtaddr=1e00000\0" \
494 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
498 "setenv bootargs root=/dev/$bdev rw " \
499 "console=$consoledev,$baudrate $othbootargs;" \
500 "tftp $loadaddr $bootfile;" \
501 "tftp $fdtaddr $fdtfile;" \
502 "bootm $loadaddr - $fdtaddr"
504 #define NFSBOOTCOMMAND \
505 "setenv bootargs root=/dev/nfs rw " \
506 "nfsroot=$serverip:$rootpath " \
507 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
508 "console=$consoledev,$baudrate $othbootargs;" \
509 "tftp $loadaddr $bootfile;" \
510 "tftp $fdtaddr $fdtfile;" \
511 "bootm $loadaddr - $fdtaddr"
513 #define RAMBOOTCOMMAND \
514 "setenv bootargs root=/dev/ram rw " \
515 "console=$consoledev,$baudrate $othbootargs;" \
516 "tftp $ramdiskaddr $ramdiskfile;" \
517 "tftp $loadaddr $bootfile;" \
518 "tftp $fdtaddr $fdtfile;" \
519 "bootm $loadaddr $ramdiskaddr $fdtaddr"
521 #define CONFIG_BOOTCOMMAND HDBOOT
523 #include <asm/fsl_secure_boot.h>
525 #endif /* __CONFIG_H */