include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  29
  30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  32 #endif
  33
  34 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  35 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  36
  37 #define CONFIG_SYS_SRIO
  38 #define CONFIG_SRIO1                    /* SRIO port 1 */
  39 #define CONFIG_SRIO2                    /* SRIO port 2 */
  40 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  41 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  42
  43 #ifndef __ASSEMBLY__
  44 #include <linux/stringify.h>
  45 #endif
  46
  47 /*
  48  * These can be toggled for performance analysis, otherwise use default.
  49  */
  50 #define CONFIG_SYS_CACHE_STASHING
  51 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  52
  53 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  54
  55 /*
  56  *  Config the L3 Cache as L3 SRAM
  57  */
  58 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  59 #ifdef CONFIG_PHYS_64BIT
  60 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  61                 CONFIG_RAMBOOT_TEXT_BASE)
  62 #else
  63 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  64 #endif
  65 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  66 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  67
  68 #ifdef CONFIG_PHYS_64BIT
  69 #define CONFIG_SYS_DCSRBAR              0xf0000000
  70 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  71 #endif
  72
  73 /* EEPROM */
  74 #define CONFIG_SYS_I2C_EEPROM_NXID
  75 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  76
  77 /*
  78  * DDR Setup
  79  */
  80 #define CONFIG_VERY_BIG_RAM
  81 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  82 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  83
  84 #define SPD_EEPROM_ADDRESS      0x52
  85 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  86
  87 /*
  88  * Local Bus Definitions
  89  */
  90
  91 /* Set the local bus clock 1/8 of platform clock */
  92 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  93
  94 /*
  95  * This board doesn't have a promjet connector.
  96  * However, it uses commone corenet board LAW and TLB.
  97  * It is necessary to use the same start address with proper offset.
  98  */
  99 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 100 #ifdef CONFIG_PHYS_64BIT
 101 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 102 #else
 103 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 104 #endif
 105
 106 #define CONFIG_SYS_FLASH_BR_PRELIM \
 107                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 108                 BR_PS_16 | BR_V)
 109 #define CONFIG_SYS_FLASH_OR_PRELIM \
 110                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 111                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 112
 113 #define CONFIG_FSL_CPLD
 114 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 115 #ifdef CONFIG_PHYS_64BIT
 116 #define CPLD_BASE_PHYS          0xfffdf0000ull
 117 #else
 118 #define CPLD_BASE_PHYS          CPLD_BASE
 119 #endif
 120
 121 #define PIXIS_LBMAP_SWITCH      7
 122 #define PIXIS_LBMAP_MASK        0xf0
 123 #define PIXIS_LBMAP_SHIFT       4
 124 #define PIXIS_LBMAP_ALTBANK     0x40
 125
 126 #define CONFIG_SYS_FLASH_QUIET_TEST
 127 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 128
 129 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 130 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 131 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 132
 133 #if defined(CONFIG_RAMBOOT_PBL)
 134 #define CONFIG_SYS_RAMBOOT
 135 #endif
 136
 137 /* Nand Flash */
 138 #ifdef CONFIG_NAND_FSL_ELBC
 139 #define CONFIG_SYS_NAND_BASE            0xffa00000
 140 #ifdef CONFIG_PHYS_64BIT
 141 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 142 #else
 143 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 144 #endif
 145
 146 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 147 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 148
 149 /* NAND flash config */
 150 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 151                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 152                                | BR_PS_8               /* Port Size = 8 bit */ \
 153                                | BR_MS_FCM             /* MSEL = FCM */ \
 154                                | BR_V)                 /* valid */
 155 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 156                                | OR_FCM_PGS            /* Large Page*/ \
 157                                | OR_FCM_CSCT \
 158                                | OR_FCM_CST \
 159                                | OR_FCM_CHT \
 160                                | OR_FCM_SCY_1 \
 161                                | OR_FCM_TRLX \
 162                                | OR_FCM_EHTR)
 163 #endif /* CONFIG_NAND_FSL_ELBC */
 164
 165 #define CONFIG_SYS_FLASH_EMPTY_INFO
 166 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 167
 168 #define CONFIG_HWCONFIG
 169
 170 /* define to use L1 as initial stack */
 171 #define CONFIG_L1_INIT_RAM
 172 #define CONFIG_SYS_INIT_RAM_LOCK
 173 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 174 #ifdef CONFIG_PHYS_64BIT
 175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 177 /* The assembler doesn't like typecast */
 178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 179         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 180           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 181 #else
 182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 185 #endif
 186 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 187
 188 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 189
 190 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 191
 192 /* Serial Port - controlled on board with jumper J8
 193  * open - index 2
 194  * shorted - index 1
 195  */
 196 #define CONFIG_SYS_NS16550_SERIAL
 197 #define CONFIG_SYS_NS16550_REG_SIZE     1
 198 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 199
 200 #define CONFIG_SYS_BAUDRATE_TABLE       \
 201         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 202
 203 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 204 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 205 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 206 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 207
 208 /* I2C */
 209
 210
 211 /*
 212  * RapidIO
 213  */
 214 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 215 #ifdef CONFIG_PHYS_64BIT
 216 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 217 #else
 218 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 219 #endif
 220 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 221
 222 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 223 #ifdef CONFIG_PHYS_64BIT
 224 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 225 #else
 226 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 227 #endif
 228 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 229
 230 /*
 231  * for slave u-boot IMAGE instored in master memory space,
 232  * PHYS must be aligned based on the SIZE
 233  */
 234 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 235 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 236 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 237 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 238 /*
 239  * for slave UCODE and ENV instored in master memory space,
 240  * PHYS must be aligned based on the SIZE
 241  */
 242 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 243 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 244 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 245
 246 /* slave core release by master*/
 247 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 248 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 249
 250 /*
 251  * SRIO_PCIE_BOOT - SLAVE
 252  */
 253 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 254 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 255 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 256                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 257 #endif
 258
 259 /*
 260  * eSPI - Enhanced SPI
 261  */
 262
 263 /*
 264  * General PCI
 265  * Memory space is mapped 1-1, but I/O space must start from 0.
 266  */
 267
 268 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 269 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 270 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 271 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 272 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 273
 274 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 275 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 276 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 277 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 278 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 279
 280 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 281 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 282 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 283 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 284 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 285
 286 /* Qman/Bman */
 287 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 288 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 289 #ifdef CONFIG_PHYS_64BIT
 290 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 291 #else
 292 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 293 #endif
 294 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 295 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 296 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 297 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 298 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 299 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 300                                         CONFIG_SYS_BMAN_CENA_SIZE)
 301 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 302 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 303 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 304 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 305 #ifdef CONFIG_PHYS_64BIT
 306 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 307 #else
 308 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 309 #endif
 310 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 311 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 312 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 313 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 314 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 315 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 316                                         CONFIG_SYS_QMAN_CENA_SIZE)
 317 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 318 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 319
 320 #define CONFIG_SYS_DPAA_FMAN
 321 #define CONFIG_SYS_DPAA_PME
 322 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 323
 324 #ifdef CONFIG_FMAN_ENET
 325 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 326 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 327 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 328 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 329 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 330
 331 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 332 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 333 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 334 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 335
 336 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 337
 338 #define CONFIG_SYS_TBIPA_VALUE  8
 339 #endif
 340
 341 /*
 342  * Environment
 343  */
 344 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 345 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 346
 347 #ifdef CONFIG_MMC
 348 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 349 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 350 #endif
 351
 352 /*
 353  * Miscellaneous configurable options
 354  */
 355
 356 /*
 357  * For booting Linux, the board info and command line data
 358  * have to be in the first 64 MB of memory, since this is
 359  * the maximum mapped by the Linux kernel during initialization.
 360  */
 361 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 362 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 363
 364 /*
 365  * Environment Configuration
 366  */
 367 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 368 #define CONFIG_UBOOTPATH        u-boot.bin
 369
 370 #define __USB_PHY_TYPE  utmi
 371
 372 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 373         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 374         "bank_intlv=cs0_cs1\0"                                  \
 375         "netdev=eth0\0"                                         \
 376         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 377         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 378         "tftpflash=tftpboot $loadaddr $uboot && "               \
 379         "protect off $ubootaddr +$filesize && "                 \
 380         "erase $ubootaddr +$filesize && "                       \
 381         "cp.b $loadaddr $ubootaddr $filesize && "               \
 382         "protect on $ubootaddr +$filesize && "                  \
 383         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 384         "consoledev=ttyS0\0"                                    \
 385         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 386         "usb_dr_mode=host\0"                                    \
 387         "ramdiskaddr=2000000\0"                                 \
 388         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 389         "fdtaddr=1e00000\0"                                     \
 390         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 391         "bdev=sda3\0"
 392
 393 #include <asm/fsl_secure_boot.h>
 394
 395 #endif  /* __CONFIG_H */