1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
22 /* Set 1M boot space */
23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29 /* High Level Configuration Options */
30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
36 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
37 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
38 #define CONFIG_PCIE1 /* PCIE controller 1 */
39 #define CONFIG_PCIE2 /* PCIE controller 2 */
40 #define CONFIG_PCIE3 /* PCIE controller 3 */
41 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
43 #define CONFIG_SYS_SRIO
44 #define CONFIG_SRIO1 /* SRIO port 1 */
45 #define CONFIG_SRIO2 /* SRIO port 2 */
46 #define CONFIG_SRIO_PCIE_BOOT_MASTER
47 #define CONFIG_SYS_DPAA_RMAN /* RMan */
49 #define CONFIG_ENV_OVERWRITE
51 #if defined(CONFIG_SPIFLASH)
52 #elif defined(CONFIG_SDCARD)
53 #define CONFIG_FSL_FIXED_MMC_LOCATION
54 #define CONFIG_SYS_MMC_ENV_DEV 0
58 unsigned long get_board_sys_clk(unsigned long dummy);
59 #include <linux/stringify.h>
61 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
64 * These can be toggled for performance analysis, otherwise use default.
66 #define CONFIG_SYS_CACHE_STASHING
67 #define CONFIG_BACKSIDE_L2_CACHE
68 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
69 #define CONFIG_BTB /* toggle branch predition */
71 #define CONFIG_ENABLE_36BIT_PHYS
73 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
76 * Config the L3 Cache as L3 SRAM
78 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
79 #ifdef CONFIG_PHYS_64BIT
80 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
81 CONFIG_RAMBOOT_TEXT_BASE)
83 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
85 #define CONFIG_SYS_L3_SIZE (1024 << 10)
86 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
88 #ifdef CONFIG_PHYS_64BIT
89 #define CONFIG_SYS_DCSRBAR 0xf0000000
90 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
94 #define CONFIG_ID_EEPROM
95 #define CONFIG_SYS_I2C_EEPROM_NXID
96 #define CONFIG_SYS_EEPROM_BUS_NUM 0
97 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
98 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
103 #define CONFIG_VERY_BIG_RAM
104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
108 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
110 #define CONFIG_DDR_SPD
112 #define CONFIG_SYS_SPD_BUS_NUM 0
113 #define SPD_EEPROM_ADDRESS 0x52
114 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
117 * Local Bus Definitions
120 /* Set the local bus clock 1/8 of platform clock */
121 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
124 * This board doesn't have a promjet connector.
125 * However, it uses commone corenet board LAW and TLB.
126 * It is necessary to use the same start address with proper offset.
128 #define CONFIG_SYS_FLASH_BASE 0xe0000000
129 #ifdef CONFIG_PHYS_64BIT
130 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
132 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
135 #define CONFIG_SYS_FLASH_BR_PRELIM \
136 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
138 #define CONFIG_SYS_FLASH_OR_PRELIM \
139 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
140 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
142 #define CONFIG_FSL_CPLD
143 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
144 #ifdef CONFIG_PHYS_64BIT
145 #define CPLD_BASE_PHYS 0xfffdf0000ull
147 #define CPLD_BASE_PHYS CPLD_BASE
150 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
151 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
153 #define PIXIS_LBMAP_SWITCH 7
154 #define PIXIS_LBMAP_MASK 0xf0
155 #define PIXIS_LBMAP_SHIFT 4
156 #define PIXIS_LBMAP_ALTBANK 0x40
158 #define CONFIG_SYS_FLASH_QUIET_TEST
159 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
162 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
163 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
164 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
168 #if defined(CONFIG_RAMBOOT_PBL)
169 #define CONFIG_SYS_RAMBOOT
172 #define CONFIG_NAND_FSL_ELBC
174 #ifdef CONFIG_NAND_FSL_ELBC
175 #define CONFIG_SYS_NAND_BASE 0xffa00000
176 #ifdef CONFIG_PHYS_64BIT
177 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
179 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
182 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
183 #define CONFIG_SYS_MAX_NAND_DEVICE 1
184 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
186 /* NAND flash config */
187 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
188 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
189 | BR_PS_8 /* Port Size = 8 bit */ \
190 | BR_MS_FCM /* MSEL = FCM */ \
192 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
193 | OR_FCM_PGS /* Large Page*/ \
201 #ifdef CONFIG_MTD_RAW_NAND
202 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
203 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
204 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
205 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
207 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
208 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
209 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
210 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
213 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
214 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
215 #endif /* CONFIG_NAND_FSL_ELBC */
217 #define CONFIG_SYS_FLASH_EMPTY_INFO
218 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
219 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
221 #define CONFIG_HWCONFIG
223 /* define to use L1 as initial stack */
224 #define CONFIG_L1_INIT_RAM
225 #define CONFIG_SYS_INIT_RAM_LOCK
226 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
227 #ifdef CONFIG_PHYS_64BIT
228 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
229 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
230 /* The assembler doesn't like typecast */
231 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
232 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
233 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
235 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
236 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
237 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
239 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
241 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
242 GENERATED_GBL_DATA_SIZE)
243 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
245 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
246 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
248 /* Serial Port - controlled on board with jumper J8
252 #define CONFIG_SYS_NS16550_SERIAL
253 #define CONFIG_SYS_NS16550_REG_SIZE 1
254 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
256 #define CONFIG_SYS_BAUDRATE_TABLE \
257 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
259 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
260 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
261 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
262 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
265 #ifndef CONFIG_DM_I2C
266 #define CONFIG_SYS_I2C
267 #define CONFIG_SYS_FSL_I2C_SPEED 400000
268 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
269 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
270 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
271 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
272 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
274 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
275 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
277 #define CONFIG_SYS_I2C_FSL
283 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
284 #ifdef CONFIG_PHYS_64BIT
285 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
287 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
289 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
291 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
292 #ifdef CONFIG_PHYS_64BIT
293 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
295 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
297 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
300 * for slave u-boot IMAGE instored in master memory space,
301 * PHYS must be aligned based on the SIZE
303 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
304 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
305 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
306 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
308 * for slave UCODE and ENV instored in master memory space,
309 * PHYS must be aligned based on the SIZE
311 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
312 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
313 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
315 /* slave core release by master*/
316 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
317 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
320 * SRIO_PCIE_BOOT - SLAVE
322 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
323 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
324 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
325 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
329 * eSPI - Enhanced SPI
334 * Memory space is mapped 1-1, but I/O space must start from 0.
337 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
338 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
339 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
340 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
341 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
343 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
344 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
345 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
346 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
347 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
349 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
350 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
351 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
352 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
353 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
356 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
357 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
358 #ifdef CONFIG_PHYS_64BIT
359 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
361 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
363 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
364 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
365 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
366 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
367 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
368 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
369 CONFIG_SYS_BMAN_CENA_SIZE)
370 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
371 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
372 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
373 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
374 #ifdef CONFIG_PHYS_64BIT
375 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
377 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
379 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
380 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
381 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
382 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
383 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
384 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
385 CONFIG_SYS_QMAN_CENA_SIZE)
386 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
387 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
389 #define CONFIG_SYS_DPAA_FMAN
390 #define CONFIG_SYS_DPAA_PME
391 /* Default address of microcode for the Linux Fman driver */
392 #if defined(CONFIG_SPIFLASH)
394 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
395 * env, so we got 0x110000.
397 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
398 #elif defined(CONFIG_SDCARD)
400 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
401 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
402 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
404 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
405 #elif defined(CONFIG_MTD_RAW_NAND)
406 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
407 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
409 * Slave has no ucode locally, it can fetch this from remote. When implementing
410 * in two corenet boards, slave's ucode could be stored in master's memory
411 * space, the address can be mapped from slave TLB->slave LAW->
412 * slave SRIO or PCIE outbound window->master inbound window->
413 * master LAW->the ucode address in master's memory space.
415 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
417 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
419 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
420 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
423 #if !defined(CONFIG_DM_PCI)
424 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
425 #define CONFIG_PCI_INDIRECT_BRIDGE
426 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
427 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
428 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
429 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
430 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
431 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
432 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
433 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
434 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
435 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
436 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
437 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
440 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
441 #endif /* CONFIG_PCI */
444 #define CONFIG_FSL_SATA_V2
446 #ifdef CONFIG_FSL_SATA_V2
447 #define CONFIG_SYS_SATA_MAX_DEVICE 2
449 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
450 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
452 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
453 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
458 #ifdef CONFIG_FMAN_ENET
459 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
460 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
461 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
462 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
463 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
465 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
466 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
467 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
468 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
470 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
472 #define CONFIG_SYS_TBIPA_VALUE 8
473 #define CONFIG_ETHPRIME "FM1@DTSEC1"
479 #define CONFIG_LOADS_ECHO /* echo on for serial download */
480 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
485 #define CONFIG_HAS_FSL_DR_USB
486 #define CONFIG_HAS_FSL_MPH_USB
488 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
489 #define CONFIG_USB_EHCI_FSL
490 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
494 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
495 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
499 * Miscellaneous configurable options
501 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
504 * For booting Linux, the board info and command line data
505 * have to be in the first 64 MB of memory, since this is
506 * the maximum mapped by the Linux kernel during initialization.
508 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
509 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
511 #ifdef CONFIG_CMD_KGDB
512 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
516 * Environment Configuration
518 #define CONFIG_ROOTPATH "/opt/nfsroot"
519 #define CONFIG_BOOTFILE "uImage"
520 #define CONFIG_UBOOTPATH u-boot.bin
522 /* default location for tftp and bootm */
523 #define CONFIG_LOADADDR 1000000
525 #define __USB_PHY_TYPE utmi
527 #define CONFIG_EXTRA_ENV_SETTINGS \
528 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
529 "bank_intlv=cs0_cs1\0" \
531 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
532 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
533 "tftpflash=tftpboot $loadaddr $uboot && " \
534 "protect off $ubootaddr +$filesize && " \
535 "erase $ubootaddr +$filesize && " \
536 "cp.b $loadaddr $ubootaddr $filesize && " \
537 "protect on $ubootaddr +$filesize && " \
538 "cmp.b $loadaddr $ubootaddr $filesize\0" \
539 "consoledev=ttyS0\0" \
540 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
541 "usb_dr_mode=host\0" \
542 "ramdiskaddr=2000000\0" \
543 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
544 "fdtaddr=1e00000\0" \
545 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
548 #define CONFIG_HDBOOT \
549 "setenv bootargs root=/dev/$bdev rw " \
550 "console=$consoledev,$baudrate $othbootargs;" \
551 "tftp $loadaddr $bootfile;" \
552 "tftp $fdtaddr $fdtfile;" \
553 "bootm $loadaddr - $fdtaddr"
555 #define CONFIG_NFSBOOTCOMMAND \
556 "setenv bootargs root=/dev/nfs rw " \
557 "nfsroot=$serverip:$rootpath " \
558 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
559 "console=$consoledev,$baudrate $othbootargs;" \
560 "tftp $loadaddr $bootfile;" \
561 "tftp $fdtaddr $fdtfile;" \
562 "bootm $loadaddr - $fdtaddr"
564 #define CONFIG_RAMBOOTCOMMAND \
565 "setenv bootargs root=/dev/ram rw " \
566 "console=$consoledev,$baudrate $othbootargs;" \
567 "tftp $ramdiskaddr $ramdiskfile;" \
568 "tftp $loadaddr $bootfile;" \
569 "tftp $fdtaddr $fdtfile;" \
570 "bootm $loadaddr $ramdiskaddr $fdtaddr"
572 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
574 #include <asm/fsl_secure_boot.h>
576 #endif /* __CONFIG_H */