include/configs/P2041RDB.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  19 #endif
  20
  21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  22 /* Set 1M boot space */
  23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  27 #define CONFIG_SYS_NO_FLASH
  28 #endif
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE
  32 #define CONFIG_E500                     /* BOOKE e500 family */
  33 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  34 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  35 #define CONFIG_MP                       /* support multiple processors */
  36
  37 #ifndef CONFIG_SYS_TEXT_BASE
  38 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  39 #endif
  40
  41 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  42 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  43 #endif
  44
  45 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  46 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  47 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  48 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  49 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  50 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  51 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  52 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  53 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  54
  55 #define CONFIG_SYS_SRIO
  56 #define CONFIG_SRIO1                    /* SRIO port 1 */
  57 #define CONFIG_SRIO2                    /* SRIO port 2 */
  58 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  59 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  60
  61 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  62
  63 #define CONFIG_ENV_OVERWRITE
  64
  65 #ifdef CONFIG_SYS_NO_FLASH
  66 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  67 #define CONFIG_ENV_IS_NOWHERE
  68 #endif
  69 #else
  70 #define CONFIG_FLASH_CFI_DRIVER
  71 #define CONFIG_SYS_FLASH_CFI
  72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  73 #endif
  74
  75 #if defined(CONFIG_SPIFLASH)
  76         #define CONFIG_SYS_EXTRA_ENV_RELOC
  77         #define CONFIG_ENV_IS_IN_SPI_FLASH
  78         #define CONFIG_ENV_SPI_BUS              0
  79         #define CONFIG_ENV_SPI_CS               0
  80         #define CONFIG_ENV_SPI_MAX_HZ           10000000
  81         #define CONFIG_ENV_SPI_MODE             0
  82         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  83         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  84         #define CONFIG_ENV_SECT_SIZE            0x10000
  85 #elif defined(CONFIG_SDCARD)
  86         #define CONFIG_SYS_EXTRA_ENV_RELOC
  87         #define CONFIG_ENV_IS_IN_MMC
  88         #define CONFIG_FSL_FIXED_MMC_LOCATION
  89         #define CONFIG_SYS_MMC_ENV_DEV          0
  90         #define CONFIG_ENV_SIZE                 0x2000
  91         #define CONFIG_ENV_OFFSET               (512 * 1658)
  92 #elif defined(CONFIG_NAND)
  93 #define CONFIG_SYS_EXTRA_ENV_RELOC
  94 #define CONFIG_ENV_IS_IN_NAND
  95 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  96 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  97 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  98 #define CONFIG_ENV_IS_IN_REMOTE
  99 #define CONFIG_ENV_ADDR         0xffe20000
 100 #define CONFIG_ENV_SIZE         0x2000
 101 #elif defined(CONFIG_ENV_IS_NOWHERE)
 102 #define CONFIG_ENV_SIZE         0x2000
 103 #else
 104         #define CONFIG_ENV_IS_IN_FLASH
 105         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 106                         - CONFIG_ENV_SECT_SIZE)
 107         #define CONFIG_ENV_SIZE         0x2000
 108         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 109 #endif
 110
 111 #ifndef __ASSEMBLY__
 112 unsigned long get_board_sys_clk(unsigned long dummy);
 113 #endif
 114 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
 115
 116 /*
 117  * These can be toggled for performance analysis, otherwise use default.
 118  */
 119 #define CONFIG_SYS_CACHE_STASHING
 120 #define CONFIG_BACKSIDE_L2_CACHE
 121 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 122 #define CONFIG_BTB                      /* toggle branch predition */
 123
 124 #define CONFIG_ENABLE_36BIT_PHYS
 125
 126 #ifdef CONFIG_PHYS_64BIT
 127 #define CONFIG_ADDR_MAP
 128 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 129 #endif
 130
 131 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 132 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 133 #define CONFIG_SYS_MEMTEST_END          0x00400000
 134 #define CONFIG_SYS_ALT_MEMTEST
 135 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 136
 137 /*
 138  *  Config the L3 Cache as L3 SRAM
 139  */
 140 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 141 #ifdef CONFIG_PHYS_64BIT
 142 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 143                 CONFIG_RAMBOOT_TEXT_BASE)
 144 #else
 145 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 146 #endif
 147 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 148 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 149
 150 #ifdef CONFIG_PHYS_64BIT
 151 #define CONFIG_SYS_DCSRBAR              0xf0000000
 152 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 153 #endif
 154
 155 /* EEPROM */
 156 #define CONFIG_ID_EEPROM
 157 #define CONFIG_SYS_I2C_EEPROM_NXID
 158 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 159 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 161
 162 /*
 163  * DDR Setup
 164  */
 165 #define CONFIG_VERY_BIG_RAM
 166 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 167 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 168
 169 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 170 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 171
 172 #define CONFIG_DDR_SPD
 173 #define CONFIG_SYS_FSL_DDR3
 174
 175 #define CONFIG_SYS_SPD_BUS_NUM  0
 176 #define SPD_EEPROM_ADDRESS      0x52
 177 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 178
 179 /*
 180  * Local Bus Definitions
 181  */
 182
 183 /* Set the local bus clock 1/8 of platform clock */
 184 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 185
 186 /*
 187  * This board doesn't have a promjet connector.
 188  * However, it uses commone corenet board LAW and TLB.
 189  * It is necessary to use the same start address with proper offset.
 190  */
 191 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 192 #ifdef CONFIG_PHYS_64BIT
 193 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 194 #else
 195 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 196 #endif
 197
 198 #define CONFIG_SYS_FLASH_BR_PRELIM \
 199                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 200                 BR_PS_16 | BR_V)
 201 #define CONFIG_SYS_FLASH_OR_PRELIM \
 202                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 203                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 204
 205 #define CONFIG_FSL_CPLD
 206 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 207 #ifdef CONFIG_PHYS_64BIT
 208 #define CPLD_BASE_PHYS          0xfffdf0000ull
 209 #else
 210 #define CPLD_BASE_PHYS          CPLD_BASE
 211 #endif
 212
 213 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 214 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 215
 216 #define PIXIS_LBMAP_SWITCH      7
 217 #define PIXIS_LBMAP_MASK        0xf0
 218 #define PIXIS_LBMAP_SHIFT       4
 219 #define PIXIS_LBMAP_ALTBANK     0x40
 220
 221 #define CONFIG_SYS_FLASH_QUIET_TEST
 222 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 223
 224 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 225 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 226 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 227 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 228
 229 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 230
 231 #if defined(CONFIG_RAMBOOT_PBL)
 232 #define CONFIG_SYS_RAMBOOT
 233 #endif
 234
 235 #define CONFIG_NAND_FSL_ELBC
 236 /* Nand Flash */
 237 #ifdef CONFIG_NAND_FSL_ELBC
 238 #define CONFIG_SYS_NAND_BASE            0xffa00000
 239 #ifdef CONFIG_PHYS_64BIT
 240 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 241 #else
 242 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 243 #endif
 244
 245 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 246 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 247 #define CONFIG_CMD_NAND
 248 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 249
 250 /* NAND flash config */
 251 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 252                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 253                                | BR_PS_8               /* Port Size = 8 bit */ \
 254                                | BR_MS_FCM             /* MSEL = FCM */ \
 255                                | BR_V)                 /* valid */
 256 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 257                                | OR_FCM_PGS            /* Large Page*/ \
 258                                | OR_FCM_CSCT \
 259                                | OR_FCM_CST \
 260                                | OR_FCM_CHT \
 261                                | OR_FCM_SCY_1 \
 262                                | OR_FCM_TRLX \
 263                                | OR_FCM_EHTR)
 264
 265 #ifdef CONFIG_NAND
 266 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 267 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 268 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 269 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 270 #else
 271 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 272 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 273 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 274 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 275 #endif
 276 #else
 277 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 278 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 279 #endif /* CONFIG_NAND_FSL_ELBC */
 280
 281 #define CONFIG_SYS_FLASH_EMPTY_INFO
 282 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 283 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 284
 285 #define CONFIG_BOARD_EARLY_INIT_F
 286 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 287 #define CONFIG_MISC_INIT_R
 288
 289 #define CONFIG_HWCONFIG
 290
 291 /* define to use L1 as initial stack */
 292 #define CONFIG_L1_INIT_RAM
 293 #define CONFIG_SYS_INIT_RAM_LOCK
 294 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 295 #ifdef CONFIG_PHYS_64BIT
 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 298 /* The assembler doesn't like typecast */
 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 300         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 301           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 302 #else
 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 306 #endif
 307 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 308
 309 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 310                                         GENERATED_GBL_DATA_SIZE)
 311 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 312
 313 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 314 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 315
 316 /* Serial Port - controlled on board with jumper J8
 317  * open - index 2
 318  * shorted - index 1
 319  */
 320 #define CONFIG_CONS_INDEX       1
 321 #define CONFIG_SYS_NS16550_SERIAL
 322 #define CONFIG_SYS_NS16550_REG_SIZE     1
 323 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 324
 325 #define CONFIG_SYS_BAUDRATE_TABLE       \
 326         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 327
 328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 330 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 331 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 332
 333 /* I2C */
 334 #define CONFIG_SYS_I2C
 335 #define CONFIG_SYS_I2C_FSL
 336 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 337 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 338 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 339 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 340 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 341 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 342
 343 /*
 344  * RapidIO
 345  */
 346 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 347 #ifdef CONFIG_PHYS_64BIT
 348 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 349 #else
 350 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 351 #endif
 352 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 353
 354 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 355 #ifdef CONFIG_PHYS_64BIT
 356 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 357 #else
 358 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 359 #endif
 360 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 361
 362 /*
 363  * for slave u-boot IMAGE instored in master memory space,
 364  * PHYS must be aligned based on the SIZE
 365  */
 366 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 370 /*
 371  * for slave UCODE and ENV instored in master memory space,
 372  * PHYS must be aligned based on the SIZE
 373  */
 374 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 375 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 376 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 377
 378 /* slave core release by master*/
 379 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 380 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 381
 382 /*
 383  * SRIO_PCIE_BOOT - SLAVE
 384  */
 385 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 386 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 387 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 388                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 389 #endif
 390
 391 /*
 392  * eSPI - Enhanced SPI
 393  */
 394 #define CONFIG_SF_DEFAULT_SPEED         10000000
 395 #define CONFIG_SF_DEFAULT_MODE          0
 396
 397 /*
 398  * General PCI
 399  * Memory space is mapped 1-1, but I/O space must start from 0.
 400  */
 401
 402 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 403 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 404 #ifdef CONFIG_PHYS_64BIT
 405 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 406 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 407 #else
 408 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 409 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 410 #endif
 411 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 412 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 413 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 414 #ifdef CONFIG_PHYS_64BIT
 415 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 416 #else
 417 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 418 #endif
 419 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 420
 421 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 422 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 423 #ifdef CONFIG_PHYS_64BIT
 424 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 425 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 426 #else
 427 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 428 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 429 #endif
 430 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 431 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 432 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 433 #ifdef CONFIG_PHYS_64BIT
 434 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 435 #else
 436 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 437 #endif
 438 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 439
 440 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 441 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 442 #ifdef CONFIG_PHYS_64BIT
 443 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 444 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 445 #else
 446 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 447 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 448 #endif
 449 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 450 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 451 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 452 #ifdef CONFIG_PHYS_64BIT
 453 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 454 #else
 455 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 456 #endif
 457 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 458
 459 /* Qman/Bman */
 460 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 461 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 462 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 463 #ifdef CONFIG_PHYS_64BIT
 464 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 465 #else
 466 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 467 #endif
 468 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 469 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 470 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 471 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 472 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 473 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 474                                         CONFIG_SYS_BMAN_CENA_SIZE)
 475 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 476 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 477 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 478 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 479 #ifdef CONFIG_PHYS_64BIT
 480 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 481 #else
 482 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 483 #endif
 484 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 485 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 486 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 487 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 488 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 489 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 490                                         CONFIG_SYS_QMAN_CENA_SIZE)
 491 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 492 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 493
 494 #define CONFIG_SYS_DPAA_FMAN
 495 #define CONFIG_SYS_DPAA_PME
 496 /* Default address of microcode for the Linux Fman driver */
 497 #if defined(CONFIG_SPIFLASH)
 498 /*
 499  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 500  * env, so we got 0x110000.
 501  */
 502 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 503 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 504 #elif defined(CONFIG_SDCARD)
 505 /*
 506  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 507  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 508  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 509  */
 510 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 511 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 512 #elif defined(CONFIG_NAND)
 513 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 514 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 515 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 516 /*
 517  * Slave has no ucode locally, it can fetch this from remote. When implementing
 518  * in two corenet boards, slave's ucode could be stored in master's memory
 519  * space, the address can be mapped from slave TLB->slave LAW->
 520  * slave SRIO or PCIE outbound window->master inbound window->
 521  * master LAW->the ucode address in master's memory space.
 522  */
 523 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 524 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 525 #else
 526 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 527 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 528 #endif
 529 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 530 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 531
 532 #ifdef CONFIG_SYS_DPAA_FMAN
 533 #define CONFIG_FMAN_ENET
 534 #define CONFIG_PHYLIB_10G
 535 #define CONFIG_PHY_VITESSE
 536 #define CONFIG_PHY_TERANETICS
 537 #endif
 538
 539 #ifdef CONFIG_PCI
 540 #define CONFIG_PCI_INDIRECT_BRIDGE
 541
 542 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 543 #define CONFIG_DOS_PARTITION
 544 #endif  /* CONFIG_PCI */
 545
 546 /* SATA */
 547 #define CONFIG_FSL_SATA_V2
 548
 549 #ifdef CONFIG_FSL_SATA_V2
 550 #define CONFIG_FSL_SATA
 551 #define CONFIG_LIBATA
 552
 553 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 554 #define CONFIG_SATA1
 555 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 556 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 557 #define CONFIG_SATA2
 558 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 559 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 560
 561 #define CONFIG_LBA48
 562 #define CONFIG_CMD_SATA
 563 #define CONFIG_DOS_PARTITION
 564 #endif
 565
 566 #ifdef CONFIG_FMAN_ENET
 567 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 568 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 569 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 570 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 571 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 572
 573 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 574 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 575 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 576 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 577
 578 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 579
 580 #define CONFIG_SYS_TBIPA_VALUE  8
 581 #define CONFIG_MII              /* MII PHY management */
 582 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 583 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 584 #endif
 585
 586 /*
 587  * Environment
 588  */
 589 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 590 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 591
 592 /*
 593  * Command line configuration.
 594  */
 595 #define CONFIG_CMD_ERRATA
 596 #define CONFIG_CMD_IRQ
 597
 598 #ifdef CONFIG_PCI
 599 #define CONFIG_CMD_PCI
 600 #endif
 601
 602 /*
 603 * USB
 604 */
 605 #define CONFIG_HAS_FSL_DR_USB
 606 #define CONFIG_HAS_FSL_MPH_USB
 607
 608 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 609 #define CONFIG_USB_EHCI
 610 #define CONFIG_USB_EHCI_FSL
 611 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 612 #endif
 613
 614 #define CONFIG_MMC
 615
 616 #ifdef CONFIG_MMC
 617 #define CONFIG_FSL_ESDHC
 618 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 619 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 620 #define CONFIG_GENERIC_MMC
 621 #define CONFIG_DOS_PARTITION
 622 #endif
 623
 624 /* Hash command with SHA acceleration supported in hardware */
 625 #ifdef CONFIG_FSL_CAAM
 626 #define CONFIG_CMD_HASH
 627 #define CONFIG_SHA_HW_ACCEL
 628 #endif
 629
 630 /*
 631  * Miscellaneous configurable options
 632  */
 633 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 634 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 635 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 636 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 637 #ifdef CONFIG_CMD_KGDB
 638 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 639 #else
 640 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 641 #endif
 642 /* Print Buffer Size */
 643 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 644                                 sizeof(CONFIG_SYS_PROMPT)+16)
 645 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 646 /* Boot Argument Buffer Size */
 647 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 648
 649 /*
 650  * For booting Linux, the board info and command line data
 651  * have to be in the first 64 MB of memory, since this is
 652  * the maximum mapped by the Linux kernel during initialization.
 653  */
 654 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 655 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 656
 657 #ifdef CONFIG_CMD_KGDB
 658 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 659 #endif
 660
 661 /*
 662  * Environment Configuration
 663  */
 664 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 665 #define CONFIG_BOOTFILE         "uImage"
 666 #define CONFIG_UBOOTPATH        u-boot.bin
 667
 668 /* default location for tftp and bootm */
 669 #define CONFIG_LOADADDR         1000000
 670
 671
 672 #define CONFIG_BAUDRATE 115200
 673
 674 #define __USB_PHY_TYPE  utmi
 675
 676 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 677         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 678         "bank_intlv=cs0_cs1\0"                                  \
 679         "netdev=eth0\0"                                         \
 680         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 681         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 682         "tftpflash=tftpboot $loadaddr $uboot && "               \
 683         "protect off $ubootaddr +$filesize && "                 \
 684         "erase $ubootaddr +$filesize && "                       \
 685         "cp.b $loadaddr $ubootaddr $filesize && "               \
 686         "protect on $ubootaddr +$filesize && "                  \
 687         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 688         "consoledev=ttyS0\0"                                    \
 689         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 690         "usb_dr_mode=host\0"                                    \
 691         "ramdiskaddr=2000000\0"                                 \
 692         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 693         "fdtaddr=1e00000\0"                                     \
 694         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 695         "bdev=sda3\0"
 696
 697 #define CONFIG_HDBOOT                                   \
 698         "setenv bootargs root=/dev/$bdev rw "           \
 699         "console=$consoledev,$baudrate $othbootargs;"   \
 700         "tftp $loadaddr $bootfile;"                     \
 701         "tftp $fdtaddr $fdtfile;"                       \
 702         "bootm $loadaddr - $fdtaddr"
 703
 704 #define CONFIG_NFSBOOTCOMMAND                   \
 705         "setenv bootargs root=/dev/nfs rw "     \
 706         "nfsroot=$serverip:$rootpath "          \
 707         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 708         "console=$consoledev,$baudrate $othbootargs;"   \
 709         "tftp $loadaddr $bootfile;"             \
 710         "tftp $fdtaddr $fdtfile;"               \
 711         "bootm $loadaddr - $fdtaddr"
 712
 713 #define CONFIG_RAMBOOTCOMMAND                           \
 714         "setenv bootargs root=/dev/ram rw "             \
 715         "console=$consoledev,$baudrate $othbootargs;"   \
 716         "tftp $ramdiskaddr $ramdiskfile;"               \
 717         "tftp $loadaddr $bootfile;"                     \
 718         "tftp $fdtaddr $fdtfile;"                       \
 719         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 720
 721 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 722
 723 #include <asm/fsl_secure_boot.h>
 724
 725 #endif  /* __CONFIG_H */