Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u...
[platform/kernel/u-boot.git] / include / configs / P2041RDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
4  * Copyright 2020-2021 NXP
5  */
6
7 /*
8  * P2041 RDB board configuration file
9  * Also supports P2040 RDB
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
17 #endif
18
19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
20 /* Set 1M boot space */
21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
25 #endif
26
27 /* High Level Configuration Options */
28 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
29
30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
31 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
32 #endif
33
34 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
35 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
36 #define CONFIG_PCIE1                    /* PCIE controller 1 */
37 #define CONFIG_PCIE2                    /* PCIE controller 2 */
38 #define CONFIG_PCIE3                    /* PCIE controller 3 */
39
40 #define CONFIG_SYS_SRIO
41 #define CONFIG_SRIO1                    /* SRIO port 1 */
42 #define CONFIG_SRIO2                    /* SRIO port 2 */
43 #define CONFIG_SRIO_PCIE_BOOT_MASTER
44 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
45
46 #if defined(CONFIG_SPIFLASH)
47 #elif defined(CONFIG_SDCARD)
48         #define CONFIG_FSL_FIXED_MMC_LOCATION
49 #endif
50
51 #ifndef __ASSEMBLY__
52 #include <linux/stringify.h>
53 #endif
54
55 /*
56  * These can be toggled for performance analysis, otherwise use default.
57  */
58 #define CONFIG_SYS_CACHE_STASHING
59 #define CONFIG_BACKSIDE_L2_CACHE
60 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
61 #define CONFIG_BTB                      /* toggle branch predition */
62
63 #define CONFIG_ENABLE_36BIT_PHYS
64
65 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
66
67 /*
68  *  Config the L3 Cache as L3 SRAM
69  */
70 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
71 #ifdef CONFIG_PHYS_64BIT
72 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
73                 CONFIG_RAMBOOT_TEXT_BASE)
74 #else
75 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
76 #endif
77 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
78 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
79
80 #ifdef CONFIG_PHYS_64BIT
81 #define CONFIG_SYS_DCSRBAR              0xf0000000
82 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
83 #endif
84
85 /* EEPROM */
86 #define CONFIG_SYS_I2C_EEPROM_NXID
87 #define CONFIG_SYS_EEPROM_BUS_NUM       0
88
89 /*
90  * DDR Setup
91  */
92 #define CONFIG_VERY_BIG_RAM
93 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
94 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
95
96 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
97 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
98
99 #define CONFIG_SYS_SPD_BUS_NUM  0
100 #define SPD_EEPROM_ADDRESS      0x52
101 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
102
103 /*
104  * Local Bus Definitions
105  */
106
107 /* Set the local bus clock 1/8 of platform clock */
108 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
109
110 /*
111  * This board doesn't have a promjet connector.
112  * However, it uses commone corenet board LAW and TLB.
113  * It is necessary to use the same start address with proper offset.
114  */
115 #define CONFIG_SYS_FLASH_BASE           0xe0000000
116 #ifdef CONFIG_PHYS_64BIT
117 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
118 #else
119 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
120 #endif
121
122 #define CONFIG_SYS_FLASH_BR_PRELIM \
123                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
124                 BR_PS_16 | BR_V)
125 #define CONFIG_SYS_FLASH_OR_PRELIM \
126                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
127                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
128
129 #define CONFIG_FSL_CPLD
130 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
131 #ifdef CONFIG_PHYS_64BIT
132 #define CPLD_BASE_PHYS          0xfffdf0000ull
133 #else
134 #define CPLD_BASE_PHYS          CPLD_BASE
135 #endif
136
137 #define PIXIS_LBMAP_SWITCH      7
138 #define PIXIS_LBMAP_MASK        0xf0
139 #define PIXIS_LBMAP_SHIFT       4
140 #define PIXIS_LBMAP_ALTBANK     0x40
141
142 #define CONFIG_SYS_FLASH_QUIET_TEST
143 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
144
145 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
146 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
147 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
148
149 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
150
151 #if defined(CONFIG_RAMBOOT_PBL)
152 #define CONFIG_SYS_RAMBOOT
153 #endif
154
155 /* Nand Flash */
156 #ifdef CONFIG_NAND_FSL_ELBC
157 #define CONFIG_SYS_NAND_BASE            0xffa00000
158 #ifdef CONFIG_PHYS_64BIT
159 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
160 #else
161 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
162 #endif
163
164 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
165 #define CONFIG_SYS_MAX_NAND_DEVICE      1
166
167 /* NAND flash config */
168 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
169                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
170                                | BR_PS_8               /* Port Size = 8 bit */ \
171                                | BR_MS_FCM             /* MSEL = FCM */ \
172                                | BR_V)                 /* valid */
173 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
174                                | OR_FCM_PGS            /* Large Page*/ \
175                                | OR_FCM_CSCT \
176                                | OR_FCM_CST \
177                                | OR_FCM_CHT \
178                                | OR_FCM_SCY_1 \
179                                | OR_FCM_TRLX \
180                                | OR_FCM_EHTR)
181 #endif /* CONFIG_NAND_FSL_ELBC */
182
183 #define CONFIG_SYS_FLASH_EMPTY_INFO
184 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
185
186 #define CONFIG_HWCONFIG
187
188 /* define to use L1 as initial stack */
189 #define CONFIG_L1_INIT_RAM
190 #define CONFIG_SYS_INIT_RAM_LOCK
191 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
192 #ifdef CONFIG_PHYS_64BIT
193 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
195 /* The assembler doesn't like typecast */
196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
197         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
198           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
199 #else
200 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
201 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
202 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
203 #endif
204 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
205
206 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
207                                         GENERATED_GBL_DATA_SIZE)
208 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
209
210 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
211
212 /* Serial Port - controlled on board with jumper J8
213  * open - index 2
214  * shorted - index 1
215  */
216 #define CONFIG_SYS_NS16550_SERIAL
217 #define CONFIG_SYS_NS16550_REG_SIZE     1
218 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
219
220 #define CONFIG_SYS_BAUDRATE_TABLE       \
221         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
222
223 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
224 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
225 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
226 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
227
228 /* I2C */
229
230
231 /*
232  * RapidIO
233  */
234 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
235 #ifdef CONFIG_PHYS_64BIT
236 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
237 #else
238 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
239 #endif
240 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
241
242 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
243 #ifdef CONFIG_PHYS_64BIT
244 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
245 #else
246 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
247 #endif
248 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
249
250 /*
251  * for slave u-boot IMAGE instored in master memory space,
252  * PHYS must be aligned based on the SIZE
253  */
254 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
255 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
256 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
257 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
258 /*
259  * for slave UCODE and ENV instored in master memory space,
260  * PHYS must be aligned based on the SIZE
261  */
262 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
263 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
264 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
265
266 /* slave core release by master*/
267 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
268 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
269
270 /*
271  * SRIO_PCIE_BOOT - SLAVE
272  */
273 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
274 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
275 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
276                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
277 #endif
278
279 /*
280  * eSPI - Enhanced SPI
281  */
282
283 /*
284  * General PCI
285  * Memory space is mapped 1-1, but I/O space must start from 0.
286  */
287
288 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
289 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
290 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
291 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
292 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
293
294 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
295 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
296 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
297 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
298 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
299
300 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
301 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
302 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
303 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
304 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
305
306 /* Qman/Bman */
307 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
308 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
309 #ifdef CONFIG_PHYS_64BIT
310 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
311 #else
312 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
313 #endif
314 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
315 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
316 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
317 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
318 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
319 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
320                                         CONFIG_SYS_BMAN_CENA_SIZE)
321 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
322 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
323 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
324 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
325 #ifdef CONFIG_PHYS_64BIT
326 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
327 #else
328 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
329 #endif
330 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
331 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
332 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
333 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
334 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
335 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
336                                         CONFIG_SYS_QMAN_CENA_SIZE)
337 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
338 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
339
340 #define CONFIG_SYS_DPAA_FMAN
341 #define CONFIG_SYS_DPAA_PME
342 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
343
344 #ifdef CONFIG_PCI
345 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
346 #endif  /* CONFIG_PCI */
347
348 /* SATA */
349 #define CONFIG_FSL_SATA_V2
350
351 #ifdef CONFIG_FSL_SATA_V2
352 #define CONFIG_SATA1
353 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
354 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
355 #define CONFIG_SATA2
356 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
357 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
358
359 #define CONFIG_LBA48
360 #endif
361
362 #ifdef CONFIG_FMAN_ENET
363 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
364 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
365 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
366 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
367 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
368
369 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
370 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
371 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
372 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
373
374 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
375
376 #define CONFIG_SYS_TBIPA_VALUE  8
377 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
378 #endif
379
380 /*
381  * Environment
382  */
383 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
384 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
385
386 /*
387 * USB
388 */
389 #define CONFIG_HAS_FSL_DR_USB
390 #define CONFIG_HAS_FSL_MPH_USB
391
392 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
393 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
394 #endif
395
396 #ifdef CONFIG_MMC
397 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
398 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
399 #endif
400
401 /*
402  * Miscellaneous configurable options
403  */
404
405 /*
406  * For booting Linux, the board info and command line data
407  * have to be in the first 64 MB of memory, since this is
408  * the maximum mapped by the Linux kernel during initialization.
409  */
410 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
411 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
412
413 /*
414  * Environment Configuration
415  */
416 #define CONFIG_ROOTPATH         "/opt/nfsroot"
417 #define CONFIG_BOOTFILE         "uImage"
418 #define CONFIG_UBOOTPATH        u-boot.bin
419
420 #define __USB_PHY_TYPE  utmi
421
422 #define CONFIG_EXTRA_ENV_SETTINGS                               \
423         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
424         "bank_intlv=cs0_cs1\0"                                  \
425         "netdev=eth0\0"                                         \
426         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
427         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
428         "tftpflash=tftpboot $loadaddr $uboot && "               \
429         "protect off $ubootaddr +$filesize && "                 \
430         "erase $ubootaddr +$filesize && "                       \
431         "cp.b $loadaddr $ubootaddr $filesize && "               \
432         "protect on $ubootaddr +$filesize && "                  \
433         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
434         "consoledev=ttyS0\0"                                    \
435         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
436         "usb_dr_mode=host\0"                                    \
437         "ramdiskaddr=2000000\0"                                 \
438         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
439         "fdtaddr=1e00000\0"                                     \
440         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
441         "bdev=sda3\0"
442
443 #include <asm/fsl_secure_boot.h>
444
445 #endif  /* __CONFIG_H */