1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
20 /* Set 1M boot space */
21 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
22 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
23 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 /* High Level Configuration Options */
29 #ifndef CONFIG_RESET_VECTOR_ADDRESS
30 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
33 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
36 #include <linux/stringify.h>
40 * These can be toggled for performance analysis, otherwise use default.
42 #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
44 #define CONFIG_POST CFG_SYS_POST_MEMORY /* test POST memory test */
47 * Config the L3 Cache as L3 SRAM
49 #define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
50 #ifdef CONFIG_PHYS_64BIT
51 #define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
52 CONFIG_RAMBOOT_TEXT_BASE)
54 #define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR
57 #ifdef CONFIG_PHYS_64BIT
58 #define CFG_SYS_DCSRBAR 0xf0000000
59 #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
65 #define CONFIG_VERY_BIG_RAM
66 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000
67 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
69 #define SPD_EEPROM_ADDRESS 0x52
70 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
73 * Local Bus Definitions
76 /* Set the local bus clock 1/8 of platform clock */
77 #define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8
80 * This board doesn't have a promjet connector.
81 * However, it uses commone corenet board LAW and TLB.
82 * It is necessary to use the same start address with proper offset.
84 #define CFG_SYS_FLASH_BASE 0xe0000000
85 #ifdef CONFIG_PHYS_64BIT
86 #define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
88 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
91 #define CONFIG_FSL_CPLD
92 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
93 #ifdef CONFIG_PHYS_64BIT
94 #define CPLD_BASE_PHYS 0xfffdf0000ull
96 #define CPLD_BASE_PHYS CPLD_BASE
99 #define PIXIS_LBMAP_SWITCH 7
100 #define PIXIS_LBMAP_MASK 0xf0
101 #define PIXIS_LBMAP_SHIFT 4
102 #define PIXIS_LBMAP_ALTBANK 0x40
104 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
107 #ifdef CONFIG_NAND_FSL_ELBC
108 #define CFG_SYS_NAND_BASE 0xffa00000
109 #ifdef CONFIG_PHYS_64BIT
110 #define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull
112 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
115 #define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE}
117 /* NAND flash config */
118 #define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
119 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
120 | BR_PS_8 /* Port Size = 8 bit */ \
121 | BR_MS_FCM /* MSEL = FCM */ \
123 #define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
124 | OR_FCM_PGS /* Large Page*/ \
131 #endif /* CONFIG_NAND_FSL_ELBC */
133 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
135 /* define to use L1 as initial stack */
136 #define CONFIG_L1_INIT_RAM
137 #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
138 #ifdef CONFIG_PHYS_64BIT
139 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
140 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
141 /* The assembler doesn't like typecast */
142 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
143 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
144 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
146 #define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
147 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
148 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
150 #define CFG_SYS_INIT_RAM_SIZE 0x00004000
152 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 /* Serial Port - controlled on board with jumper J8
158 #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
160 #define CFG_SYS_BAUDRATE_TABLE \
161 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
163 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
164 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
165 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
166 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
174 #define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
175 #ifdef CONFIG_PHYS_64BIT
176 #define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
178 #define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000
180 #define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
182 #define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
183 #ifdef CONFIG_PHYS_64BIT
184 #define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
186 #define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000
188 #define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
191 * for slave u-boot IMAGE instored in master memory space,
192 * PHYS must be aligned based on the SIZE
194 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
195 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
196 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
197 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
199 * for slave UCODE and ENV instored in master memory space,
200 * PHYS must be aligned based on the SIZE
202 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
203 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
204 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
206 /* slave core release by master*/
207 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
208 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
211 * SRIO_PCIE_BOOT - SLAVE
213 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
214 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
215 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
216 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
220 * eSPI - Enhanced SPI
225 * Memory space is mapped 1-1, but I/O space must start from 0.
228 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
229 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
230 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
231 #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
232 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
234 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
235 #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
236 #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
237 #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
238 #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
240 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
241 #define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
242 #define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
245 #define CFG_SYS_BMAN_NUM_PORTALS 10
246 #define CFG_SYS_BMAN_MEM_BASE 0xf4000000
247 #ifdef CONFIG_PHYS_64BIT
248 #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
250 #define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
252 #define CFG_SYS_BMAN_MEM_SIZE 0x00200000
253 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
254 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
255 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
256 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
257 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
258 CFG_SYS_BMAN_CENA_SIZE)
259 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
260 #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
261 #define CFG_SYS_QMAN_NUM_PORTALS 10
262 #define CFG_SYS_QMAN_MEM_BASE 0xf4200000
263 #ifdef CONFIG_PHYS_64BIT
264 #define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull
266 #define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
268 #define CFG_SYS_QMAN_MEM_SIZE 0x00200000
269 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
270 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
271 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
272 CFG_SYS_QMAN_CENA_SIZE)
273 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
274 #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
276 #ifdef CONFIG_FMAN_ENET
277 #define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
278 #define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
279 #define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
280 #define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
281 #define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
283 #define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
284 #define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
285 #define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
286 #define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
288 #define CFG_SYS_FM1_10GEC1_PHY_ADDR 0
290 #define CFG_SYS_TBIPA_VALUE 8
294 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
298 * Miscellaneous configurable options
302 * For booting Linux, the board info and command line data
303 * have to be in the first 64 MB of memory, since this is
304 * the maximum mapped by the Linux kernel during initialization.
306 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
309 * Environment Configuration
311 #define CONFIG_ROOTPATH "/opt/nfsroot"
312 #define CONFIG_UBOOTPATH u-boot.bin
314 #define __USB_PHY_TYPE utmi
316 #define CONFIG_EXTRA_ENV_SETTINGS \
317 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
318 "bank_intlv=cs0_cs1\0" \
320 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
321 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
322 "tftpflash=tftpboot $loadaddr $uboot && " \
323 "protect off $ubootaddr +$filesize && " \
324 "erase $ubootaddr +$filesize && " \
325 "cp.b $loadaddr $ubootaddr $filesize && " \
326 "protect on $ubootaddr +$filesize && " \
327 "cmp.b $loadaddr $ubootaddr $filesize\0" \
328 "consoledev=ttyS0\0" \
329 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
330 "usb_dr_mode=host\0" \
331 "ramdiskaddr=2000000\0" \
332 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
333 "fdtaddr=1e00000\0" \
334 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
337 #include <asm/fsl_secure_boot.h>
339 #endif /* __CONFIG_H */