2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P2041 RDB board configuration file
25 * Also supports P2040 RDB
30 #define CONFIG_P2041RDB
31 #define CONFIG_PHYS_64BIT
32 #define CONFIG_PPC_P2041
34 #ifdef CONFIG_RAMBOOT_PBL
35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
40 /* Set 1M boot space */
41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
45 #define CONFIG_SYS_NO_FLASH
48 /* High Level Configuration Options */
50 #define CONFIG_E500 /* BOOKE e500 family */
51 #define CONFIG_E500MC /* BOOKE e500mc family */
52 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
53 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
54 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
55 #define CONFIG_MP /* support multiple processors */
57 #ifndef CONFIG_SYS_TEXT_BASE
58 #define CONFIG_SYS_TEXT_BASE 0xeff80000
61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
62 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
65 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
66 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
67 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
68 #define CONFIG_PCI /* Enable PCI/PCIE */
69 #define CONFIG_PCIE1 /* PCIE controler 1 */
70 #define CONFIG_PCIE2 /* PCIE controler 2 */
71 #define CONFIG_PCIE3 /* PCIE controler 3 */
72 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
73 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
75 #define CONFIG_SYS_SRIO
76 #define CONFIG_SRIO1 /* SRIO port 1 */
77 #define CONFIG_SRIO2 /* SRIO port 2 */
78 #define CONFIG_SYS_DPAA_RMAN /* RMan */
80 #define CONFIG_FSL_LAW /* Use common FSL init code */
82 #define CONFIG_ENV_OVERWRITE
84 #ifdef CONFIG_SYS_NO_FLASH
85 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
86 #define CONFIG_ENV_IS_NOWHERE
89 #define CONFIG_FLASH_CFI_DRIVER
90 #define CONFIG_SYS_FLASH_CFI
91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
94 #if defined(CONFIG_SPIFLASH)
95 #define CONFIG_SYS_EXTRA_ENV_RELOC
96 #define CONFIG_ENV_IS_IN_SPI_FLASH
97 #define CONFIG_ENV_SPI_BUS 0
98 #define CONFIG_ENV_SPI_CS 0
99 #define CONFIG_ENV_SPI_MAX_HZ 10000000
100 #define CONFIG_ENV_SPI_MODE 0
101 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
102 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
103 #define CONFIG_ENV_SECT_SIZE 0x10000
104 #elif defined(CONFIG_SDCARD)
105 #define CONFIG_SYS_EXTRA_ENV_RELOC
106 #define CONFIG_ENV_IS_IN_MMC
107 #define CONFIG_FSL_FIXED_MMC_LOCATION
108 #define CONFIG_SYS_MMC_ENV_DEV 0
109 #define CONFIG_ENV_SIZE 0x2000
110 #define CONFIG_ENV_OFFSET (512 * 1097)
111 #elif defined(CONFIG_NAND)
112 #define CONFIG_SYS_EXTRA_ENV_RELOC
113 #define CONFIG_ENV_IS_IN_NAND
114 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
115 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
116 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
117 #define CONFIG_ENV_IS_IN_REMOTE
118 #define CONFIG_ENV_ADDR 0xffe20000
119 #define CONFIG_ENV_SIZE 0x2000
120 #elif defined(CONFIG_ENV_IS_NOWHERE)
121 #define CONFIG_ENV_SIZE 0x2000
123 #define CONFIG_ENV_IS_IN_FLASH
124 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
125 - CONFIG_ENV_SECT_SIZE)
126 #define CONFIG_ENV_SIZE 0x2000
127 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
131 unsigned long get_board_sys_clk(unsigned long dummy);
133 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
136 * These can be toggled for performance analysis, otherwise use default.
138 #define CONFIG_SYS_CACHE_STASHING
139 #define CONFIG_BACKSIDE_L2_CACHE
140 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
141 #define CONFIG_BTB /* toggle branch predition */
143 #define CONFIG_ENABLE_36BIT_PHYS
145 #ifdef CONFIG_PHYS_64BIT
146 #define CONFIG_ADDR_MAP
147 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
150 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
151 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
152 #define CONFIG_SYS_MEMTEST_END 0x00400000
153 #define CONFIG_SYS_ALT_MEMTEST
154 #define CONFIG_PANIC_HANG /* do not reset board on panic */
157 * Config the L3 Cache as L3 SRAM
159 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
160 #ifdef CONFIG_PHYS_64BIT
161 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
162 CONFIG_RAMBOOT_TEXT_BASE)
164 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
166 #define CONFIG_SYS_L3_SIZE (1024 << 10)
167 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
169 #ifdef CONFIG_PHYS_64BIT
170 #define CONFIG_SYS_DCSRBAR 0xf0000000
171 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
175 #define CONFIG_ID_EEPROM
176 #define CONFIG_SYS_I2C_EEPROM_NXID
177 #define CONFIG_SYS_EEPROM_BUS_NUM 0
178 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
184 #define CONFIG_VERY_BIG_RAM
185 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
186 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
188 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
189 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
191 #define CONFIG_DDR_SPD
192 #define CONFIG_FSL_DDR3
194 #define CONFIG_SYS_SPD_BUS_NUM 0
195 #define SPD_EEPROM_ADDRESS 0x52
196 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
199 * Local Bus Definitions
202 /* Set the local bus clock 1/8 of platform clock */
203 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
206 * This board doesn't have a promjet connector.
207 * However, it uses commone corenet board LAW and TLB.
208 * It is necessary to use the same start address with proper offset.
210 #define CONFIG_SYS_FLASH_BASE 0xe0000000
211 #ifdef CONFIG_PHYS_64BIT
212 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
214 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
217 #define CONFIG_SYS_FLASH_BR_PRELIM \
218 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
220 #define CONFIG_SYS_FLASH_OR_PRELIM \
221 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
222 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
224 #define CONFIG_FSL_CPLD
225 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
226 #ifdef CONFIG_PHYS_64BIT
227 #define CPLD_BASE_PHYS 0xfffdf0000ull
229 #define CPLD_BASE_PHYS CPLD_BASE
232 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
233 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
235 #define PIXIS_LBMAP_SWITCH 7
236 #define PIXIS_LBMAP_MASK 0xf0
237 #define PIXIS_LBMAP_SHIFT 4
238 #define PIXIS_LBMAP_ALTBANK 0x40
240 #define CONFIG_SYS_FLASH_QUIET_TEST
241 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
243 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
244 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
245 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
248 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
250 #if defined(CONFIG_RAMBOOT_PBL)
251 #define CONFIG_SYS_RAMBOOT
254 #define CONFIG_NAND_FSL_ELBC
256 #ifdef CONFIG_NAND_FSL_ELBC
257 #define CONFIG_SYS_NAND_BASE 0xffa00000
258 #ifdef CONFIG_PHYS_64BIT
259 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
261 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
264 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
265 #define CONFIG_SYS_MAX_NAND_DEVICE 1
266 #define CONFIG_MTD_NAND_VERIFY_WRITE
267 #define CONFIG_CMD_NAND
268 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
270 /* NAND flash config */
271 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
272 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
273 | BR_PS_8 /* Port Size = 8 bit */ \
274 | BR_MS_FCM /* MSEL = FCM */ \
276 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
277 | OR_FCM_PGS /* Large Page*/ \
286 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
287 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
288 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
289 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
291 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
292 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
293 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
294 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
297 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
298 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
299 #endif /* CONFIG_NAND_FSL_ELBC */
301 #define CONFIG_SYS_FLASH_EMPTY_INFO
302 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
303 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
305 #define CONFIG_BOARD_EARLY_INIT_F
306 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
307 #define CONFIG_MISC_INIT_R
309 #define CONFIG_HWCONFIG
311 /* define to use L1 as initial stack */
312 #define CONFIG_L1_INIT_RAM
313 #define CONFIG_SYS_INIT_RAM_LOCK
314 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
315 #ifdef CONFIG_PHYS_64BIT
316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
318 /* The assembler doesn't like typecast */
319 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
320 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
321 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
323 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
324 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
325 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
327 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
329 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
330 GENERATED_GBL_DATA_SIZE)
331 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
333 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
334 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
336 /* Serial Port - controlled on board with jumper J8
340 #define CONFIG_CONS_INDEX 1
341 #define CONFIG_SYS_NS16550
342 #define CONFIG_SYS_NS16550_SERIAL
343 #define CONFIG_SYS_NS16550_REG_SIZE 1
344 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
346 #define CONFIG_SYS_BAUDRATE_TABLE \
347 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
349 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
350 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
351 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
352 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
354 /* Use the HUSH parser */
355 #define CONFIG_SYS_HUSH_PARSER
357 /* pass open firmware flat tree */
358 #define CONFIG_OF_LIBFDT
359 #define CONFIG_OF_BOARD_SETUP
360 #define CONFIG_OF_STDOUT_VIA_ALIAS
362 /* new uImage format support */
364 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
367 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
368 #define CONFIG_HARD_I2C /* I2C with hardware support */
369 #define CONFIG_I2C_MULTI_BUS
370 #define CONFIG_I2C_CMD_TREE
371 #define CONFIG_SYS_I2C_SPEED 400000
372 #define CONFIG_SYS_I2C_SLAVE 0x7F
373 #define CONFIG_SYS_I2C_OFFSET 0x118000
374 #define CONFIG_SYS_I2C2_OFFSET 0x118100
379 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
380 #ifdef CONFIG_PHYS_64BIT
381 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
383 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
385 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
387 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
388 #ifdef CONFIG_PHYS_64BIT
389 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
391 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
393 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
396 * for slave u-boot IMAGE instored in master memory space,
397 * PHYS must be aligned based on the SIZE
399 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
400 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
401 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
402 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
404 * for slave UCODE and ENV instored in master memory space,
405 * PHYS must be aligned based on the SIZE
407 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
408 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
409 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
411 /* slave core release by master*/
412 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
413 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
416 * SRIO_PCIE_BOOT - SLAVE
418 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
419 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
420 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
421 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
425 * eSPI - Enhanced SPI
427 #define CONFIG_FSL_ESPI
428 #define CONFIG_SPI_FLASH
429 #define CONFIG_SPI_FLASH_SPANSION
430 #define CONFIG_CMD_SF
431 #define CONFIG_SF_DEFAULT_SPEED 10000000
432 #define CONFIG_SF_DEFAULT_MODE 0
436 * Memory space is mapped 1-1, but I/O space must start from 0.
439 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
440 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
441 #ifdef CONFIG_PHYS_64BIT
442 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
443 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
445 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
446 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
448 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
449 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
450 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
451 #ifdef CONFIG_PHYS_64BIT
452 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
454 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
456 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
458 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
459 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
460 #ifdef CONFIG_PHYS_64BIT
461 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
462 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
464 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
465 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
467 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
468 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
469 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
470 #ifdef CONFIG_PHYS_64BIT
471 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
473 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
475 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
477 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
478 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
479 #ifdef CONFIG_PHYS_64BIT
480 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
481 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
483 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
484 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
486 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
487 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
488 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
489 #ifdef CONFIG_PHYS_64BIT
490 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
492 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
494 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
497 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
498 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
499 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
500 #ifdef CONFIG_PHYS_64BIT
501 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
503 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
505 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
506 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
507 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
508 #ifdef CONFIG_PHYS_64BIT
509 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
511 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
513 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
515 #define CONFIG_SYS_DPAA_FMAN
516 #define CONFIG_SYS_DPAA_PME
517 /* Default address of microcode for the Linux Fman driver */
518 #if defined(CONFIG_SPIFLASH)
520 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
521 * env, so we got 0x110000.
523 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
524 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
525 #elif defined(CONFIG_SDCARD)
527 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
528 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
529 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
531 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
532 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
533 #elif defined(CONFIG_NAND)
534 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
535 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
536 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
538 * Slave has no ucode locally, it can fetch this from remote. When implementing
539 * in two corenet boards, slave's ucode could be stored in master's memory
540 * space, the address can be mapped from slave TLB->slave LAW->
541 * slave SRIO or PCIE outbound window->master inbound window->
542 * master LAW->the ucode address in master's memory space.
544 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
545 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
547 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
548 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
550 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
551 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
553 #ifdef CONFIG_SYS_DPAA_FMAN
554 #define CONFIG_FMAN_ENET
555 #define CONFIG_PHYLIB_10G
556 #define CONFIG_PHY_VITESSE
557 #define CONFIG_PHY_TERANETICS
561 #define CONFIG_PCI_PNP /* do pci plug-and-play */
564 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
565 #define CONFIG_DOS_PARTITION
566 #endif /* CONFIG_PCI */
569 #define CONFIG_FSL_SATA_V2
571 #ifdef CONFIG_FSL_SATA_V2
572 #define CONFIG_FSL_SATA
573 #define CONFIG_LIBATA
575 #define CONFIG_SYS_SATA_MAX_DEVICE 2
577 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
578 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
580 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
581 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
584 #define CONFIG_CMD_SATA
585 #define CONFIG_DOS_PARTITION
586 #define CONFIG_CMD_EXT2
589 #ifdef CONFIG_FMAN_ENET
590 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
591 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
592 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
593 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
594 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
596 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
597 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
598 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
599 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
601 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
603 #define CONFIG_SYS_TBIPA_VALUE 8
604 #define CONFIG_MII /* MII PHY management */
605 #define CONFIG_ETHPRIME "FM1@DTSEC1"
606 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
612 #define CONFIG_LOADS_ECHO /* echo on for serial download */
613 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
616 * Command line configuration.
618 #include <config_cmd_default.h>
620 #define CONFIG_CMD_DHCP
621 #define CONFIG_CMD_ELF
622 #define CONFIG_CMD_ERRATA
623 #define CONFIG_CMD_GREPENV
624 #define CONFIG_CMD_IRQ
625 #define CONFIG_CMD_I2C
626 #define CONFIG_CMD_MII
627 #define CONFIG_CMD_PING
628 #define CONFIG_CMD_SETEXPR
631 #define CONFIG_CMD_PCI
632 #define CONFIG_CMD_NET
638 #define CONFIG_HAS_FSL_DR_USB
639 #define CONFIG_HAS_FSL_MPH_USB
641 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
642 #define CONFIG_CMD_USB
643 #define CONFIG_USB_STORAGE
644 #define CONFIG_USB_EHCI
645 #define CONFIG_USB_EHCI_FSL
646 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
649 #define CONFIG_CMD_EXT2
654 #define CONFIG_FSL_ESDHC
655 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
656 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
657 #define CONFIG_CMD_MMC
658 #define CONFIG_GENERIC_MMC
659 #define CONFIG_CMD_EXT2
660 #define CONFIG_CMD_FAT
661 #define CONFIG_DOS_PARTITION
665 * Miscellaneous configurable options
667 #define CONFIG_SYS_LONGHELP /* undef to save memory */
668 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
669 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
670 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
671 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
672 #ifdef CONFIG_CMD_KGDB
673 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
675 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
677 /* Print Buffer Size */
678 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
679 sizeof(CONFIG_SYS_PROMPT)+16)
680 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
681 /* Boot Argument Buffer Size */
682 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
683 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */
686 * For booting Linux, the board info and command line data
687 * have to be in the first 64 MB of memory, since this is
688 * the maximum mapped by the Linux kernel during initialization.
690 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
691 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
693 #ifdef CONFIG_CMD_KGDB
694 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
695 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
699 * Environment Configuration
701 #define CONFIG_ROOTPATH "/opt/nfsroot"
702 #define CONFIG_BOOTFILE "uImage"
703 #define CONFIG_UBOOTPATH u-boot.bin
705 /* default location for tftp and bootm */
706 #define CONFIG_LOADADDR 1000000
708 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
710 #define CONFIG_BAUDRATE 115200
712 #define __USB_PHY_TYPE utmi
714 #define CONFIG_EXTRA_ENV_SETTINGS \
715 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
716 "bank_intlv=cs0_cs1\0" \
718 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
719 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
720 "tftpflash=tftpboot $loadaddr $uboot && " \
721 "protect off $ubootaddr +$filesize && " \
722 "erase $ubootaddr +$filesize && " \
723 "cp.b $loadaddr $ubootaddr $filesize && " \
724 "protect on $ubootaddr +$filesize && " \
725 "cmp.b $loadaddr $ubootaddr $filesize\0" \
726 "consoledev=ttyS0\0" \
727 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
728 "usb_dr_mode=host\0" \
729 "ramdiskaddr=2000000\0" \
730 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
732 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
736 #define CONFIG_HDBOOT \
737 "setenv bootargs root=/dev/$bdev rw " \
738 "console=$consoledev,$baudrate $othbootargs;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr - $fdtaddr"
743 #define CONFIG_NFSBOOTCOMMAND \
744 "setenv bootargs root=/dev/nfs rw " \
745 "nfsroot=$serverip:$rootpath " \
746 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
747 "console=$consoledev,$baudrate $othbootargs;" \
748 "tftp $loadaddr $bootfile;" \
749 "tftp $fdtaddr $fdtfile;" \
750 "bootm $loadaddr - $fdtaddr"
752 #define CONFIG_RAMBOOTCOMMAND \
753 "setenv bootargs root=/dev/ram rw " \
754 "console=$consoledev,$baudrate $othbootargs;" \
755 "tftp $ramdiskaddr $ramdiskfile;" \
756 "tftp $loadaddr $bootfile;" \
757 "tftp $fdtaddr $fdtfile;" \
758 "bootm $loadaddr $ramdiskaddr $fdtaddr"
760 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
762 #ifdef CONFIG_SECURE_BOOT
763 #include <asm/fsl_secure_boot.h>
766 #endif /* __CONFIG_H */