1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
20 /* Set 1M boot space */
21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
23 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 /* High Level Configuration Options */
29 #ifndef CONFIG_RESET_VECTOR_ADDRESS
30 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
33 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
34 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
36 #define CONFIG_SYS_SRIO
37 #define CONFIG_SRIO1 /* SRIO port 1 */
38 #define CONFIG_SRIO2 /* SRIO port 2 */
39 #define CONFIG_SRIO_PCIE_BOOT_MASTER
40 #define CONFIG_SYS_DPAA_RMAN /* RMan */
43 #include <linux/stringify.h>
47 * These can be toggled for performance analysis, otherwise use default.
49 #define CONFIG_SYS_CACHE_STASHING
50 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
52 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
55 * Config the L3 Cache as L3 SRAM
57 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
58 #ifdef CONFIG_PHYS_64BIT
59 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
60 CONFIG_RAMBOOT_TEXT_BASE)
62 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
64 #define CONFIG_SYS_L3_SIZE (1024 << 10)
65 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
67 #ifdef CONFIG_PHYS_64BIT
68 #define CONFIG_SYS_DCSRBAR 0xf0000000
69 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
73 #define CONFIG_SYS_I2C_EEPROM_NXID
74 #define CONFIG_SYS_EEPROM_BUS_NUM 0
79 #define CONFIG_VERY_BIG_RAM
80 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
83 #define SPD_EEPROM_ADDRESS 0x52
84 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
87 * Local Bus Definitions
90 /* Set the local bus clock 1/8 of platform clock */
91 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
94 * This board doesn't have a promjet connector.
95 * However, it uses commone corenet board LAW and TLB.
96 * It is necessary to use the same start address with proper offset.
98 #define CONFIG_SYS_FLASH_BASE 0xe0000000
99 #ifdef CONFIG_PHYS_64BIT
100 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
102 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
105 #define CONFIG_SYS_FLASH_BR_PRELIM \
106 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
108 #define CONFIG_SYS_FLASH_OR_PRELIM \
109 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
110 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
112 #define CONFIG_FSL_CPLD
113 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
114 #ifdef CONFIG_PHYS_64BIT
115 #define CPLD_BASE_PHYS 0xfffdf0000ull
117 #define CPLD_BASE_PHYS CPLD_BASE
120 #define PIXIS_LBMAP_SWITCH 7
121 #define PIXIS_LBMAP_MASK 0xf0
122 #define PIXIS_LBMAP_SHIFT 4
123 #define PIXIS_LBMAP_ALTBANK 0x40
125 #define CONFIG_SYS_FLASH_QUIET_TEST
126 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
128 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
129 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
130 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
133 #ifdef CONFIG_NAND_FSL_ELBC
134 #define CONFIG_SYS_NAND_BASE 0xffa00000
135 #ifdef CONFIG_PHYS_64BIT
136 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
138 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
141 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
142 #define CONFIG_SYS_MAX_NAND_DEVICE 1
144 /* NAND flash config */
145 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
146 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
147 | BR_PS_8 /* Port Size = 8 bit */ \
148 | BR_MS_FCM /* MSEL = FCM */ \
150 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
151 | OR_FCM_PGS /* Large Page*/ \
158 #endif /* CONFIG_NAND_FSL_ELBC */
160 #define CONFIG_SYS_FLASH_EMPTY_INFO
161 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
163 #define CONFIG_HWCONFIG
165 /* define to use L1 as initial stack */
166 #define CONFIG_L1_INIT_RAM
167 #define CONFIG_SYS_INIT_RAM_LOCK
168 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
169 #ifdef CONFIG_PHYS_64BIT
170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
171 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
172 /* The assembler doesn't like typecast */
173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
174 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
175 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
177 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
181 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
183 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
185 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
187 /* Serial Port - controlled on board with jumper J8
191 #define CONFIG_SYS_NS16550_SERIAL
192 #define CONFIG_SYS_NS16550_REG_SIZE 1
193 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
195 #define CONFIG_SYS_BAUDRATE_TABLE \
196 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
200 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
201 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
209 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
210 #ifdef CONFIG_PHYS_64BIT
211 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
213 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
215 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
217 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
218 #ifdef CONFIG_PHYS_64BIT
219 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
221 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
223 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
226 * for slave u-boot IMAGE instored in master memory space,
227 * PHYS must be aligned based on the SIZE
229 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
230 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
231 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
232 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
234 * for slave UCODE and ENV instored in master memory space,
235 * PHYS must be aligned based on the SIZE
237 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
238 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
239 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
241 /* slave core release by master*/
242 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
243 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
246 * SRIO_PCIE_BOOT - SLAVE
248 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
249 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
250 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
251 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
255 * eSPI - Enhanced SPI
260 * Memory space is mapped 1-1, but I/O space must start from 0.
263 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
264 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
265 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
266 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
267 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
269 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
270 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
271 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
272 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
273 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
275 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
276 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
277 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
278 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
279 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
282 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
283 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
284 #ifdef CONFIG_PHYS_64BIT
285 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
287 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
289 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
290 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
291 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
292 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
293 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
294 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
295 CONFIG_SYS_BMAN_CENA_SIZE)
296 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
297 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
298 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
299 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
300 #ifdef CONFIG_PHYS_64BIT
301 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
303 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
305 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
306 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
307 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
308 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
309 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
310 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
311 CONFIG_SYS_QMAN_CENA_SIZE)
312 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
313 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
315 #define CONFIG_SYS_DPAA_FMAN
316 #define CONFIG_SYS_DPAA_PME
317 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
319 #ifdef CONFIG_FMAN_ENET
320 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
321 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
322 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
323 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
324 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
326 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
327 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
328 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
329 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
331 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
333 #define CONFIG_SYS_TBIPA_VALUE 8
339 #define CONFIG_LOADS_ECHO /* echo on for serial download */
340 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
343 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
344 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
348 * Miscellaneous configurable options
352 * For booting Linux, the board info and command line data
353 * have to be in the first 64 MB of memory, since this is
354 * the maximum mapped by the Linux kernel during initialization.
356 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
357 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
360 * Environment Configuration
362 #define CONFIG_ROOTPATH "/opt/nfsroot"
363 #define CONFIG_UBOOTPATH u-boot.bin
365 #define __USB_PHY_TYPE utmi
367 #define CONFIG_EXTRA_ENV_SETTINGS \
368 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
369 "bank_intlv=cs0_cs1\0" \
371 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
372 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
373 "tftpflash=tftpboot $loadaddr $uboot && " \
374 "protect off $ubootaddr +$filesize && " \
375 "erase $ubootaddr +$filesize && " \
376 "cp.b $loadaddr $ubootaddr $filesize && " \
377 "protect on $ubootaddr +$filesize && " \
378 "cmp.b $loadaddr $ubootaddr $filesize\0" \
379 "consoledev=ttyS0\0" \
380 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
381 "usb_dr_mode=host\0" \
382 "ramdiskaddr=2000000\0" \
383 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
384 "fdtaddr=1e00000\0" \
385 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
388 #include <asm/fsl_secure_boot.h>
390 #endif /* __CONFIG_H */