1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
20 /* Set 1M boot space */
21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
23 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 /* High Level Configuration Options */
28 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
30 #ifndef CONFIG_RESET_VECTOR_ADDRESS
31 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
35 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
36 #define CONFIG_PCIE1 /* PCIE controller 1 */
37 #define CONFIG_PCIE2 /* PCIE controller 2 */
38 #define CONFIG_PCIE3 /* PCIE controller 3 */
39 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
41 #define CONFIG_SYS_SRIO
42 #define CONFIG_SRIO1 /* SRIO port 1 */
43 #define CONFIG_SRIO2 /* SRIO port 2 */
44 #define CONFIG_SRIO_PCIE_BOOT_MASTER
45 #define CONFIG_SYS_DPAA_RMAN /* RMan */
47 #if defined(CONFIG_SPIFLASH)
48 #elif defined(CONFIG_SDCARD)
49 #define CONFIG_FSL_FIXED_MMC_LOCATION
53 unsigned long get_board_sys_clk(unsigned long dummy);
54 #include <linux/stringify.h>
56 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
59 * These can be toggled for performance analysis, otherwise use default.
61 #define CONFIG_SYS_CACHE_STASHING
62 #define CONFIG_BACKSIDE_L2_CACHE
63 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
64 #define CONFIG_BTB /* toggle branch predition */
66 #define CONFIG_ENABLE_36BIT_PHYS
68 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
71 * Config the L3 Cache as L3 SRAM
73 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
74 #ifdef CONFIG_PHYS_64BIT
75 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
76 CONFIG_RAMBOOT_TEXT_BASE)
78 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
80 #define CONFIG_SYS_L3_SIZE (1024 << 10)
81 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
83 #ifdef CONFIG_PHYS_64BIT
84 #define CONFIG_SYS_DCSRBAR 0xf0000000
85 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
89 #define CONFIG_SYS_I2C_EEPROM_NXID
90 #define CONFIG_SYS_EEPROM_BUS_NUM 0
95 #define CONFIG_VERY_BIG_RAM
96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
100 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
102 #define CONFIG_SYS_SPD_BUS_NUM 0
103 #define SPD_EEPROM_ADDRESS 0x52
104 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
107 * Local Bus Definitions
110 /* Set the local bus clock 1/8 of platform clock */
111 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
114 * This board doesn't have a promjet connector.
115 * However, it uses commone corenet board LAW and TLB.
116 * It is necessary to use the same start address with proper offset.
118 #define CONFIG_SYS_FLASH_BASE 0xe0000000
119 #ifdef CONFIG_PHYS_64BIT
120 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
122 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
125 #define CONFIG_SYS_FLASH_BR_PRELIM \
126 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
128 #define CONFIG_SYS_FLASH_OR_PRELIM \
129 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
130 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
132 #define CONFIG_FSL_CPLD
133 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
134 #ifdef CONFIG_PHYS_64BIT
135 #define CPLD_BASE_PHYS 0xfffdf0000ull
137 #define CPLD_BASE_PHYS CPLD_BASE
140 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
141 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
143 #define PIXIS_LBMAP_SWITCH 7
144 #define PIXIS_LBMAP_MASK 0xf0
145 #define PIXIS_LBMAP_SHIFT 4
146 #define PIXIS_LBMAP_ALTBANK 0x40
148 #define CONFIG_SYS_FLASH_QUIET_TEST
149 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
151 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
152 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
153 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
154 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
158 #if defined(CONFIG_RAMBOOT_PBL)
159 #define CONFIG_SYS_RAMBOOT
162 #define CONFIG_NAND_FSL_ELBC
164 #ifdef CONFIG_NAND_FSL_ELBC
165 #define CONFIG_SYS_NAND_BASE 0xffa00000
166 #ifdef CONFIG_PHYS_64BIT
167 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
169 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
172 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
173 #define CONFIG_SYS_MAX_NAND_DEVICE 1
174 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
176 /* NAND flash config */
177 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
178 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
179 | BR_PS_8 /* Port Size = 8 bit */ \
180 | BR_MS_FCM /* MSEL = FCM */ \
182 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
183 | OR_FCM_PGS /* Large Page*/ \
191 #ifdef CONFIG_MTD_RAW_NAND
192 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
193 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
194 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
195 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
197 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
198 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
199 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
200 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
203 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
204 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
205 #endif /* CONFIG_NAND_FSL_ELBC */
207 #define CONFIG_SYS_FLASH_EMPTY_INFO
208 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
209 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
211 #define CONFIG_HWCONFIG
213 /* define to use L1 as initial stack */
214 #define CONFIG_L1_INIT_RAM
215 #define CONFIG_SYS_INIT_RAM_LOCK
216 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
217 #ifdef CONFIG_PHYS_64BIT
218 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
219 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
220 /* The assembler doesn't like typecast */
221 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
222 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
223 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
227 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
229 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
231 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
232 GENERATED_GBL_DATA_SIZE)
233 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
235 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
237 /* Serial Port - controlled on board with jumper J8
241 #define CONFIG_SYS_NS16550_SERIAL
242 #define CONFIG_SYS_NS16550_REG_SIZE 1
243 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
245 #define CONFIG_SYS_BAUDRATE_TABLE \
246 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
248 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
249 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
250 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
251 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
259 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
260 #ifdef CONFIG_PHYS_64BIT
261 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
263 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
265 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
267 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
268 #ifdef CONFIG_PHYS_64BIT
269 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
271 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
273 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
276 * for slave u-boot IMAGE instored in master memory space,
277 * PHYS must be aligned based on the SIZE
279 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
280 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
281 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
282 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
284 * for slave UCODE and ENV instored in master memory space,
285 * PHYS must be aligned based on the SIZE
287 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
288 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
289 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
291 /* slave core release by master*/
292 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
293 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
296 * SRIO_PCIE_BOOT - SLAVE
298 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
299 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
300 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
301 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
305 * eSPI - Enhanced SPI
310 * Memory space is mapped 1-1, but I/O space must start from 0.
313 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
314 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
315 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
316 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
317 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
319 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
320 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
321 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
322 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
323 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
325 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
326 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
327 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
328 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
329 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
332 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
333 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
334 #ifdef CONFIG_PHYS_64BIT
335 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
337 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
339 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
340 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
341 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
342 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
343 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
344 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
345 CONFIG_SYS_BMAN_CENA_SIZE)
346 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
347 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
348 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
349 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
350 #ifdef CONFIG_PHYS_64BIT
351 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
353 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
355 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
356 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
357 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
358 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
359 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
360 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
361 CONFIG_SYS_QMAN_CENA_SIZE)
362 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
363 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
365 #define CONFIG_SYS_DPAA_FMAN
366 #define CONFIG_SYS_DPAA_PME
367 /* Default address of microcode for the Linux Fman driver */
368 #if defined(CONFIG_SPIFLASH)
370 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
371 * env, so we got 0x110000.
373 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
374 #elif defined(CONFIG_SDCARD)
376 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
377 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
378 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
380 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
381 #elif defined(CONFIG_MTD_RAW_NAND)
382 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
383 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
385 * Slave has no ucode locally, it can fetch this from remote. When implementing
386 * in two corenet boards, slave's ucode could be stored in master's memory
387 * space, the address can be mapped from slave TLB->slave LAW->
388 * slave SRIO or PCIE outbound window->master inbound window->
389 * master LAW->the ucode address in master's memory space.
391 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
393 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
395 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
396 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
399 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
400 #endif /* CONFIG_PCI */
403 #define CONFIG_FSL_SATA_V2
405 #ifdef CONFIG_FSL_SATA_V2
406 #define CONFIG_SYS_SATA_MAX_DEVICE 2
408 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
409 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
411 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
412 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
417 #ifdef CONFIG_FMAN_ENET
418 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
419 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
420 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
421 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
422 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
424 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
425 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
426 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
427 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
429 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
431 #define CONFIG_SYS_TBIPA_VALUE 8
432 #define CONFIG_ETHPRIME "FM1@DTSEC1"
438 #define CONFIG_LOADS_ECHO /* echo on for serial download */
439 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
444 #define CONFIG_HAS_FSL_DR_USB
445 #define CONFIG_HAS_FSL_MPH_USB
447 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
448 #define CONFIG_USB_EHCI_FSL
449 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
453 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
454 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
458 * Miscellaneous configurable options
462 * For booting Linux, the board info and command line data
463 * have to be in the first 64 MB of memory, since this is
464 * the maximum mapped by the Linux kernel during initialization.
466 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
467 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
469 #ifdef CONFIG_CMD_KGDB
470 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
474 * Environment Configuration
476 #define CONFIG_ROOTPATH "/opt/nfsroot"
477 #define CONFIG_BOOTFILE "uImage"
478 #define CONFIG_UBOOTPATH u-boot.bin
480 #define __USB_PHY_TYPE utmi
482 #define CONFIG_EXTRA_ENV_SETTINGS \
483 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
484 "bank_intlv=cs0_cs1\0" \
486 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
487 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
488 "tftpflash=tftpboot $loadaddr $uboot && " \
489 "protect off $ubootaddr +$filesize && " \
490 "erase $ubootaddr +$filesize && " \
491 "cp.b $loadaddr $ubootaddr $filesize && " \
492 "protect on $ubootaddr +$filesize && " \
493 "cmp.b $loadaddr $ubootaddr $filesize\0" \
494 "consoledev=ttyS0\0" \
495 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
496 "usb_dr_mode=host\0" \
497 "ramdiskaddr=2000000\0" \
498 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
499 "fdtaddr=1e00000\0" \
500 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
504 "setenv bootargs root=/dev/$bdev rw " \
505 "console=$consoledev,$baudrate $othbootargs;" \
506 "tftp $loadaddr $bootfile;" \
507 "tftp $fdtaddr $fdtfile;" \
508 "bootm $loadaddr - $fdtaddr"
510 #define NFSBOOTCOMMAND \
511 "setenv bootargs root=/dev/nfs rw " \
512 "nfsroot=$serverip:$rootpath " \
513 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
514 "console=$consoledev,$baudrate $othbootargs;" \
515 "tftp $loadaddr $bootfile;" \
516 "tftp $fdtaddr $fdtfile;" \
517 "bootm $loadaddr - $fdtaddr"
519 #define RAMBOOTCOMMAND \
520 "setenv bootargs root=/dev/ram rw " \
521 "console=$consoledev,$baudrate $othbootargs;" \
522 "tftp $ramdiskaddr $ramdiskfile;" \
523 "tftp $loadaddr $bootfile;" \
524 "tftp $fdtaddr $fdtfile;" \
525 "bootm $loadaddr $ramdiskaddr $fdtaddr"
527 #define CONFIG_BOOTCOMMAND HDBOOT
529 #include <asm/fsl_secure_boot.h>
531 #endif /* __CONFIG_H */