2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P2041 RDB board configuration file
30 #define CONFIG_P2041RDB
31 #define CONFIG_PHYS_64BIT
32 #define CONFIG_PPC_P2041
34 #ifdef CONFIG_RAMBOOT_PBL
35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
39 /* High Level Configuration Options */
41 #define CONFIG_E500 /* BOOKE e500 family */
42 #define CONFIG_E500MC /* BOOKE e500mc family */
43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
45 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
46 #define CONFIG_MP /* support multiple processors */
48 #ifndef CONFIG_SYS_TEXT_BASE
49 #define CONFIG_SYS_TEXT_BASE 0xeff80000
52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
57 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
58 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
59 #define CONFIG_PCI /* Enable PCI/PCIE */
60 #define CONFIG_PCIE1 /* PCIE controler 1 */
61 #define CONFIG_PCIE2 /* PCIE controler 2 */
62 #define CONFIG_PCIE3 /* PCIE controler 3 */
63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
66 #define CONFIG_SYS_SRIO
67 #define CONFIG_SRIO1 /* SRIO port 1 */
68 #define CONFIG_SRIO2 /* SRIO port 2 */
69 #define CONFIG_SYS_DPAA_RMAN /* RMan */
71 #define CONFIG_FSL_LAW /* Use common FSL init code */
73 #define CONFIG_ENV_OVERWRITE
75 #ifdef CONFIG_SYS_NO_FLASH
76 #define CONFIG_ENV_IS_NOWHERE
78 #define CONFIG_FLASH_CFI_DRIVER
79 #define CONFIG_SYS_FLASH_CFI
82 #if defined(CONFIG_SPIFLASH)
83 #define CONFIG_SYS_EXTRA_ENV_RELOC
84 #define CONFIG_ENV_IS_IN_SPI_FLASH
85 #define CONFIG_ENV_SPI_BUS 0
86 #define CONFIG_ENV_SPI_CS 0
87 #define CONFIG_ENV_SPI_MAX_HZ 10000000
88 #define CONFIG_ENV_SPI_MODE 0
89 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
90 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
91 #define CONFIG_ENV_SECT_SIZE 0x10000
92 #elif defined(CONFIG_SDCARD)
93 #define CONFIG_SYS_EXTRA_ENV_RELOC
94 #define CONFIG_ENV_IS_IN_MMC
95 #define CONFIG_FSL_FIXED_MMC_LOCATION
96 #define CONFIG_SYS_MMC_ENV_DEV 0
97 #define CONFIG_ENV_SIZE 0x2000
98 #define CONFIG_ENV_OFFSET (512 * 1097)
100 #define CONFIG_ENV_IS_IN_FLASH
101 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
102 - CONFIG_ENV_SECT_SIZE)
103 #define CONFIG_ENV_SIZE 0x2000
104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
108 unsigned long get_board_sys_clk(unsigned long dummy);
110 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
113 * These can be toggled for performance analysis, otherwise use default.
115 #define CONFIG_SYS_CACHE_STASHING
116 #define CONFIG_BACKSIDE_L2_CACHE
117 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
118 #define CONFIG_BTB /* toggle branch predition */
120 #define CONFIG_ENABLE_36BIT_PHYS
122 #ifdef CONFIG_PHYS_64BIT
123 #define CONFIG_ADDR_MAP
124 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
127 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
128 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
129 #define CONFIG_SYS_MEMTEST_END 0x00400000
130 #define CONFIG_SYS_ALT_MEMTEST
131 #define CONFIG_PANIC_HANG /* do not reset board on panic */
134 * Config the L3 Cache as L3 SRAM
136 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
137 #ifdef CONFIG_PHYS_64BIT
138 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
139 CONFIG_RAMBOOT_TEXT_BASE)
141 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
143 #define CONFIG_SYS_L3_SIZE (1024 << 10)
144 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
146 #ifdef CONFIG_PHYS_64BIT
147 #define CONFIG_SYS_DCSRBAR 0xf0000000
148 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
152 #define CONFIG_ID_EEPROM
153 #define CONFIG_SYS_I2C_EEPROM_NXID
154 #define CONFIG_SYS_EEPROM_BUS_NUM 0
155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
161 #define CONFIG_VERY_BIG_RAM
162 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
163 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
165 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
166 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
168 #define CONFIG_DDR_SPD
169 #define CONFIG_FSL_DDR3
171 #define CONFIG_SYS_SPD_BUS_NUM 0
172 #define SPD_EEPROM_ADDRESS 0x52
173 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
176 * Local Bus Definitions
179 /* Set the local bus clock 1/8 of platform clock */
180 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
182 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */
183 #ifdef CONFIG_PHYS_64BIT
184 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
186 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
189 #define CONFIG_SYS_FLASH_BR_PRELIM \
190 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
191 #define CONFIG_SYS_FLASH_OR_PRELIM \
192 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
193 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
195 #define CONFIG_FSL_CPLD
196 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
197 #ifdef CONFIG_PHYS_64BIT
198 #define CPLD_BASE_PHYS 0xfffdf0000ull
200 #define CPLD_BASE_PHYS CPLD_BASE
203 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
204 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
206 #define PIXIS_LBMAP_SWITCH 7
207 #define PIXIS_LBMAP_MASK 0xf0
208 #define PIXIS_LBMAP_SHIFT 4
209 #define PIXIS_LBMAP_ALTBANK 0x40
211 #define CONFIG_SYS_FLASH_QUIET_TEST
212 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
215 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
216 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
219 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
221 #if defined(CONFIG_RAMBOOT_PBL)
222 #define CONFIG_SYS_RAMBOOT
225 #define CONFIG_NAND_FSL_ELBC
227 #ifdef CONFIG_NAND_FSL_ELBC
228 #define CONFIG_SYS_NAND_BASE 0xffa00000
229 #ifdef CONFIG_PHYS_64BIT
230 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
232 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
235 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
236 #define CONFIG_SYS_MAX_NAND_DEVICE 1
237 #define CONFIG_MTD_NAND_VERIFY_WRITE
238 #define CONFIG_CMD_NAND
239 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
241 /* NAND flash config */
242 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
243 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
244 | BR_PS_8 /* Port Size = 8 bit */ \
245 | BR_MS_FCM /* MSEL = FCM */ \
247 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
248 | OR_FCM_PGS /* Large Page*/ \
257 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
258 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
259 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
260 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
262 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
263 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
264 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
265 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
268 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
269 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
270 #endif /* CONFIG_NAND_FSL_ELBC */
272 #define CONFIG_SYS_FLASH_EMPTY_INFO
273 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
274 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
276 #define CONFIG_BOARD_EARLY_INIT_F
277 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
278 #define CONFIG_MISC_INIT_R
280 #define CONFIG_HWCONFIG
282 /* define to use L1 as initial stack */
283 #define CONFIG_L1_INIT_RAM
284 #define CONFIG_SYS_INIT_RAM_LOCK
285 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
286 #ifdef CONFIG_PHYS_64BIT
287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
289 /* The assembler doesn't like typecast */
290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
291 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
292 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
298 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
300 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
301 GENERATED_GBL_DATA_SIZE)
302 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
304 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
305 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
307 /* Serial Port - controlled on board with jumper J8
311 #define CONFIG_CONS_INDEX 1
312 #define CONFIG_SYS_NS16550
313 #define CONFIG_SYS_NS16550_SERIAL
314 #define CONFIG_SYS_NS16550_REG_SIZE 1
315 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
317 #define CONFIG_SYS_BAUDRATE_TABLE \
318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
320 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
321 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
322 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
323 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
325 /* Use the HUSH parser */
326 #define CONFIG_SYS_HUSH_PARSER
327 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
329 /* pass open firmware flat tree */
330 #define CONFIG_OF_LIBFDT
331 #define CONFIG_OF_BOARD_SETUP
332 #define CONFIG_OF_STDOUT_VIA_ALIAS
334 /* new uImage format support */
336 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
339 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
340 #define CONFIG_HARD_I2C /* I2C with hardware support */
341 #define CONFIG_I2C_MULTI_BUS
342 #define CONFIG_I2C_CMD_TREE
343 #define CONFIG_SYS_I2C_SPEED 400000
344 #define CONFIG_SYS_I2C_SLAVE 0x7F
345 #define CONFIG_SYS_I2C_OFFSET 0x118000
346 #define CONFIG_SYS_I2C2_OFFSET 0x118100
351 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
352 #ifdef CONFIG_PHYS_64BIT
353 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
355 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
357 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
359 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
360 #ifdef CONFIG_PHYS_64BIT
361 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
363 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
365 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
368 * eSPI - Enhanced SPI
370 #define CONFIG_FSL_ESPI
371 #define CONFIG_SPI_FLASH
372 #define CONFIG_SPI_FLASH_SPANSION
373 #define CONFIG_CMD_SF
374 #define CONFIG_SF_DEFAULT_SPEED 10000000
375 #define CONFIG_SF_DEFAULT_MODE 0
379 * Memory space is mapped 1-1, but I/O space must start from 0.
382 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
383 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
384 #ifdef CONFIG_PHYS_64BIT
385 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
386 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
388 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
389 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
391 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
392 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
393 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
394 #ifdef CONFIG_PHYS_64BIT
395 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
397 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
399 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
401 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
402 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
405 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
407 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
408 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
410 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
411 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
412 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
413 #ifdef CONFIG_PHYS_64BIT
414 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
416 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
418 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
420 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
421 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
422 #ifdef CONFIG_PHYS_64BIT
423 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
424 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
426 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
427 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
429 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
430 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
431 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
432 #ifdef CONFIG_PHYS_64BIT
433 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
435 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
437 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
440 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
441 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
442 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
443 #ifdef CONFIG_PHYS_64BIT
444 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
446 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
448 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
449 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
450 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
451 #ifdef CONFIG_PHYS_64BIT
452 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
454 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
456 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
458 #define CONFIG_SYS_DPAA_FMAN
459 #define CONFIG_SYS_DPAA_PME
460 /* Default address of microcode for the Linux Fman driver */
461 #if defined(CONFIG_SPIFLASH)
463 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
464 * env, so we got 0x110000.
466 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
467 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
468 #elif defined(CONFIG_SDCARD)
470 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
471 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
472 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
474 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
475 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
476 #elif defined(CONFIG_NAND)
477 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
478 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
480 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
481 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
483 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
484 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
486 #ifdef CONFIG_SYS_DPAA_FMAN
487 #define CONFIG_FMAN_ENET
488 #define CONFIG_PHYLIB_10G
489 #define CONFIG_PHY_VITESSE
490 #define CONFIG_PHY_TERANETICS
494 #define CONFIG_PCI_PNP /* do pci plug-and-play */
497 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
498 #define CONFIG_DOS_PARTITION
499 #endif /* CONFIG_PCI */
502 #define CONFIG_FSL_SATA
503 #ifdef CONFIG_FSL_SATA
504 #define CONFIG_LIBATA
506 #define CONFIG_SYS_SATA_MAX_DEVICE 2
508 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
509 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
511 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
512 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
515 #define CONFIG_CMD_SATA
516 #define CONFIG_DOS_PARTITION
517 #define CONFIG_CMD_EXT2
520 #ifdef CONFIG_FMAN_ENET
521 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
522 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
523 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
524 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
525 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
527 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
528 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
529 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
530 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
532 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
534 #define CONFIG_SYS_TBIPA_VALUE 8
535 #define CONFIG_MII /* MII PHY management */
536 #define CONFIG_ETHPRIME "FM1@DTSEC1"
537 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
543 #define CONFIG_LOADS_ECHO /* echo on for serial download */
544 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
547 * Command line configuration.
549 #include <config_cmd_default.h>
551 #define CONFIG_CMD_DHCP
552 #define CONFIG_CMD_ELF
553 #define CONFIG_CMD_ERRATA
554 #define CONFIG_CMD_GREPENV
555 #define CONFIG_CMD_IRQ
556 #define CONFIG_CMD_I2C
557 #define CONFIG_CMD_MII
558 #define CONFIG_CMD_PING
559 #define CONFIG_CMD_SETEXPR
562 #define CONFIG_CMD_PCI
563 #define CONFIG_CMD_NET
569 #define CONFIG_CMD_USB
570 #define CONFIG_USB_STORAGE
571 #define CONFIG_USB_EHCI
572 #define CONFIG_USB_EHCI_FSL
573 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
574 #define CONFIG_CMD_EXT2
579 #define CONFIG_FSL_ESDHC
580 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
581 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
582 #define CONFIG_CMD_MMC
583 #define CONFIG_GENERIC_MMC
584 #define CONFIG_CMD_EXT2
585 #define CONFIG_CMD_FAT
586 #define CONFIG_DOS_PARTITION
590 * Miscellaneous configurable options
592 #define CONFIG_SYS_LONGHELP /* undef to save memory */
593 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
594 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
595 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
596 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
597 #ifdef CONFIG_CMD_KGDB
598 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
600 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
602 /* Print Buffer Size */
603 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
604 sizeof(CONFIG_SYS_PROMPT)+16)
605 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
606 /* Boot Argument Buffer Size */
607 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
608 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */
611 * For booting Linux, the board info and command line data
612 * have to be in the first 64 MB of memory, since this is
613 * the maximum mapped by the Linux kernel during initialization.
615 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
616 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
618 #ifdef CONFIG_CMD_KGDB
619 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
620 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
624 * Environment Configuration
626 #define CONFIG_ROOTPATH "/opt/nfsroot"
627 #define CONFIG_BOOTFILE "uImage"
628 #define CONFIG_UBOOTPATH u-boot.bin
630 /* default location for tftp and bootm */
631 #define CONFIG_LOADADDR 1000000
633 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
635 #define CONFIG_BAUDRATE 115200
637 #define __USB_PHY_TYPE utmi
639 #define CONFIG_EXTRA_ENV_SETTINGS \
640 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
641 "bank_intlv=cs0_cs1\0" \
643 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
644 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
645 "tftpflash=tftpboot $loadaddr $uboot && " \
646 "protect off $ubootaddr +$filesize && " \
647 "erase $ubootaddr +$filesize && " \
648 "cp.b $loadaddr $ubootaddr $filesize && " \
649 "protect on $ubootaddr +$filesize && " \
650 "cmp.b $loadaddr $ubootaddr $filesize\0" \
651 "consoledev=ttyS0\0" \
652 "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \
653 "usb_dr_mode=host\0" \
654 "ramdiskaddr=2000000\0" \
655 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
657 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
661 #define CONFIG_HDBOOT \
662 "setenv bootargs root=/dev/$bdev rw " \
663 "console=$consoledev,$baudrate $othbootargs;" \
664 "tftp $loadaddr $bootfile;" \
665 "tftp $fdtaddr $fdtfile;" \
666 "bootm $loadaddr - $fdtaddr"
668 #define CONFIG_NFSBOOTCOMMAND \
669 "setenv bootargs root=/dev/nfs rw " \
670 "nfsroot=$serverip:$rootpath " \
671 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
672 "console=$consoledev,$baudrate $othbootargs;" \
673 "tftp $loadaddr $bootfile;" \
674 "tftp $fdtaddr $fdtfile;" \
675 "bootm $loadaddr - $fdtaddr"
677 #define CONFIG_RAMBOOTCOMMAND \
678 "setenv bootargs root=/dev/ram rw " \
679 "console=$consoledev,$baudrate $othbootargs;" \
680 "tftp $ramdiskaddr $ramdiskfile;" \
681 "tftp $loadaddr $bootfile;" \
682 "tftp $fdtaddr $fdtfile;" \
683 "bootm $loadaddr $ramdiskaddr $fdtaddr"
685 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
687 #ifdef CONFIG_SECURE_BOOT
688 #include <asm/fsl_secure_boot.h>
691 #endif /* __CONFIG_H */