include/configs/P2041RDB.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * P2041 RDB board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_P2041RDB
  31 #define CONFIG_PHYS_64BIT
  32 #define CONFIG_PPC_P2041
  33
  34 #ifdef CONFIG_RAMBOOT_PBL
  35 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  37 #endif
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE
  41 #define CONFIG_E500                     /* BOOKE e500 family */
  42 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  43 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  44 #define CONFIG_MPC85xx                  /* MPC85xx/PQ3 platform */
  45 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  46 #define CONFIG_MP                       /* support multiple processors */
  47
  48 #ifndef CONFIG_SYS_TEXT_BASE
  49 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  50 #endif
  51
  52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  53 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  54 #endif
  55
  56 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  57 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  58 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  59 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  60 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  61 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  62 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  63 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  64 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  65
  66 #define CONFIG_SYS_SRIO
  67 #define CONFIG_SRIO1                    /* SRIO port 1 */
  68 #define CONFIG_SRIO2                    /* SRIO port 2 */
  69 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  70
  71 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  72
  73 #define CONFIG_ENV_OVERWRITE
  74
  75 #ifdef CONFIG_SYS_NO_FLASH
  76 #ifndef CONFIG_RAMBOOT_PBL
  77 #define CONFIG_ENV_IS_NOWHERE
  78 #endif
  79 #else
  80 #define CONFIG_FLASH_CFI_DRIVER
  81 #define CONFIG_SYS_FLASH_CFI
  82 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  83 #endif
  84
  85 #if defined(CONFIG_SPIFLASH)
  86         #define CONFIG_SYS_EXTRA_ENV_RELOC
  87         #define CONFIG_ENV_IS_IN_SPI_FLASH
  88         #define CONFIG_ENV_SPI_BUS              0
  89         #define CONFIG_ENV_SPI_CS               0
  90         #define CONFIG_ENV_SPI_MAX_HZ           10000000
  91         #define CONFIG_ENV_SPI_MODE             0
  92         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  93         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  94         #define CONFIG_ENV_SECT_SIZE            0x10000
  95 #elif defined(CONFIG_SDCARD)
  96         #define CONFIG_SYS_EXTRA_ENV_RELOC
  97         #define CONFIG_ENV_IS_IN_MMC
  98         #define CONFIG_FSL_FIXED_MMC_LOCATION
  99         #define CONFIG_SYS_MMC_ENV_DEV          0
 100         #define CONFIG_ENV_SIZE                 0x2000
 101         #define CONFIG_ENV_OFFSET               (512 * 1097)
 102 #elif defined(CONFIG_NAND)
 103 #define CONFIG_SYS_EXTRA_ENV_RELOC
 104 #define CONFIG_ENV_IS_IN_NAND
 105 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 106 #define CONFIG_ENV_OFFSET               (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 107 #elif defined(CONFIG_ENV_IS_NOWHERE)
 108         #define CONFIG_ENV_SIZE         0x2000
 109 #else
 110         #define CONFIG_ENV_IS_IN_FLASH
 111         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 112                         - CONFIG_ENV_SECT_SIZE)
 113         #define CONFIG_ENV_SIZE         0x2000
 114         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 115 #endif
 116
 117 #ifndef __ASSEMBLY__
 118 unsigned long get_board_sys_clk(unsigned long dummy);
 119 #endif
 120 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
 121
 122 /*
 123  * These can be toggled for performance analysis, otherwise use default.
 124  */
 125 #define CONFIG_SYS_CACHE_STASHING
 126 #define CONFIG_BACKSIDE_L2_CACHE
 127 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 128 #define CONFIG_BTB                      /* toggle branch predition */
 129
 130 #define CONFIG_ENABLE_36BIT_PHYS
 131
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_ADDR_MAP
 134 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 135 #endif
 136
 137 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 138 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 139 #define CONFIG_SYS_MEMTEST_END          0x00400000
 140 #define CONFIG_SYS_ALT_MEMTEST
 141 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 142
 143 /*
 144  *  Config the L3 Cache as L3 SRAM
 145  */
 146 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 147 #ifdef CONFIG_PHYS_64BIT
 148 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 149                 CONFIG_RAMBOOT_TEXT_BASE)
 150 #else
 151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 152 #endif
 153 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 154 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 155
 156 #ifdef CONFIG_PHYS_64BIT
 157 #define CONFIG_SYS_DCSRBAR              0xf0000000
 158 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 159 #endif
 160
 161 /* EEPROM */
 162 #define CONFIG_ID_EEPROM
 163 #define CONFIG_SYS_I2C_EEPROM_NXID
 164 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 167
 168 /*
 169  * DDR Setup
 170  */
 171 #define CONFIG_VERY_BIG_RAM
 172 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 173 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 174
 175 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 176 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 177
 178 #define CONFIG_DDR_SPD
 179 #define CONFIG_FSL_DDR3
 180
 181 #define CONFIG_SYS_SPD_BUS_NUM  0
 182 #define SPD_EEPROM_ADDRESS      0x52
 183 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 184
 185 /*
 186  * Local Bus Definitions
 187  */
 188
 189 /* Set the local bus clock 1/8 of platform clock */
 190 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 191
 192 #define CONFIG_SYS_FLASH_BASE           0xe8000000      /* Start of PromJet */
 193 #ifdef CONFIG_PHYS_64BIT
 194 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 195 #else
 196 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 197 #endif
 198
 199 #define CONFIG_SYS_FLASH_BR_PRELIM \
 200                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 201 #define CONFIG_SYS_FLASH_OR_PRELIM \
 202                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 203                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 204
 205 #define CONFIG_FSL_CPLD
 206 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 207 #ifdef CONFIG_PHYS_64BIT
 208 #define CPLD_BASE_PHYS          0xfffdf0000ull
 209 #else
 210 #define CPLD_BASE_PHYS          CPLD_BASE
 211 #endif
 212
 213 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 214 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 215
 216 #define PIXIS_LBMAP_SWITCH      7
 217 #define PIXIS_LBMAP_MASK        0xf0
 218 #define PIXIS_LBMAP_SHIFT       4
 219 #define PIXIS_LBMAP_ALTBANK     0x40
 220
 221 #define CONFIG_SYS_FLASH_QUIET_TEST
 222 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 223
 224 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 225 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 226 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 227 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 228
 229 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 230
 231 #if defined(CONFIG_RAMBOOT_PBL)
 232 #define CONFIG_SYS_RAMBOOT
 233 #endif
 234
 235 #define CONFIG_NAND_FSL_ELBC
 236 /* Nand Flash */
 237 #ifdef CONFIG_NAND_FSL_ELBC
 238 #define CONFIG_SYS_NAND_BASE            0xffa00000
 239 #ifdef CONFIG_PHYS_64BIT
 240 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 241 #else
 242 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 243 #endif
 244
 245 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 246 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 247 #define CONFIG_MTD_NAND_VERIFY_WRITE
 248 #define CONFIG_CMD_NAND
 249 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 250
 251 /* NAND flash config */
 252 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 253                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 254                                | BR_PS_8               /* Port Size = 8 bit */ \
 255                                | BR_MS_FCM             /* MSEL = FCM */ \
 256                                | BR_V)                 /* valid */
 257 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 258                                | OR_FCM_PGS            /* Large Page*/ \
 259                                | OR_FCM_CSCT \
 260                                | OR_FCM_CST \
 261                                | OR_FCM_CHT \
 262                                | OR_FCM_SCY_1 \
 263                                | OR_FCM_TRLX \
 264                                | OR_FCM_EHTR)
 265
 266 #ifdef CONFIG_NAND
 267 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 268 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 269 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 270 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 271 #else
 272 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 273 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 274 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 275 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 276 #endif
 277 #else
 278 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 279 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 280 #endif /* CONFIG_NAND_FSL_ELBC */
 281
 282 #define CONFIG_SYS_FLASH_EMPTY_INFO
 283 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 284 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 285
 286 #define CONFIG_BOARD_EARLY_INIT_F
 287 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 288 #define CONFIG_MISC_INIT_R
 289
 290 #define CONFIG_HWCONFIG
 291
 292 /* define to use L1 as initial stack */
 293 #define CONFIG_L1_INIT_RAM
 294 #define CONFIG_SYS_INIT_RAM_LOCK
 295 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 296 #ifdef CONFIG_PHYS_64BIT
 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 299 /* The assembler doesn't like typecast */
 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 301         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 302           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 303 #else
 304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 307 #endif
 308 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 309
 310 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 311                                         GENERATED_GBL_DATA_SIZE)
 312 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 313
 314 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 315 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 316
 317 /* Serial Port - controlled on board with jumper J8
 318  * open - index 2
 319  * shorted - index 1
 320  */
 321 #define CONFIG_CONS_INDEX       1
 322 #define CONFIG_SYS_NS16550
 323 #define CONFIG_SYS_NS16550_SERIAL
 324 #define CONFIG_SYS_NS16550_REG_SIZE     1
 325 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 326
 327 #define CONFIG_SYS_BAUDRATE_TABLE       \
 328         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 329
 330 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 331 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 332 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 333 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 334
 335 /* Use the HUSH parser */
 336 #define CONFIG_SYS_HUSH_PARSER
 337
 338 /* pass open firmware flat tree */
 339 #define CONFIG_OF_LIBFDT
 340 #define CONFIG_OF_BOARD_SETUP
 341 #define CONFIG_OF_STDOUT_VIA_ALIAS
 342
 343 /* new uImage format support */
 344 #define CONFIG_FIT
 345 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 346
 347 /* I2C */
 348 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 349 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 350 #define CONFIG_I2C_MULTI_BUS
 351 #define CONFIG_I2C_CMD_TREE
 352 #define CONFIG_SYS_I2C_SPEED            400000
 353 #define CONFIG_SYS_I2C_SLAVE            0x7F
 354 #define CONFIG_SYS_I2C_OFFSET           0x118000
 355 #define CONFIG_SYS_I2C2_OFFSET          0x118100
 356
 357 /*
 358  * RapidIO
 359  */
 360 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 361 #ifdef CONFIG_PHYS_64BIT
 362 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 363 #else
 364 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 365 #endif
 366 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 367
 368 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 369 #ifdef CONFIG_PHYS_64BIT
 370 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 371 #else
 372 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 373 #endif
 374 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 375
 376 /*
 377  * eSPI - Enhanced SPI
 378  */
 379 #define CONFIG_FSL_ESPI
 380 #define CONFIG_SPI_FLASH
 381 #define CONFIG_SPI_FLASH_SPANSION
 382 #define CONFIG_CMD_SF
 383 #define CONFIG_SF_DEFAULT_SPEED         10000000
 384 #define CONFIG_SF_DEFAULT_MODE          0
 385
 386 /*
 387  * General PCI
 388  * Memory space is mapped 1-1, but I/O space must start from 0.
 389  */
 390
 391 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 392 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 393 #ifdef CONFIG_PHYS_64BIT
 394 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 395 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 396 #else
 397 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 398 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 399 #endif
 400 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 401 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 402 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 403 #ifdef CONFIG_PHYS_64BIT
 404 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 405 #else
 406 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 407 #endif
 408 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 409
 410 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 411 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 412 #ifdef CONFIG_PHYS_64BIT
 413 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 414 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 415 #else
 416 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 417 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 418 #endif
 419 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 420 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 421 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 422 #ifdef CONFIG_PHYS_64BIT
 423 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 424 #else
 425 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 426 #endif
 427 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 428
 429 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 430 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 431 #ifdef CONFIG_PHYS_64BIT
 432 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 433 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 434 #else
 435 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 436 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 437 #endif
 438 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 439 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 440 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 441 #ifdef CONFIG_PHYS_64BIT
 442 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 443 #else
 444 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 445 #endif
 446 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 447
 448 /* Qman/Bman */
 449 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 450 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 451 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 452 #ifdef CONFIG_PHYS_64BIT
 453 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 454 #else
 455 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 456 #endif
 457 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 458 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 459 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 460 #ifdef CONFIG_PHYS_64BIT
 461 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 462 #else
 463 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 464 #endif
 465 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 466
 467 #define CONFIG_SYS_DPAA_FMAN
 468 #define CONFIG_SYS_DPAA_PME
 469 /* Default address of microcode for the Linux Fman driver */
 470 #if defined(CONFIG_SPIFLASH)
 471 /*
 472  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 473  * env, so we got 0x110000.
 474  */
 475 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 476 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
 477 #elif defined(CONFIG_SDCARD)
 478 /*
 479  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 480  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 481  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 482  */
 483 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 484 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1130)
 485 #elif defined(CONFIG_NAND)
 486 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 487 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 488 #else
 489 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 490 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xEF000000
 491 #endif
 492 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 493 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 494
 495 #ifdef CONFIG_SYS_DPAA_FMAN
 496 #define CONFIG_FMAN_ENET
 497 #define CONFIG_PHYLIB_10G
 498 #define CONFIG_PHY_VITESSE
 499 #define CONFIG_PHY_TERANETICS
 500 #endif
 501
 502 #ifdef CONFIG_PCI
 503 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 504 #define CONFIG_E1000
 505
 506 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 507 #define CONFIG_DOS_PARTITION
 508 #endif  /* CONFIG_PCI */
 509
 510 /* SATA */
 511 #define CONFIG_FSL_SATA
 512 #ifdef CONFIG_FSL_SATA
 513 #define CONFIG_LIBATA
 514
 515 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 516 #define CONFIG_SATA1
 517 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 518 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 519 #define CONFIG_SATA2
 520 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 521 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 522
 523 #define CONFIG_LBA48
 524 #define CONFIG_CMD_SATA
 525 #define CONFIG_DOS_PARTITION
 526 #define CONFIG_CMD_EXT2
 527 #endif
 528
 529 #ifdef CONFIG_FMAN_ENET
 530 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 531 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 532 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 533 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 534 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 535
 536 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 537 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 538 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 539 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 540
 541 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 542
 543 #define CONFIG_SYS_TBIPA_VALUE  8
 544 #define CONFIG_MII              /* MII PHY management */
 545 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 546 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 547 #endif
 548
 549 /*
 550  * Environment
 551  */
 552 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 553 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 554
 555 /*
 556  * Command line configuration.
 557  */
 558 #include <config_cmd_default.h>
 559
 560 #define CONFIG_CMD_DHCP
 561 #define CONFIG_CMD_ELF
 562 #define CONFIG_CMD_ERRATA
 563 #define CONFIG_CMD_GREPENV
 564 #define CONFIG_CMD_IRQ
 565 #define CONFIG_CMD_I2C
 566 #define CONFIG_CMD_MII
 567 #define CONFIG_CMD_PING
 568 #define CONFIG_CMD_SETEXPR
 569
 570 #ifdef CONFIG_PCI
 571 #define CONFIG_CMD_PCI
 572 #define CONFIG_CMD_NET
 573 #endif
 574
 575 /*
 576 * USB
 577 */
 578 #define CONFIG_HAS_FSL_DR_USB
 579 #define CONFIG_HAS_FSL_MPH_USB
 580
 581 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 582 #define CONFIG_CMD_USB
 583 #define CONFIG_USB_STORAGE
 584 #define CONFIG_USB_EHCI
 585 #define CONFIG_USB_EHCI_FSL
 586 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 587 #endif
 588
 589 #define CONFIG_CMD_EXT2
 590
 591 #define CONFIG_MMC
 592
 593 #ifdef CONFIG_MMC
 594 #define CONFIG_FSL_ESDHC
 595 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 596 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 597 #define CONFIG_CMD_MMC
 598 #define CONFIG_GENERIC_MMC
 599 #define CONFIG_CMD_EXT2
 600 #define CONFIG_CMD_FAT
 601 #define CONFIG_DOS_PARTITION
 602 #endif
 603
 604 /*
 605  * Miscellaneous configurable options
 606  */
 607 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 608 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 609 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 610 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 611 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 612 #ifdef CONFIG_CMD_KGDB
 613 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 614 #else
 615 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 616 #endif
 617 /* Print Buffer Size */
 618 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 619                                 sizeof(CONFIG_SYS_PROMPT)+16)
 620 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 621 /* Boot Argument Buffer Size */
 622 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 623 #define CONFIG_SYS_HZ           1000            /* decrementer freq 1ms ticks */
 624
 625 /*
 626  * For booting Linux, the board info and command line data
 627  * have to be in the first 64 MB of memory, since this is
 628  * the maximum mapped by the Linux kernel during initialization.
 629  */
 630 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 631 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 632
 633 #ifdef CONFIG_CMD_KGDB
 634 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 635 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 636 #endif
 637
 638 /*
 639  * Environment Configuration
 640  */
 641 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 642 #define CONFIG_BOOTFILE         "uImage"
 643 #define CONFIG_UBOOTPATH        u-boot.bin
 644
 645 /* default location for tftp and bootm */
 646 #define CONFIG_LOADADDR         1000000
 647
 648 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 649
 650 #define CONFIG_BAUDRATE 115200
 651
 652 #define __USB_PHY_TYPE  utmi
 653
 654 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 655         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 656         "bank_intlv=cs0_cs1\0"                                  \
 657         "netdev=eth0\0"                                         \
 658         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                  \
 659         "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"          \
 660         "tftpflash=tftpboot $loadaddr $uboot && "               \
 661         "protect off $ubootaddr +$filesize && "                 \
 662         "erase $ubootaddr +$filesize && "                       \
 663         "cp.b $loadaddr $ubootaddr $filesize && "               \
 664         "protect on $ubootaddr +$filesize && "                  \
 665         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 666         "consoledev=ttyS0\0"                                    \
 667         "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0"             \
 668         "usb_dr_mode=host\0"                                    \
 669         "ramdiskaddr=2000000\0"                                 \
 670         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 671         "fdtaddr=c00000\0"                                      \
 672         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 673         "bdev=sda3\0"                                           \
 674         "c=ffe\0"
 675
 676 #define CONFIG_HDBOOT                                   \
 677         "setenv bootargs root=/dev/$bdev rw "           \
 678         "console=$consoledev,$baudrate $othbootargs;"   \
 679         "tftp $loadaddr $bootfile;"                     \
 680         "tftp $fdtaddr $fdtfile;"                       \
 681         "bootm $loadaddr - $fdtaddr"
 682
 683 #define CONFIG_NFSBOOTCOMMAND                   \
 684         "setenv bootargs root=/dev/nfs rw "     \
 685         "nfsroot=$serverip:$rootpath "          \
 686         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 687         "console=$consoledev,$baudrate $othbootargs;"   \
 688         "tftp $loadaddr $bootfile;"             \
 689         "tftp $fdtaddr $fdtfile;"               \
 690         "bootm $loadaddr - $fdtaddr"
 691
 692 #define CONFIG_RAMBOOTCOMMAND                           \
 693         "setenv bootargs root=/dev/ram rw "             \
 694         "console=$consoledev,$baudrate $othbootargs;"   \
 695         "tftp $ramdiskaddr $ramdiskfile;"               \
 696         "tftp $loadaddr $bootfile;"                     \
 697         "tftp $fdtaddr $fdtfile;"                       \
 698         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 699
 700 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 701
 702 #ifdef CONFIG_SECURE_BOOT
 703 #include <asm/fsl_secure_boot.h>
 704 #endif
 705
 706 #endif  /* __CONFIG_H */