include/configs/P2020DS.h

   1 /*
   2  * Copyright 2007-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * p2020ds board configuration file
   9  *
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include "../board/freescale/common/ics307_clk.h"
  15
  16 #ifdef CONFIG_36BIT
  17 #define CONFIG_PHYS_64BIT
  18 #endif
  19
  20 #ifdef CONFIG_SDCARD
  21 #define CONFIG_SYS_RAMBOOT
  22 #define CONFIG_SYS_EXTRA_ENV_RELOC
  23 #define CONFIG_SYS_TEXT_BASE            0xf8f40000
  24 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  25 #endif
  26
  27 #ifdef CONFIG_SPIFLASH
  28 #define CONFIG_SYS_RAMBOOT
  29 #define CONFIG_SYS_EXTRA_ENV_RELOC
  30 #define CONFIG_SYS_TEXT_BASE            0xf8f40000
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  32 #endif
  33
  34 /* High Level Configuration Options */
  35 #define CONFIG_BOOKE            1       /* BOOKE */
  36 #define CONFIG_E500             1       /* BOOKE e500 family */
  37 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  38 #define CONFIG_P2020            1
  39 #define CONFIG_P2020DS          1
  40 #define CONFIG_MP               1       /* support multiple processors */
  41
  42 #ifndef CONFIG_SYS_TEXT_BASE
  43 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  44 #endif
  45
  46 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  47 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  48 #endif
  49
  50 #define CONFIG_SYS_SRIO
  51 #define CONFIG_SRIO1                    /* SRIO port 1 */
  52 #define CONFIG_SRIO2                    /* SRIO port 2 */
  53
  54 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  55 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  56 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  57 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  58 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  59 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  60 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  61 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  62 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  63
  64 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  65 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  66
  67 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  68 #define CONFIG_ENV_OVERWRITE
  69
  70 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  71 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk() /* ddrclk for MPC85xx */
  72 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  73
  74 /*
  75  * These can be toggled for performance analysis, otherwise use default.
  76  */
  77 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  78 #define CONFIG_BTB                      /* toggle branch predition */
  79
  80 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
  81
  82 #define CONFIG_ENABLE_36BIT_PHYS        1
  83
  84 #ifdef CONFIG_PHYS_64BIT
  85 #define CONFIG_ADDR_MAP                 1
  86 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  87 #endif
  88
  89 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  90 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  91 #define CONFIG_SYS_MEMTEST_END          0x00400000
  92 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  93
  94 /*
  95  * Config the L2 Cache
  96  */
  97 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
  98 #ifdef CONFIG_PHYS_64BIT
  99 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 100 #else
 101 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 102 #endif
 103 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 104 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 105
 106 #define CONFIG_SYS_CCSRBAR              0xffe00000
 107 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 108
 109 /* DDR Setup */
 110 #define CONFIG_VERY_BIG_RAM
 111 #ifdef CONFIG_DDR2
 112 #define CONFIG_SYS_FSL_DDR2
 113 #else
 114 #define CONFIG_SYS_FSL_DDR3             1
 115 #endif
 116
 117 /* ECC will be enabled based on perf_mode environment variable */
 118 /* #define      CONFIG_DDR_ECC */
 119
 120 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 121 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 122
 123 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 124 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 125
 126 #define CONFIG_NUM_DDR_CONTROLLERS      1
 127 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 128 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 129
 130 /* I2C addresses of SPD EEPROMs */
 131 #define CONFIG_DDR_SPD
 132 #define CONFIG_SYS_SPD_BUS_NUM          0       /* SPD EEPROM located on I2C bus 0 */
 133 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 134
 135 /* These are used when DDR doesn't use SPD.  */
 136 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1GB */
 137
 138 /* Default settings for "stable" mode */
 139 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 140 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
 141 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 142 #define CONFIG_SYS_DDR_CS1_CONFIG       0x00000000
 143 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 144 #define CONFIG_SYS_DDR_TIMING_0         0x00330804
 145 #define CONFIG_SYS_DDR_TIMING_1         0x6f6b4846
 146 #define CONFIG_SYS_DDR_TIMING_2         0x0fa890d4
 147 #define CONFIG_SYS_DDR_MODE_1           0x00421422
 148 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 149 #define CONFIG_SYS_DDR_MODE_CTRL        0x00000000
 150 #define CONFIG_SYS_DDR_INTERVAL         0x61800100
 151 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 152 #define CONFIG_SYS_DDR_CLK_CTRL         0x02000000
 153 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 154 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 155 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 156 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x8655A608
 157 #define CONFIG_SYS_DDR_CONTROL          0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
 158 #define CONFIG_SYS_DDR_CONTROL2         0x24400011
 159 #define CONFIG_SYS_DDR_CDR1             0x00040000
 160 #define CONFIG_SYS_DDR_CDR2             0x00000000
 161
 162 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 163 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 164 #define CONFIG_SYS_DDR_SBE              0x00010000
 165
 166 /* Settings that differ for "performance" mode */
 167 #define CONFIG_SYS_DDR_CS0_BNDS_PERF            0x0000007F /* Interleaving Enabled */
 168 #define CONFIG_SYS_DDR_CS1_BNDS_PERF            0x00000000 /* Interleaving Enabled */
 169 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF  0x80014202
 170 #define CONFIG_SYS_DDR_TIMING_1_PERF            0x5d5b4543
 171 #define CONFIG_SYS_DDR_TIMING_2_PERF            0x0fa890ce
 172 #define CONFIG_SYS_DDR_CONTROL_PERF             0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
 173
 174 /*
 175  * The following set of values were tested for DDR2
 176  * with a DDR3 to DDR2 interposer
 177  *
 178 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 179 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
 180 #define CONFIG_SYS_DDR_TIMING_1         0x3935d322
 181 #define CONFIG_SYS_DDR_TIMING_2         0x14904cc8
 182 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 183 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 184 #define CONFIG_SYS_DDR_INTERVAL         0x06180100
 185 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 186 #define CONFIG_SYS_DDR_CLK_CTRL         0x03800000
 187 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 188 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 189 #define CONFIG_SYS_DDR_CONTROL          0xC3008000
 190 #define CONFIG_SYS_DDR_CONTROL2         0x04400010
 191  *
 192  */
 193
 194 /*
 195  * Memory map
 196  *
 197  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 198  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 199  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 200  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 201  *
 202  * Localbus cacheable (TBD)
 203  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 204  *
 205  * Localbus non-cacheable
 206  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 207  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 208  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 209  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 210  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 211  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 212  */
 213
 214 /*
 215  * Local Bus Definitions
 216  */
 217 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 218 #ifdef CONFIG_PHYS_64BIT
 219 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 220 #else
 221 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 222 #endif
 223
 224 #define CONFIG_FLASH_BR_PRELIM  \
 225         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 226 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 227
 228 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 229 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 230
 231 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 232 #define CONFIG_SYS_FLASH_QUIET_TEST
 233 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 234
 235 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 236 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 237 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 238 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 239
 240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 241
 242 #define CONFIG_FLASH_CFI_DRIVER
 243 #define CONFIG_SYS_FLASH_CFI
 244 #define CONFIG_SYS_FLASH_EMPTY_INFO
 245 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 246
 247 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 248
 249 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 250 #define CONFIG_FSL_NGPIXIS              /* use common ngPIXIS code */
 251
 252 #ifdef CONFIG_FSL_NGPIXIS
 253 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 254 #ifdef CONFIG_PHYS_64BIT
 255 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 256 #else
 257 #define PIXIS_BASE_PHYS PIXIS_BASE
 258 #endif
 259
 260 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 261 #define CONFIG_SYS_OR3_PRELIM           0xffffeff7      /* 32KB but only 4k mapped */
 262
 263 #define PIXIS_LBMAP_SWITCH      7
 264 #define PIXIS_LBMAP_MASK        0xf0
 265 #define PIXIS_LBMAP_SHIFT       4
 266 #define PIXIS_LBMAP_ALTBANK     0x20
 267 #endif
 268
 269 #define CONFIG_SYS_INIT_RAM_LOCK        1
 270 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 271 #ifdef CONFIG_PHYS_64BIT
 272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 274 /* The assembler doesn't like typecast */
 275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 276         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 277           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 278 #else
 279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 282 #endif
 283 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 284
 285 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 286 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 287
 288 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 289 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 290
 291 #define CONFIG_SYS_NAND_BASE            0xffa00000
 292 #ifdef CONFIG_PHYS_64BIT
 293 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 294 #else
 295 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 296 #endif
 297 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE,\
 298                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 299                                 CONFIG_SYS_NAND_BASE + 0x80000,\
 300                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 301 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 302 #define CONFIG_MTD_NAND_VERIFY_WRITE
 303 #define CONFIG_CMD_NAND                 1
 304 #define CONFIG_NAND_FSL_ELBC            1
 305 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 306
 307 /* NAND flash config */
 308 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 309                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 310                                 | BR_PS_8               /* Port Size = 8bit */ \
 311                                 | BR_MS_FCM             /* MSEL = FCM */ \
 312                                 | BR_V)                 /* valid */
 313 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000          /* length 256K */ \
 314                                 | OR_FCM_PGS            /* Large Page*/ \
 315                                 | OR_FCM_CSCT \
 316                                 | OR_FCM_CST \
 317                                 | OR_FCM_CHT \
 318                                 | OR_FCM_SCY_1 \
 319                                 | OR_FCM_TRLX \
 320                                 | OR_FCM_EHTR)
 321
 322 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 323 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 324 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM  /* NAND Base Address */
 325 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM  /* NAND Options */
 326
 327 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
 328                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 329                                 | BR_PS_8               /* Port Size = 8bit */ \
 330                                 | BR_MS_FCM             /* MSEL = FCM */ \
 331                                 | BR_V)                 /* valid */
 332 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM        /* NAND Options */
 333 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
 334                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 335                                 | BR_PS_8               /* Port Size = 8bit */ \
 336                                 | BR_MS_FCM             /* MSEL = FCM */ \
 337                                 | BR_V)                 /* valid */
 338 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM        /* NAND Options */
 339
 340 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
 341                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 342                                 | BR_PS_8               /* Port Size = 8bit */ \
 343                                 | BR_MS_FCM             /* MSEL = FCM */ \
 344                                 | BR_V)                 /* valid */
 345 #define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM        /* NAND Options */
 346
 347 /* Serial Port - controlled on board with jumper J8
 348  * open - index 2
 349  * shorted - index 1
 350  */
 351 #define CONFIG_CONS_INDEX       1
 352 #define CONFIG_SYS_NS16550
 353 #define CONFIG_SYS_NS16550_SERIAL
 354 #define CONFIG_SYS_NS16550_REG_SIZE     1
 355 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 356
 357 #define CONFIG_SYS_BAUDRATE_TABLE       \
 358         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 359
 360 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 361 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 362
 363 /* Use the HUSH parser */
 364 #define CONFIG_SYS_HUSH_PARSER
 365
 366 /*
 367  * Pass open firmware flat tree
 368  */
 369 #define CONFIG_OF_LIBFDT                1
 370 #define CONFIG_OF_BOARD_SETUP           1
 371 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 372
 373 /* I2C */
 374 #define CONFIG_SYS_I2C
 375 #define CONFIG_SYS_I2C_FSL
 376 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 377 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 378 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 379 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 380 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 381 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 382 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 383 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 384
 385 /*
 386  * I2C2 EEPROM
 387  */
 388 #define CONFIG_ID_EEPROM
 389 #ifdef CONFIG_ID_EEPROM
 390 #define CONFIG_SYS_I2C_EEPROM_NXID
 391 #endif
 392 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 393 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 394 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 395
 396 /*
 397  * eSPI - Enhanced SPI
 398  */
 399 #define CONFIG_FSL_ESPI
 400
 401 #define CONFIG_SPI_FLASH
 402 #define CONFIG_SPI_FLASH_SPANSION
 403
 404 #define CONFIG_CMD_SF
 405 #define CONFIG_SF_DEFAULT_SPEED         10000000
 406 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 407
 408 /*
 409  * General PCI
 410  * Memory space is mapped 1-1, but I/O space must start from 0.
 411  */
 412
 413 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 414 #define CONFIG_SYS_PCIE3_NAME           "Slot 1"
 415 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 416 #ifdef CONFIG_PHYS_64BIT
 417 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 418 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 419 #else
 420 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 421 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 422 #endif
 423 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 424 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 425 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 426 #ifdef CONFIG_PHYS_64BIT
 427 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 428 #else
 429 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 430 #endif
 431 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 432
 433 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 434 #define CONFIG_SYS_PCIE2_NAME           "ULI"
 435 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 436 #ifdef CONFIG_PHYS_64BIT
 437 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 438 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 439 #else
 440 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 441 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 442 #endif
 443 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 444 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 445 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 446 #ifdef CONFIG_PHYS_64BIT
 447 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 448 #else
 449 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 450 #endif
 451 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 452
 453 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 454 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 455 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 456 #ifdef CONFIG_PHYS_64BIT
 457 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 458 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 459 #else
 460 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 461 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 462 #endif
 463 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 464 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 465 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 466 #ifdef CONFIG_PHYS_64BIT
 467 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 468 #else
 469 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 470 #endif
 471 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 472
 473 #if defined(CONFIG_PCI)
 474
 475 /*PCIE video card used*/
 476 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 477
 478 /* video */
 479 #undef CONFIG_VIDEO
 480
 481 #if defined(CONFIG_VIDEO)
 482 #define CONFIG_BIOSEMU
 483 #define CONFIG_CFB_CONSOLE
 484 #define CONFIG_VIDEO_SW_CURSOR
 485 #define CONFIG_VGA_AS_SINGLE_DEVICE
 486 #define CONFIG_ATI_RADEON_FB
 487 #define CONFIG_VIDEO_LOGO
 488 /*#define CONFIG_CONSOLE_CURSOR*/
 489 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 490 #endif
 491
 492 /* SRIO1 uses the same window as PCIE2 mem window */
 493 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 494 #ifdef CONFIG_PHYS_64BIT
 495 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 496 #else
 497 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 498 #endif
 499 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 500
 501 /* SRIO2 uses the same window as PCIE1 mem window */
 502 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xc0000000
 503 #ifdef CONFIG_PHYS_64BIT
 504 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc40000000ull
 505 #else
 506 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc0000000
 507 #endif
 508 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x20000000      /* 512M */
 509
 510 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 511 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 512 #define CONFIG_DOS_PARTITION
 513 #define CONFIG_SCSI_AHCI
 514
 515 #ifdef CONFIG_SCSI_AHCI
 516 #define CONFIG_LIBATA
 517 #define CONFIG_SATA_ULI5288
 518 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 519 #define CONFIG_SYS_SCSI_MAX_LUN 1
 520 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 521 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 522 #endif /* SCSI */
 523
 524 #endif  /* CONFIG_PCI */
 525
 526
 527 #if defined(CONFIG_TSEC_ENET)
 528
 529 #define CONFIG_MII              1       /* MII PHY management */
 530 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 531 #define CONFIG_TSEC1    1
 532 #define CONFIG_TSEC1_NAME       "eTSEC1"
 533 #define CONFIG_TSEC2    1
 534 #define CONFIG_TSEC2_NAME       "eTSEC2"
 535 #define CONFIG_TSEC3    1
 536 #define CONFIG_TSEC3_NAME       "eTSEC3"
 537
 538 #define CONFIG_FSL_SGMII_RISER  1
 539 #define SGMII_RISER_PHY_OFFSET  0x1b
 540
 541 #ifdef CONFIG_FSL_SGMII_RISER
 542 #define CONFIG_SYS_TBIPA_VALUE          0x10 /* avoid conflict with eTSEC4 paddr */
 543 #endif
 544
 545 #define TSEC1_PHY_ADDR          0
 546 #define TSEC2_PHY_ADDR          1
 547 #define TSEC3_PHY_ADDR          2
 548
 549 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 550 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 551 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 552
 553 #define TSEC1_PHYIDX            0
 554 #define TSEC2_PHYIDX            0
 555 #define TSEC3_PHYIDX            0
 556
 557 #define CONFIG_ETHPRIME         "eTSEC1"
 558
 559 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 560 #endif  /* CONFIG_TSEC_ENET */
 561
 562 /*
 563  * Environment
 564  */
 565 #if defined(CONFIG_SDCARD)
 566 #define CONFIG_ENV_IS_IN_MMC
 567 #define CONFIG_FSL_FIXED_MMC_LOCATION
 568 #define CONFIG_ENV_SIZE                 0x2000
 569 #define CONFIG_SYS_MMC_ENV_DEV          0
 570 #elif defined(CONFIG_SPIFLASH)
 571 #define CONFIG_ENV_IS_IN_SPI_FLASH
 572 #define CONFIG_ENV_SPI_BUS              0
 573 #define CONFIG_ENV_SPI_CS               0
 574 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 575 #define CONFIG_ENV_SPI_MODE             0
 576 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 577 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 578 #define CONFIG_ENV_SECT_SIZE            0x10000
 579 #else
 580 #define CONFIG_ENV_IS_IN_FLASH  1
 581 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 582 #define CONFIG_ENV_SIZE         0x2000
 583 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 584 #endif
 585
 586 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 587 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 588
 589 /*
 590  * Command line configuration.
 591  */
 592 #include <config_cmd_default.h>
 593
 594 #define CONFIG_CMD_IRQ
 595 #define CONFIG_CMD_PING
 596 #define CONFIG_CMD_I2C
 597 #define CONFIG_CMD_MII
 598 #define CONFIG_CMD_ELF
 599 #define CONFIG_CMD_IRQ
 600 #define CONFIG_CMD_SETEXPR
 601 #define CONFIG_CMD_REGINFO
 602
 603 #if defined(CONFIG_PCI)
 604 #define CONFIG_CMD_PCI
 605 #define CONFIG_CMD_NET
 606 #define CONFIG_CMD_SCSI
 607 #define CONFIG_CMD_EXT2
 608 #endif
 609
 610 /*
 611  * USB
 612  */
 613 #define CONFIG_HAS_FSL_DR_USB
 614 #ifdef CONFIG_HAS_FSL_DR_USB
 615 #define CONFIG_USB_EHCI
 616
 617 #ifdef CONFIG_USB_EHCI
 618 #define CONFIG_CMD_USB
 619 #define CONFIG_USB_STORAGE
 620 #define CONFIG_USB_EHCI_FSL
 621 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 622 #endif
 623 #endif
 624
 625 /*
 626  * SDHC/MMC
 627  */
 628 #define CONFIG_MMC
 629
 630 #ifdef CONFIG_MMC
 631 #define CONFIG_FSL_ESDHC
 632 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 633 #define CONFIG_CMD_MMC
 634 #define CONFIG_GENERIC_MMC
 635 #endif
 636
 637 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 638 #define CONFIG_CMD_EXT2
 639 #define CONFIG_CMD_FAT
 640 #define CONFIG_DOS_PARTITION
 641 #endif
 642
 643 /*
 644  * Miscellaneous configurable options
 645  */
 646 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 647 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 648 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 649 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 650 #if defined(CONFIG_CMD_KGDB)
 651 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 652 #else
 653 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 654 #endif
 655 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 656 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 657 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 658
 659 /*
 660  * For booting Linux, the board info and command line data
 661  * have to be in the first 64 MB of memory, since this is
 662  * the maximum mapped by the Linux kernel during initialization.
 663  */
 664 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 665 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 666
 667 #if defined(CONFIG_CMD_KGDB)
 668 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 669 #endif
 670
 671 /*
 672  * Environment Configuration
 673  */
 674
 675 /* The mac addresses for all ethernet interface */
 676 #if defined(CONFIG_TSEC_ENET)
 677 #define CONFIG_HAS_ETH0
 678 #define CONFIG_HAS_ETH1
 679 #define CONFIG_HAS_ETH2
 680 #endif
 681
 682 #define CONFIG_IPADDR           192.168.1.254
 683
 684 #define CONFIG_HOSTNAME         unknown
 685 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 686 #define CONFIG_BOOTFILE         "uImage"
 687 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 688
 689 #define CONFIG_SERVERIP         192.168.1.1
 690 #define CONFIG_GATEWAYIP        192.168.1.1
 691 #define CONFIG_NETMASK          255.255.255.0
 692
 693 /* default location for tftp and bootm */
 694 #define CONFIG_LOADADDR         1000000
 695
 696 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 697
 698 #define CONFIG_BAUDRATE 115200
 699
 700 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 701 "perf_mode=performance\0"                       \
 702         "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;"  \
 703         "usb1:dr_mode=host,phy_type=ulpi\0"                     \
 704 "netdev=eth0\0"                                         \
 705 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 706 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 707         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 708         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 709         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 710         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 711         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 712 "satabootcmd=setenv bootargs root=/dev/$bdev rw "       \
 713         "console=$consoledev,$baudrate $othbootargs;"   \
 714         "tftp $loadaddr $bootfile;"                     \
 715         "tftp $fdtaddr $fdtfile;"                       \
 716         "bootm $loadaddr - $fdtaddr"                    \
 717 "consoledev=ttyS0\0"                            \
 718 "ramdiskaddr=2000000\0"                 \
 719 "ramdiskfile=p2020ds/ramdisk.uboot\0"           \
 720 "fdtaddr=c00000\0"                              \
 721 "othbootargs=cache-sram-size=0x10000\0" \
 722 "fdtfile=p2020ds/p2020ds.dtb\0"         \
 723 "bdev=sda3\0"                                   \
 724 "partition=scsi 0:0\0"
 725
 726 #define CONFIG_HDBOOT                           \
 727  "setenv bootargs root=/dev/$bdev rw "          \
 728  "console=$consoledev,$baudrate $othbootargs;"  \
 729  "ext2load $partition $loadaddr $bootfile;"     \
 730  "ext2load $partition $fdtaddr $fdtfile;"       \
 731  "bootm $loadaddr - $fdtaddr"
 732
 733 #define CONFIG_NFSBOOTCOMMAND           \
 734  "setenv bootargs root=/dev/nfs rw "    \
 735  "nfsroot=$serverip:$rootpath "         \
 736  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 737  "console=$consoledev,$baudrate $othbootargs;"  \
 738  "tftp $loadaddr $bootfile;"            \
 739  "tftp $fdtaddr $fdtfile;"              \
 740  "bootm $loadaddr - $fdtaddr"
 741
 742 #define CONFIG_RAMBOOTCOMMAND           \
 743  "setenv bootargs root=/dev/ram rw "    \
 744  "console=$consoledev,$baudrate $othbootargs;"  \
 745  "tftp $ramdiskaddr $ramdiskfile;"      \
 746  "tftp $loadaddr $bootfile;"            \
 747  "tftp $fdtaddr $fdtfile;"              \
 748  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 749
 750 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 751
 752 #endif  /* __CONFIG_H */