2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P1 P2 RDB board configuration file
25 * This file is intended to address a set of Low End and Ultra Low End
26 * Freescale SOCs of QorIQ series(RDB platforms).
27 * Currently only P2020RDB
34 #define CONFIG_PHYS_64BIT
37 #ifdef CONFIG_P1011RDB
40 #ifdef CONFIG_P1020RDB
43 #ifdef CONFIG_P2010RDB
46 #ifdef CONFIG_P2020RDB
51 #define CONFIG_NAND_U_BOOT 1
52 #define CONFIG_RAMBOOT_NAND 1
53 #ifdef CONFIG_NAND_SPL
54 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
57 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
58 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
59 #endif /* CONFIG_NAND_SPL */
63 #define CONFIG_RAMBOOT_SDCARD 1
64 #define CONFIG_SYS_TEXT_BASE 0x11000000
65 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
68 #ifdef CONFIG_SPIFLASH
69 #define CONFIG_RAMBOOT_SPIFLASH 1
70 #define CONFIG_SYS_TEXT_BASE 0x11000000
71 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
74 #ifndef CONFIG_SYS_TEXT_BASE
75 #define CONFIG_SYS_TEXT_BASE 0xeff80000
78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
79 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
82 #ifndef CONFIG_SYS_MONITOR_BASE
83 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
86 /* High Level Configuration Options */
87 #define CONFIG_BOOKE 1 /* BOOKE */
88 #define CONFIG_E500 1 /* BOOKE e500 family */
89 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
90 #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
92 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
93 #if defined(CONFIG_PCI)
94 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
95 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
96 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
97 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
98 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
99 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
100 #endif /* #if defined(CONFIG_PCI) */
101 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
102 #define CONFIG_TSEC_ENET /* tsec ethernet support */
103 #define CONFIG_ENV_OVERWRITE
105 #if defined(CONFIG_PCI)
106 #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
110 extern unsigned long get_board_sys_clk(unsigned long dummy);
112 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
113 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
115 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
119 #define CONFIG_HWCONFIG
122 * These can be toggled for performance analysis, otherwise use default.
124 #define CONFIG_L2_CACHE /* toggle L2 cache */
125 #define CONFIG_BTB /* toggle branch predition */
127 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
129 #define CONFIG_ENABLE_36BIT_PHYS 1
131 #ifdef CONFIG_PHYS_64BIT
132 #define CONFIG_ADDR_MAP 1
133 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
136 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
137 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
138 #define CONFIG_PANIC_HANG /* do not reset board on panic */
141 * Config the L2 Cache as L2 SRAM
143 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
144 #ifdef CONFIG_PHYS_64BIT
145 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
147 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
149 #define CONFIG_SYS_L2_SIZE (512 << 10)
150 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
152 #define CONFIG_SYS_CCSRBAR 0xffe00000
153 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
155 #if defined(CONFIG_NAND_SPL)
156 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
160 #define CONFIG_FSL_DDR2
161 #undef CONFIG_FSL_DDR_INTERACTIVE
162 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
164 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
166 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
167 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
168 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
170 #define CONFIG_NUM_DDR_CONTROLLERS 1
171 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
172 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
174 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
175 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
176 #define CONFIG_SYS_DDR_SBE 0x00FF0000
181 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
182 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
183 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
185 * Localbus cacheable (TBD)
186 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
188 * Localbus non-cacheable
189 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
190 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
191 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
192 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
193 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
197 * Local Bus Definitions
199 #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
201 #ifdef CONFIG_PHYS_64BIT
202 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull
204 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
207 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
209 #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
211 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
212 #define CONFIG_SYS_FLASH_QUIET_TEST
213 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
215 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
216 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
217 #undef CONFIG_SYS_FLASH_CHECKSUM
218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
221 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
222 defined(CONFIG_RAMBOOT_SPIFLASH)
223 #define CONFIG_SYS_RAMBOOT
224 #define CONFIG_SYS_EXTRA_ENV_RELOC
226 #undef CONFIG_SYS_RAMBOOT
229 #define CONFIG_FLASH_CFI_DRIVER
230 #define CONFIG_SYS_FLASH_CFI
231 #define CONFIG_SYS_FLASH_EMPTY_INFO
232 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
234 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
235 #define CONFIG_MISC_INIT_R
236 #define CONFIG_HWCONFIG
238 #define CONFIG_SYS_INIT_RAM_LOCK 1
239 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
240 #ifdef CONFIG_PHYS_64BIT
241 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
243 /* The assembler doesn't like typecast */
244 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
245 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
246 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
248 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
249 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
250 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
252 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
254 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
255 - GENERATED_GBL_DATA_SIZE)
256 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
258 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
259 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
261 #ifndef CONFIG_NAND_SPL
262 #define CONFIG_SYS_NAND_BASE 0xffa00000
263 #ifdef CONFIG_PHYS_64BIT
264 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
266 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
269 #define CONFIG_SYS_NAND_BASE 0xfff00000
270 #ifdef CONFIG_PHYS_64BIT
271 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
273 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
277 #define CONFIG_CMD_NAND
278 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
279 #define CONFIG_SYS_MAX_NAND_DEVICE 1
280 #define CONFIG_MTD_NAND_VERIFY_WRITE
281 #define CONFIG_NAND_FSL_ELBC 1
282 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
284 /* NAND boot: 4K NAND loader config */
285 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
286 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
287 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
288 #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
289 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
290 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
291 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
293 /* NAND flash config */
294 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
295 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
296 | BR_PS_8 /* Port Size = 8 bit */ \
297 | BR_MS_FCM /* MSEL = FCM */ \
300 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
308 #ifdef CONFIG_RAMBOOT_NAND
309 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
310 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
311 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
312 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
314 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
315 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
316 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
317 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
320 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
322 #ifdef CONFIG_PHYS_64BIT
323 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
325 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
328 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
330 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
331 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
332 OR_GPCM_EHTR | OR_GPCM_EAD)
334 /* Serial Port - controlled on board with jumper J8
338 #define CONFIG_CONS_INDEX 1
339 #define CONFIG_SYS_NS16550
340 #define CONFIG_SYS_NS16550_SERIAL
341 #define CONFIG_SYS_NS16550_REG_SIZE 1
342 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
343 #ifdef CONFIG_NAND_SPL
344 #define CONFIG_NS16550_MIN_FUNCTIONS
347 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
349 #define CONFIG_SYS_BAUDRATE_TABLE \
350 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
352 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
353 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
355 /* Use the HUSH parser */
356 #define CONFIG_SYS_HUSH_PARSER
359 * Pass open firmware flat tree
361 #define CONFIG_OF_LIBFDT 1
362 #define CONFIG_OF_BOARD_SETUP 1
363 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
365 /* new uImage format support */
367 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
370 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
371 #define CONFIG_HARD_I2C /* I2C with hardware support */
372 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
373 #define CONFIG_I2C_MULTI_BUS
374 #define CONFIG_I2C_CMD_TREE
375 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
376 #define CONFIG_SYS_I2C_SLAVE 0x7F
377 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
378 #define CONFIG_SYS_I2C_OFFSET 0x3000
379 #define CONFIG_SYS_I2C2_OFFSET 0x3100
384 #define CONFIG_ID_EEPROM
385 #ifdef CONFIG_ID_EEPROM
386 #define CONFIG_SYS_I2C_EEPROM_NXID
388 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
389 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
390 #define CONFIG_SYS_EEPROM_BUS_NUM 1
392 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
394 #define CONFIG_RTC_DS1337
395 #define CONFIG_SYS_RTC_DS1337_NOOSC
396 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
398 /* eSPI - Enhanced SPI */
399 #define CONFIG_FSL_ESPI
400 #define CONFIG_SPI_FLASH
401 #define CONFIG_SPI_FLASH_SPANSION
402 #define CONFIG_CMD_SF
403 #define CONFIG_SF_DEFAULT_SPEED 10000000
404 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
408 * Memory space is mapped 1-1, but I/O space must start from 0.
411 #if defined(CONFIG_PCI)
412 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
413 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
414 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
415 #ifdef CONFIG_PHYS_64BIT
416 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
417 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
419 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
420 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
422 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
423 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
424 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
428 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
430 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
432 /* controller 1, Slot 1, tgtid 1, Base address a000 */
433 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
434 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
435 #ifdef CONFIG_PHYS_64BIT
436 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
437 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
439 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
440 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
442 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
443 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
444 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
445 #ifdef CONFIG_PHYS_64BIT
446 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
448 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
450 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
452 #define CONFIG_PCI_PNP /* do pci plug-and-play */
454 #undef CONFIG_EEPRO100
456 #undef CONFIG_RTL8139
458 #ifdef CONFIG_RTL8139
459 /* This macro is used by RTL8139 but not defined in PPC architecture */
460 #define KSEG1ADDR(x) (x)
461 #define _IO_BASE 0x00000000
465 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
466 #define CONFIG_DOS_PARTITION
468 #endif /* CONFIG_PCI */
471 #if defined(CONFIG_TSEC_ENET)
472 #define CONFIG_MII 1 /* MII PHY management */
473 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
474 #define CONFIG_TSEC1 1
475 #define CONFIG_TSEC1_NAME "eTSEC1"
476 #define CONFIG_TSEC2 1
477 #define CONFIG_TSEC2_NAME "eTSEC2"
478 #define CONFIG_TSEC3 1
479 #define CONFIG_TSEC3_NAME "eTSEC3"
481 #define TSEC1_PHY_ADDR 2
482 #define TSEC2_PHY_ADDR 0
483 #define TSEC3_PHY_ADDR 1
485 #define CONFIG_VSC7385_ENET
487 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
488 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
489 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
491 #define TSEC1_PHYIDX 0
492 #define TSEC2_PHYIDX 0
493 #define TSEC3_PHYIDX 0
497 #ifdef CONFIG_VSC7385_ENET
498 /* The size of the VSC7385 firmware image */
499 #define CONFIG_VSC7385_IMAGE_SIZE 8192
502 #define CONFIG_ETHPRIME "eTSEC1"
504 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
506 #endif /* CONFIG_TSEC_ENET */
511 #if defined(CONFIG_SYS_RAMBOOT)
512 #if defined(CONFIG_RAMBOOT_NAND)
513 #define CONFIG_ENV_IS_IN_NAND 1
514 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
515 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
516 #elif defined(CONFIG_RAMBOOT_SDCARD)
517 #define CONFIG_ENV_IS_IN_MMC
518 #define CONFIG_FSL_FIXED_MMC_LOCATION
519 #define CONFIG_ENV_SIZE 0x2000
520 #define CONFIG_SYS_MMC_ENV_DEV 0
521 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
522 #define CONFIG_ENV_IS_IN_SPI_FLASH
523 #define CONFIG_ENV_SPI_BUS 0
524 #define CONFIG_ENV_SPI_CS 0
525 #define CONFIG_ENV_SPI_MAX_HZ 10000000
526 #define CONFIG_ENV_SPI_MODE 0
527 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
528 #define CONFIG_ENV_SECT_SIZE 0x10000
529 #define CONFIG_ENV_SIZE 0x2000
532 #define CONFIG_ENV_IS_IN_FLASH 1
533 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
534 #define CONFIG_ENV_ADDR 0xfff80000
536 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
538 #define CONFIG_ENV_SIZE 0x2000
539 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
542 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
543 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
546 * Command line configuration.
548 #include <config_cmd_default.h>
550 #define CONFIG_CMD_DATE
551 #define CONFIG_CMD_ELF
552 #define CONFIG_CMD_I2C
553 #define CONFIG_CMD_IRQ
554 #define CONFIG_CMD_MII
555 #define CONFIG_CMD_PING
556 #define CONFIG_CMD_SETEXPR
557 #define CONFIG_CMD_REGINFO
559 #if defined(CONFIG_PCI)
560 #define CONFIG_CMD_NET
561 #define CONFIG_CMD_PCI
564 #undef CONFIG_WATCHDOG /* watchdog disabled */
569 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
570 #define CONFIG_CMD_MMC
571 #define CONFIG_DOS_PARTITION
572 #define CONFIG_FSL_ESDHC
573 #define CONFIG_GENERIC_MMC
574 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
576 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
580 #define CONFIG_HAS_FSL_DR_USB
582 #if defined(CONFIG_HAS_FSL_DR_USB)
583 #define CONFIG_USB_EHCI
585 #ifdef CONFIG_USB_EHCI
586 #define CONFIG_CMD_USB
587 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
588 #define CONFIG_USB_EHCI_FSL
589 #define CONFIG_USB_STORAGE
593 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
594 #define CONFIG_CMD_EXT2
595 #define CONFIG_CMD_FAT
596 #define CONFIG_DOS_PARTITION
600 * Miscellaneous configurable options
602 #define CONFIG_SYS_LONGHELP /* undef to save memory */
603 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
604 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
605 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
606 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
607 #if defined(CONFIG_CMD_KGDB)
608 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
610 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
612 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
613 /* Print Buffer Size */
614 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
615 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
616 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
619 * For booting Linux, the board info and command line data
620 * have to be in the first 64 MB of memory, since this is
621 * the maximum mapped by the Linux kernel during initialization.
623 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/
624 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
626 #if defined(CONFIG_CMD_KGDB)
627 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
628 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
632 * Environment Configuration
635 #if defined(CONFIG_TSEC_ENET)
636 #define CONFIG_HAS_ETH0
637 #define CONFIG_HAS_ETH1
638 #define CONFIG_HAS_ETH2
641 #define CONFIG_HOSTNAME P2020RDB
642 #define CONFIG_ROOTPATH "/opt/nfsroot"
643 #define CONFIG_BOOTFILE "uImage"
644 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
646 /* default location for tftp and bootm */
647 #define CONFIG_LOADADDR 1000000
649 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
650 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
652 #define CONFIG_BAUDRATE 115200
654 #define CONFIG_EXTRA_ENV_SETTINGS \
656 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
657 "loadaddr=1000000\0" \
658 "tftpflash=tftpboot $loadaddr $uboot; " \
659 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
661 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
663 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
665 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
667 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
669 "consoledev=ttyS0\0" \
670 "ramdiskaddr=2000000\0" \
671 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
673 "fdtfile=p2020rdb.dtb\0" \
675 "jffs2nor=mtdblock3\0" \
676 "norbootaddr=ef080000\0" \
677 "norfdtaddr=ef040000\0" \
678 "jffs2nand=mtdblock9\0" \
679 "nandbootaddr=100000\0" \
680 "nandfdtaddr=80000\0" \
681 "nandimgsize=400000\0" \
682 "nandfdtsize=80000\0" \
683 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
684 "vscfw_addr=ef000000\0" \
685 "othbootargs=ramdisk_size=600000\0" \
686 "usbfatboot=setenv bootargs root=/dev/ram rw " \
687 "console=$consoledev,$baudrate $othbootargs; " \
689 "fatload usb 0:2 $loadaddr $bootfile;" \
690 "fatload usb 0:2 $fdtaddr $fdtfile;" \
691 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
692 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
693 "usbext2boot=setenv bootargs root=/dev/ram rw " \
694 "console=$consoledev,$baudrate $othbootargs; " \
696 "ext2load usb 0:4 $loadaddr $bootfile;" \
697 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
698 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
699 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
700 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
701 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
702 "bootm $norbootaddr - $norfdtaddr\0" \
703 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
704 "console=$consoledev,$baudrate $othbootargs;" \
705 "nand read 2000000 $nandbootaddr $nandimgsize;" \
706 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
707 "bootm 2000000 - 3000000;\0"
709 #define CONFIG_NFSBOOTCOMMAND \
710 "setenv bootargs root=/dev/nfs rw " \
711 "nfsroot=$serverip:$rootpath " \
712 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
713 "console=$consoledev,$baudrate $othbootargs;" \
714 "tftp $loadaddr $bootfile;" \
715 "tftp $fdtaddr $fdtfile;" \
716 "bootm $loadaddr - $fdtaddr"
718 #define CONFIG_HDBOOT \
719 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
720 "console=$consoledev,$baudrate $othbootargs;" \
722 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
723 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
724 "bootm $loadaddr - $fdtaddr"
726 #define CONFIG_RAMBOOTCOMMAND \
727 "setenv bootargs root=/dev/ram rw " \
728 "console=$consoledev,$baudrate $othbootargs; " \
729 "tftp $ramdiskaddr $ramdiskfile;" \
730 "tftp $loadaddr $bootfile;" \
731 "tftp $fdtaddr $fdtfile;" \
732 "bootm $loadaddr $ramdiskaddr $fdtaddr"
734 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
736 #endif /* __CONFIG_H */