2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P1 P2 RDB board configuration file
25 * This file is intended to address a set of Low End and Ultra Low End
26 * Freescale SOCs of QorIQ series(RDB platforms).
27 * Currently only P2020RDB
33 #ifdef CONFIG_P1011RDB
36 #ifdef CONFIG_P1020RDB
39 #ifdef CONFIG_P2010RDB
42 #ifdef CONFIG_P2020RDB
47 #define CONFIG_NAND_U_BOOT 1
48 #define CONFIG_RAMBOOT_NAND 1
49 #ifdef CONFIG_NAND_SPL
50 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
53 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
54 #endif /* CONFIG_NAND_SPL */
58 #define CONFIG_RAMBOOT_SDCARD 1
59 #define CONFIG_SYS_TEXT_BASE 0xf8f80000
62 #ifdef CONFIG_SPIFLASH
63 #define CONFIG_RAMBOOT_SPIFLASH 1
64 #define CONFIG_SYS_TEXT_BASE 0xf8f80000
67 #ifndef CONFIG_SYS_TEXT_BASE
68 #define CONFIG_SYS_TEXT_BASE 0xeff80000
71 #ifndef CONFIG_SYS_MONITOR_BASE
72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
75 /* High Level Configuration Options */
76 #define CONFIG_BOOKE 1 /* BOOKE */
77 #define CONFIG_E500 1 /* BOOKE e500 family */
78 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
79 #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
80 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
81 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
82 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
83 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
84 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
85 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
86 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
87 #define CONFIG_TSEC_ENET /* tsec ethernet support */
88 #define CONFIG_ENV_OVERWRITE
90 #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
92 extern unsigned long get_board_sys_clk(unsigned long dummy);
94 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
95 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
97 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
101 #define CONFIG_HWCONFIG
104 * These can be toggled for performance analysis, otherwise use default.
106 #define CONFIG_L2_CACHE /* toggle L2 cache */
107 #define CONFIG_BTB /* toggle branch predition */
109 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
111 #define CONFIG_ENABLE_36BIT_PHYS 1
113 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
114 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
115 #define CONFIG_PANIC_HANG /* do not reset board on panic */
118 * Config the L2 Cache as L2 SRAM
120 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
121 #ifdef CONFIG_PHYS_64BIT
122 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
124 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
126 #define CONFIG_SYS_L2_SIZE (512 << 10)
127 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
130 * Base addresses -- Note these are effective addresses where the
131 * actual resources get mapped (not physical addresses)
133 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
134 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
136 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
137 /* CONFIG_SYS_IMMR */
139 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
140 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
142 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
146 #define CONFIG_FSL_DDR2
147 #undef CONFIG_FSL_DDR_INTERACTIVE
148 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
149 #undef CONFIG_DDR_DLL
151 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
153 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
154 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
155 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
157 #define CONFIG_NUM_DDR_CONTROLLERS 1
158 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
159 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
161 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
162 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
163 #define CONFIG_SYS_DDR_SBE 0x00FF0000
168 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
169 * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
170 * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
172 * Localbus cacheable (TBD)
173 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
175 * Localbus non-cacheable
176 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
177 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
178 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
179 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
180 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
184 * Local Bus Definitions
186 #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
188 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
190 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
192 #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
194 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
195 #define CONFIG_SYS_FLASH_QUIET_TEST
196 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
198 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
199 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
200 #undef CONFIG_SYS_FLASH_CHECKSUM
201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
204 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
205 defined(CONFIG_RAMBOOT_SPIFLASH)
206 #define CONFIG_SYS_RAMBOOT
207 #define CONFIG_SYS_EXTRA_ENV_RELOC
209 #undef CONFIG_SYS_RAMBOOT
212 #define CONFIG_FLASH_CFI_DRIVER
213 #define CONFIG_SYS_FLASH_CFI
214 #define CONFIG_SYS_FLASH_EMPTY_INFO
215 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
217 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
218 #define CONFIG_HWCONFIG
220 #define CONFIG_SYS_INIT_RAM_LOCK 1
221 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
222 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
224 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
225 - GENERATED_GBL_DATA_SIZE)
226 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
228 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
229 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
231 #ifndef CONFIG_NAND_SPL
232 #define CONFIG_SYS_NAND_BASE 0xffa00000
234 #define CONFIG_SYS_NAND_BASE 0xfff00000
236 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
237 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
238 #define CONFIG_SYS_MAX_NAND_DEVICE 1
239 #define NAND_MAX_CHIPS 1
240 #define CONFIG_MTD_NAND_VERIFY_WRITE
241 #define CONFIG_CMD_NAND 1
242 #define CONFIG_NAND_FSL_ELBC 1
243 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
245 /* NAND boot: 4K NAND loader config */
246 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
247 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
248 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
249 #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
250 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
251 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
252 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
254 /* NAND flash config */
255 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
256 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
257 | BR_PS_8 /* Port Size = 8 bit */ \
258 | BR_MS_FCM /* MSEL = FCM */ \
261 #define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
269 #ifdef CONFIG_RAMBOOT_NAND
270 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
271 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
272 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
273 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
275 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
276 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
277 #define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
278 #define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
281 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
283 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
285 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
286 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
287 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
288 OR_GPCM_EHTR | OR_GPCM_EAD)
290 /* Serial Port - controlled on board with jumper J8
294 #define CONFIG_CONS_INDEX 1
295 #define CONFIG_SYS_NS16550
296 #define CONFIG_SYS_NS16550_SERIAL
297 #define CONFIG_SYS_NS16550_REG_SIZE 1
298 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
299 #ifdef CONFIG_NAND_SPL
300 #define CONFIG_NS16550_MIN_FUNCTIONS
303 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
304 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
306 #define CONFIG_SYS_BAUDRATE_TABLE \
307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
312 /* Use the HUSH parser */
313 #define CONFIG_SYS_HUSH_PARSER
314 #ifdef CONFIG_SYS_HUSH_PARSER
315 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
319 * Pass open firmware flat tree
321 #define CONFIG_OF_LIBFDT 1
322 #define CONFIG_OF_BOARD_SETUP 1
323 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
325 /* new uImage format support */
327 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
330 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
331 #define CONFIG_HARD_I2C /* I2C with hardware support */
332 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
333 #define CONFIG_I2C_MULTI_BUS
334 #define CONFIG_I2C_CMD_TREE
335 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
336 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
337 #define CONFIG_SYS_I2C_SLAVE 0x7F
338 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
339 #define CONFIG_SYS_I2C_OFFSET 0x3000
340 #define CONFIG_SYS_I2C2_OFFSET 0x3100
345 #define CONFIG_ID_EEPROM
346 #ifdef CONFIG_ID_EEPROM
347 #define CONFIG_SYS_I2C_EEPROM_NXID
349 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
350 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
351 #define CONFIG_SYS_EEPROM_BUS_NUM 1
353 #define CONFIG_RTC_DS1337
354 #define CONFIG_SYS_RTC_DS1337_NOOSC
355 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
358 * Memory space is mapped 1-1, but I/O space must start from 0.
361 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
362 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
363 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
364 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
365 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
366 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
367 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
368 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
369 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
371 /* controller 1, Slot 1, tgtid 1, Base address a000 */
372 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
373 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
374 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
375 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
376 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
377 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
378 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
379 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
381 #if defined(CONFIG_PCI)
382 #define CONFIG_NET_MULTI
383 #define CONFIG_PCI_PNP /* do pci plug-and-play */
385 #undef CONFIG_EEPRO100
387 #undef CONFIG_RTL8139
389 #ifdef CONFIG_RTL8139
390 /* This macro is used by RTL8139 but not defined in PPC architecture */
391 #define KSEG1ADDR(x) (x)
392 #define _IO_BASE 0x00000000
396 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
397 #define CONFIG_DOS_PARTITION
399 #endif /* CONFIG_PCI */
401 #if defined(CONFIG_TSEC_ENET)
402 #ifndef CONFIG_NET_MULTI
403 #define CONFIG_NET_MULTI 1
406 #define CONFIG_MII 1 /* MII PHY management */
407 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
408 #define CONFIG_TSEC1 1
409 #define CONFIG_TSEC1_NAME "eTSEC1"
410 #define CONFIG_TSEC2 1
411 #define CONFIG_TSEC2_NAME "eTSEC2"
412 #define CONFIG_TSEC3 1
413 #define CONFIG_TSEC3_NAME "eTSEC3"
415 #define TSEC1_PHY_ADDR 2
416 #define TSEC2_PHY_ADDR 0
417 #define TSEC3_PHY_ADDR 1
419 #define CONFIG_VSC7385_ENET
421 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
422 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
425 #define TSEC1_PHYIDX 0
426 #define TSEC2_PHYIDX 0
427 #define TSEC3_PHYIDX 0
431 #ifdef CONFIG_VSC7385_ENET
432 /* The size of the VSC7385 firmware image */
433 #define CONFIG_VSC7385_IMAGE_SIZE 8192
436 #define CONFIG_ETHPRIME "eTSEC1"
438 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
440 /* TBI PHY configuration for SGMII mode */
441 #define CONFIG_TSEC_TBICR_SETTINGS ( \
443 | TBICR_ANEG_ENABLE \
444 | TBICR_FULL_DUPLEX \
448 #endif /* CONFIG_TSEC_ENET */
453 #if defined(CONFIG_SYS_RAMBOOT)
454 #if defined(CONFIG_RAMBOOT_NAND)
455 #define CONFIG_ENV_IS_IN_NAND 1
456 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
457 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
458 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
459 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
460 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
461 #define CONFIG_ENV_SIZE 0x2000
464 #define CONFIG_ENV_IS_IN_FLASH 1
465 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
466 #define CONFIG_ENV_ADDR 0xfff80000
468 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
470 #define CONFIG_ENV_SIZE 0x2000
471 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
474 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
475 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
478 * Command line configuration.
480 #include <config_cmd_default.h>
482 #define CONFIG_CMD_DATE
483 #define CONFIG_CMD_ELF
484 #define CONFIG_CMD_I2C
485 #define CONFIG_CMD_IRQ
486 #define CONFIG_CMD_MII
487 #define CONFIG_CMD_PING
488 #define CONFIG_CMD_SETEXPR
489 #define CONFIG_CMD_REGINFO
491 #if defined(CONFIG_PCI)
492 #define CONFIG_CMD_NET
493 #define CONFIG_CMD_PCI
496 #undef CONFIG_WATCHDOG /* watchdog disabled */
501 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
502 #define CONFIG_CMD_MMC
503 #define CONFIG_DOS_PARTITION
504 #define CONFIG_FSL_ESDHC
505 #define CONFIG_GENERIC_MMC
506 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
508 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
512 #define CONFIG_USB_EHCI
514 #ifdef CONFIG_USB_EHCI
515 #define CONFIG_CMD_USB
516 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
517 #define CONFIG_USB_EHCI_FSL
518 #define CONFIG_USB_STORAGE
521 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
522 #define CONFIG_CMD_EXT2
523 #define CONFIG_CMD_FAT
524 #define CONFIG_DOS_PARTITION
528 * Miscellaneous configurable options
530 #define CONFIG_SYS_LONGHELP /* undef to save memory */
531 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
532 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
533 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
534 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
535 #if defined(CONFIG_CMD_KGDB)
536 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
538 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
540 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
541 /* Print Buffer Size */
542 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
543 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
544 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
547 * For booting Linux, the board info and command line data
548 * have to be in the first 16 MB of memory, since this is
549 * the maximum mapped by the Linux kernel during initialization.
551 #define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
553 #if defined(CONFIG_CMD_KGDB)
554 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
555 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
559 * Environment Configuration
562 #if defined(CONFIG_TSEC_ENET)
563 #define CONFIG_HAS_ETH0
564 #define CONFIG_HAS_ETH1
565 #define CONFIG_HAS_ETH2
568 #define CONFIG_HOSTNAME P2020RDB
569 #define CONFIG_ROOTPATH /opt/nfsroot
570 #define CONFIG_BOOTFILE uImage
571 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
573 /* default location for tftp and bootm */
574 #define CONFIG_LOADADDR 1000000
576 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
577 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
579 #define CONFIG_BAUDRATE 115200
581 #define CONFIG_EXTRA_ENV_SETTINGS \
583 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
584 "loadaddr=1000000\0" \
585 "tftpflash=tftpboot $loadaddr $uboot; " \
586 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
587 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
588 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
589 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
590 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
591 "consoledev=ttyS0\0" \
592 "ramdiskaddr=2000000\0" \
593 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
595 "fdtfile=p2020rdb.dtb\0" \
597 "jffs2nor=mtdblock3\0" \
598 "norbootaddr=ef080000\0" \
599 "norfdtaddr=ef040000\0" \
600 "jffs2nand=mtdblock9\0" \
601 "nandbootaddr=100000\0" \
602 "nandfdtaddr=80000\0" \
603 "nandimgsize=400000\0" \
604 "nandfdtsize=80000\0" \
605 "usb_phy_type=ulpi\0" \
606 "vscfw_addr=ef000000\0" \
607 "othbootargs=ramdisk_size=600000\0" \
608 "usbfatboot=setenv bootargs root=/dev/ram rw " \
609 "console=$consoledev,$baudrate $othbootargs; " \
611 "fatload usb 0:2 $loadaddr $bootfile;" \
612 "fatload usb 0:2 $fdtaddr $fdtfile;" \
613 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
614 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
615 "usbext2boot=setenv bootargs root=/dev/ram rw " \
616 "console=$consoledev,$baudrate $othbootargs; " \
618 "ext2load usb 0:4 $loadaddr $bootfile;" \
619 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
620 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
621 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
622 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
623 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
624 "bootm $norbootaddr - $norfdtaddr\0" \
625 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
626 "console=$consoledev,$baudrate $othbootargs;" \
627 "nand read 2000000 $nandbootaddr $nandimgsize;" \
628 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
629 "bootm 2000000 - 3000000;\0"
631 #define CONFIG_NFSBOOTCOMMAND \
632 "setenv bootargs root=/dev/nfs rw " \
633 "nfsroot=$serverip:$rootpath " \
634 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
635 "console=$consoledev,$baudrate $othbootargs;" \
636 "tftp $loadaddr $bootfile;" \
637 "tftp $fdtaddr $fdtfile;" \
638 "bootm $loadaddr - $fdtaddr"
640 #define CONFIG_HDBOOT \
641 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
642 "console=$consoledev,$baudrate $othbootargs;" \
644 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
645 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
646 "bootm $loadaddr - $fdtaddr"
648 #define CONFIG_RAMBOOTCOMMAND \
649 "setenv bootargs root=/dev/ram rw " \
650 "console=$consoledev,$baudrate $othbootargs; " \
651 "tftp $ramdiskaddr $ramdiskfile;" \
652 "tftp $loadaddr $bootfile;" \
653 "tftp $fdtaddr $fdtfile;" \
654 "bootm $loadaddr $ramdiskaddr $fdtaddr"
656 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
658 #endif /* __CONFIG_H */