a8b7817a8ef7c78926be217f4c6653f796fb06bb
[platform/kernel/u-boot.git] / include / configs / P1023RDB.h
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
5  *           Chunhe Lan <Chunhe.Lan@freescale.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #define CONFIG_SYS_GENERIC_BOARD
14 #define CONFIG_DISPLAY_BOARDINFO
15
16 #ifndef CONFIG_SYS_TEXT_BASE
17 #define CONFIG_SYS_TEXT_BASE    0xeff40000
18 #endif
19
20 #ifndef CONFIG_SYS_MONITOR_BASE
21 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
22 #endif
23
24 #ifndef CONFIG_RESET_VECTOR_ADDRESS
25 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
26 #endif
27
28 /* High Level Configuration Options */
29 #define CONFIG_BOOKE            /* BOOKE */
30 #define CONFIG_E500             /* BOOKE e500 family */
31 #define CONFIG_P1023
32 #define CONFIG_MP               /* support multiple processors */
33
34 #define CONFIG_FSL_ELBC         /* Has Enhanced localbus controller */
35 #define CONFIG_PCI              /* Enable PCI/PCIE */
36 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
37 #define CONFIG_PCIE1            /* PCIE controler 1 (slot 1) */
38 #define CONFIG_PCIE2            /* PCIE controler 2 (slot 2) */
39 #define CONFIG_PCIE3            /* PCIE controler 3 (slot 3) */
40 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
41 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
42 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
43 #define CONFIG_FSL_LAW          /* Use common FSL init code */
44
45 #ifndef __ASSEMBLY__
46 extern unsigned long get_clock_freq(void);
47 #endif
48
49 #define CONFIG_SYS_CLK_FREQ     66666666
50 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
51
52 /*
53  * These can be toggled for performance analysis, otherwise use default.
54  */
55 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
56 #define CONFIG_BTB                      /* toggle branch predition */
57 #define CONFIG_HWCONFIG
58
59 #define CONFIG_ENABLE_36BIT_PHYS
60
61 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
62 #define CONFIG_SYS_MEMTEST_END          0x02000000
63
64 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
65
66 /* Implement conversion of addresses in the LBC */
67 #define CONFIG_SYS_LBC_LBCR             0x00000000
68 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
69
70 /* DDR Setup */
71 #define CONFIG_VERY_BIG_RAM
72 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
73 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
74
75 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
76 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
77
78 #define CONFIG_DDR_SPD
79 #define CONFIG_SYS_FSL_DDR3
80 #define CONFIG_FSL_DDR_INTERACTIVE
81 #define CONFIG_SYS_SDRAM_SIZE           512u    /* DDR is 512M */
82 #define CONFIG_SYS_SPD_BUS_NUM          0
83 #define SPD_EEPROM_ADDRESS              0x50
84 #define CONFIG_SYS_DDR_RAW_TIMING
85
86 /*
87  * Memory map
88  *
89  * 0x0000_0000  0x1fff_ffff     DDR                     512M cacheable
90  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
91  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
92  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
93  * 0xff00_0000  0xff3f_ffff     DPAA_QBMAN              4M cacheable
94  * 0xff60_0000  0xff7f_ffff     CCSR                    2M non-cacheable
95  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K cacheable TLB0
96  *
97  * Localbus non-cacheable
98  *
99  * 0xec00_0000  0xefff_ffff     NOR flash               64M non-cacheable
100  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
101  */
102
103 /*
104  * Local Bus Definitions
105  */
106 #define CONFIG_SYS_FLASH_BASE           0xec000000 /* start of FLASH 64M */
107 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
108
109 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
110                                 | BR_PS_16 | BR_V)
111 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
112
113 #define CONFIG_FLASH_CFI_DRIVER
114 #define CONFIG_SYS_FLASH_CFI
115 #define CONFIG_SYS_FLASH_EMPTY_INFO
116 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
117 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
118 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
119 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
120
121 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_early_init_f function */
122 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
123
124 #define CONFIG_SYS_INIT_RAM_LOCK
125 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
126 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000/* Size of used area in RAM */
127 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
128                                         GENERATED_GBL_DATA_SIZE)
129 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
130
131 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)      /* Reserve 512 kB for Mon */
132 #define CONFIG_SYS_MALLOC_LEN   (6 * 1024 * 1024) /* Reserved for malloc */
133
134 #define CONFIG_SYS_NAND_BASE            0xffa00000
135 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
136
137 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
138 #define CONFIG_SYS_MAX_NAND_DEVICE      1
139 #define CONFIG_MTD_NAND_VERIFY_WRITE
140 #define CONFIG_CMD_NAND
141 #define CONFIG_NAND_FSL_ELBC
142 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
143
144 /* NAND flash config */
145 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
146                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
147                                 | BR_PS_8               /* Port Size = 8bit */ \
148                                 | BR_MS_FCM             /* MSEL = FCM */ \
149                                 | BR_V)                 /* valid */
150 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB         /* length 256K */ \
151                                 | OR_FCM_PGS \
152                                 | OR_FCM_CSCT \
153                                 | OR_FCM_CST \
154                                 | OR_FCM_CHT \
155                                 | OR_FCM_SCY_1 \
156                                 | OR_FCM_TRLX \
157                                 | OR_FCM_EHTR)
158
159 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
160 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
161 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM
162 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
163
164 /* Serial Port */
165 #define CONFIG_CONS_INDEX               1
166 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
167 #define CONFIG_SYS_NS16550
168 #define CONFIG_SYS_NS16550_SERIAL
169 #define CONFIG_SYS_NS16550_REG_SIZE     1
170 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
171
172 #define CONFIG_SYS_BAUDRATE_TABLE       \
173         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
174
175 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
176 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
177
178 /* Use the HUSH parser */
179 #define CONFIG_SYS_HUSH_PARSER
180
181 /*
182  * Pass open firmware flat tree
183  */
184 #define CONFIG_OF_LIBFDT
185 #define CONFIG_OF_BOARD_SETUP
186 #define CONFIG_OF_STDOUT_VIA_ALIAS
187
188 /* new uImage format support */
189 #define CONFIG_FIT
190 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
191
192 /* I2C */
193 #define CONFIG_SYS_I2C
194 #define CONFIG_SYS_I2C_FSL
195 #define CONFIG_SYS_FSL_I2C_SPEED        400000
196 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
197 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
198 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
199 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
200 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
201
202 /*
203  * I2C2 EEPROM
204  */
205 #define CONFIG_ID_EEPROM
206 #ifdef CONFIG_ID_EEPROM
207 #define CONFIG_SYS_I2C_EEPROM_NXID
208 #endif
209 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
211 #define CONFIG_SYS_EEPROM_BUS_NUM               0
212
213 #define CONFIG_CMD_I2C
214
215 /*
216  * General PCI
217  * Memory space is mapped 1-1, but I/O space must start from 0.
218  */
219
220 /* controller 3, Slot 1, tgtid 3, Base address b000 */
221 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
222 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
223 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
224 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
225 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
226 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
227 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
228 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
229 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
230
231 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
232 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
233 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
234 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
235 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
236 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
237 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
238 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
239 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
240 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
241
242 /* controller 1, Slot 2, tgtid 1, Base address a000 */
243 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
244 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
245 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
246 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
247 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
248 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
249 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
250 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
251 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
252
253 #if defined(CONFIG_PCI)
254 #define CONFIG_E1000            /* Defind e1000 pci Ethernet card */
255 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
256 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
257 #endif  /* CONFIG_PCI */
258
259 /*
260  * Environment
261  */
262 #define CONFIG_ENV_OVERWRITE
263
264 #define CONFIG_ENV_IS_IN_FLASH
265 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
266 #define CONFIG_ENV_SIZE         0x2000
267 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
268
269 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
270 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
271
272 /*
273  * Command line configuration.
274  */
275 #include <config_cmd_default.h>
276
277 #define CONFIG_CMD_IRQ
278 #define CONFIG_CMD_PING
279 #define CONFIG_CMD_MII
280 #define CONFIG_CMD_SETEXPR
281 #define CONFIG_CMD_REGINFO
282
283 #if defined(CONFIG_PCI)
284 #define CONFIG_CMD_PCI
285 #define CONFIG_CMD_NET
286 #endif
287
288 /*
289  * USB
290  */
291 #define CONFIG_HAS_FSL_DR_USB
292 #ifdef CONFIG_HAS_FSL_DR_USB
293 #define CONFIG_USB_EHCI
294
295 #ifdef CONFIG_USB_EHCI
296 #define CONFIG_CMD_USB
297 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
298 #define CONFIG_USB_EHCI_FSL
299 #define CONFIG_USB_STORAGE
300 #define CONFIG_CMD_FAT
301 #define CONFIG_CMD_EXT2
302 #define CONFIG_CMD_FAT
303 #define CONFIG_DOS_PARTITION
304 #endif
305 #endif
306
307 /*
308  * Miscellaneous configurable options
309  */
310 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
311 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
312 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
313 #if defined(CONFIG_CMD_KGDB)
314 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
315 #else
316 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
317 #endif
318 /* Print Buffer Size */
319 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
320 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
321 /* Boot Argument Buffer Size */
322 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
323
324 /*
325  * For booting Linux, the board info and command line data
326  * have to be in the first 64 MB of memory, since this is
327  * the maximum mapped by the Linux kernel during initialization.
328  */
329 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)   /* Initial Memory map for Linux*/
330 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)   /* Increase max gunzip size */
331
332 /*
333  * Environment Configuration
334  */
335 #define CONFIG_BOOTFILE         "uImage"
336 #define CONFIG_UBOOTPATH        (u-boot.bin) /* U-Boot image on TFTP server */
337
338 /* default location for tftp and bootm */
339 #define CONFIG_LOADADDR         1000000
340
341 #define CONFIG_BOOTDELAY -1     /* -1 disables auto-boot */
342
343 #define CONFIG_BAUDRATE 115200
344
345 /* Qman/Bman */
346 #define CONFIG_SYS_DPAA_QBMAN           /* support Q/Bman */
347 #define CONFIG_SYS_QMAN_MEM_BASE        0xff000000
348 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
349 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
350 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
351 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
352 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
353 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
354 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
355                                         CONFIG_SYS_QMAN_CENA_SIZE)
356 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
357 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
358 #define CONFIG_SYS_BMAN_MEM_BASE        0xff200000
359 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
360 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
361 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
362 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
363 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
364 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
365 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
366                                         CONFIG_SYS_BMAN_CENA_SIZE)
367 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
368 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
369
370 /* For FM */
371 #define CONFIG_SYS_DPAA_FMAN
372 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
373
374 #ifdef CONFIG_SYS_DPAA_FMAN
375 #define CONFIG_FMAN_ENET
376 #define CONFIG_PHY_ATHEROS
377 #endif
378
379 /* Default address of microcode for the Linux Fman driver */
380 /* QE microcode/firmware address */
381 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
382 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
383 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
384 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
385
386 #ifdef CONFIG_FMAN_ENET
387 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1
388 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x2
389
390 #define CONFIG_SYS_TBIPA_VALUE  8
391 #define CONFIG_MII              /* MII PHY management */
392 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
393 #endif
394
395 #define CONFIG_EXTRA_ENV_SETTINGS       \
396         "netdev=eth0\0"                                         \
397         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
398         "loadaddr=1000000\0"                                    \
399         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
400         "tftpflash=tftpboot $loadaddr $uboot; "                 \
401                 "protect off $ubootaddr +$filesize; "           \
402                 "erase $ubootaddr +$filesize; "                 \
403                 "cp.b $loadaddr $ubootaddr $filesize; "         \
404                 "protect on $ubootaddr +$filesize; "            \
405                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
406         "consoledev=ttyS0\0"                                    \
407         "ramdiskaddr=2000000\0"                                 \
408         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
409         "fdtaddr=c00000\0"                                      \
410         "fdtfile=p1023rdb.dtb\0"                                \
411         "othbootargs=ramdisk_size=600000\0"                     \
412         "bdev=sda1\0"                                           \
413         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
414
415 #define CONFIG_HDBOOT                                   \
416         "setenv bootargs root=/dev/$bdev rw "           \
417         "console=$consoledev,$baudrate $othbootargs;"   \
418         "tftp $loadaddr $bootfile;"                     \
419         "tftp $fdtaddr $fdtfile;"                       \
420         "bootm $loadaddr - $fdtaddr"
421
422 #define CONFIG_NFSBOOTCOMMAND                                           \
423         "setenv bootargs root=/dev/nfs rw "                             \
424         "nfsroot=$serverip:$rootpath "                                  \
425         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
426         "console=$consoledev,$baudrate $othbootargs;"                   \
427         "tftp $loadaddr $bootfile;"                                     \
428         "tftp $fdtaddr $fdtfile;"                                       \
429         "bootm $loadaddr - $fdtaddr"
430
431 #define CONFIG_RAMBOOTCOMMAND                                           \
432         "setenv bootargs root=/dev/ram rw "                             \
433         "console=$consoledev,$baudrate $othbootargs;"                   \
434         "tftp $ramdiskaddr $ramdiskfile;"                               \
435         "tftp $loadaddr $bootfile;"                                     \
436         "tftp $fdtaddr $fdtfile;"                                       \
437         "bootm $loadaddr $ramdiskaddr $fdtaddr"
438
439 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
440
441 #endif  /* __CONFIG_H */