2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "../board/freescale/common/ics307_clk.h"
15 #define CONFIG_SPL_MMC_MINIMAL
16 #define CONFIG_SPL_FLUSH_IMAGE
17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
18 #define CONFIG_FSL_LAW /* Use common FSL init code */
19 #define CONFIG_SYS_TEXT_BASE 0x11001000
20 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
21 #define CONFIG_SPL_PAD_TO 0x20000
22 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
23 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
24 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
25 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
26 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
28 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
29 #define CONFIG_SPL_MMC_BOOT
30 #ifdef CONFIG_SPL_BUILD
31 #define CONFIG_SPL_COMMON_INIT_DDR
35 #ifdef CONFIG_SPIFLASH
36 #define CONFIG_SPL_SPI_FLASH_MINIMAL
37 #define CONFIG_SPL_FLUSH_IMAGE
38 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
39 #define CONFIG_FSL_LAW /* Use common FSL init code */
40 #define CONFIG_SYS_TEXT_BASE 0x11001000
41 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
42 #define CONFIG_SPL_PAD_TO 0x20000
43 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
50 #define CONFIG_SPL_SPI_BOOT
51 #ifdef CONFIG_SPL_BUILD
52 #define CONFIG_SPL_COMMON_INIT_DDR
56 #define CONFIG_NAND_FSL_ELBC
57 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
58 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
61 #ifdef CONFIG_TPL_BUILD
62 #define CONFIG_SPL_NAND_BOOT
63 #define CONFIG_SPL_FLUSH_IMAGE
64 #define CONFIG_SPL_NAND_INIT
65 #define CONFIG_SPL_COMMON_INIT_DDR
66 #define CONFIG_SPL_MAX_SIZE (128 << 10)
67 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
69 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
70 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
71 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
72 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
73 #elif defined(CONFIG_SPL_BUILD)
74 #define CONFIG_SPL_INIT_MINIMAL
75 #define CONFIG_SPL_FLUSH_IMAGE
76 #define CONFIG_SPL_TEXT_BASE 0xff800000
77 #define CONFIG_SPL_MAX_SIZE 4096
78 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
79 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
80 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
81 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
83 #define CONFIG_SPL_PAD_TO 0x20000
84 #define CONFIG_TPL_PAD_TO 0x20000
85 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
86 #define CONFIG_SYS_TEXT_BASE 0x11001000
87 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
90 /* High Level Configuration Options */
91 #define CONFIG_BOOKE /* BOOKE */
92 #define CONFIG_E500 /* BOOKE e500 family */
93 #define CONFIG_P1022DS
94 #define CONFIG_MP /* support multiple processors */
96 #ifndef CONFIG_SYS_TEXT_BASE
97 #define CONFIG_SYS_TEXT_BASE 0xeff40000
100 #ifndef CONFIG_RESET_VECTOR_ADDRESS
101 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
104 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
105 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
106 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
107 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
108 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
109 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
110 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
112 #define CONFIG_ENABLE_36BIT_PHYS
114 #ifdef CONFIG_PHYS_64BIT
115 #define CONFIG_ADDR_MAP
116 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
119 #define CONFIG_FSL_LAW /* Use common FSL init code */
121 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
122 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
123 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
126 * These can be toggled for performance analysis, otherwise use default.
128 #define CONFIG_L2_CACHE
131 #define CONFIG_SYS_MEMTEST_START 0x00000000
132 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
134 #define CONFIG_SYS_CCSRBAR 0xffe00000
135 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
137 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
139 #ifdef CONFIG_SPL_BUILD
140 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
144 #define CONFIG_DDR_SPD
145 #define CONFIG_VERY_BIG_RAM
146 #define CONFIG_SYS_FSL_DDR3
148 #ifdef CONFIG_DDR_ECC
149 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
150 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
156 #define CONFIG_NUM_DDR_CONTROLLERS 1
157 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
158 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
160 /* I2C addresses of SPD EEPROMs */
161 #define CONFIG_SYS_SPD_BUS_NUM 1
162 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
164 /* These are used when DDR doesn't use SPD. */
165 #define CONFIG_SYS_SDRAM_SIZE 2048
166 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
167 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
168 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
169 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
170 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
171 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
172 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
173 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
174 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
175 #define CONFIG_SYS_DDR_MODE_1 0x00441221
176 #define CONFIG_SYS_DDR_MODE_2 0x00000000
177 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
178 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
179 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
180 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
181 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
182 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
183 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
184 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
185 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
190 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
191 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
192 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
194 * Localbus cacheable (TBD)
195 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
197 * Localbus non-cacheable
198 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
199 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
200 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
201 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
202 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
203 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
207 * Local Bus Definitions
209 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
210 #ifdef CONFIG_PHYS_64BIT
211 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
213 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
216 #define CONFIG_FLASH_BR_PRELIM \
217 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
218 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
221 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
222 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
224 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
225 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
228 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
229 #define CONFIG_SYS_FLASH_QUIET_TEST
230 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
232 #define CONFIG_SYS_MAX_FLASH_BANKS 1
233 #define CONFIG_SYS_MAX_FLASH_SECT 1024
235 #ifndef CONFIG_SYS_MONITOR_BASE
236 #ifdef CONFIG_SPL_BUILD
237 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
239 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
243 #define CONFIG_FLASH_CFI_DRIVER
244 #define CONFIG_SYS_FLASH_CFI
245 #define CONFIG_SYS_FLASH_EMPTY_INFO
248 #if defined(CONFIG_NAND_FSL_ELBC)
249 #define CONFIG_SYS_NAND_BASE 0xff800000
250 #ifdef CONFIG_PHYS_64BIT
251 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
253 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
256 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
257 #define CONFIG_SYS_MAX_NAND_DEVICE 1
258 #define CONFIG_CMD_NAND 1
259 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
260 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
262 /* NAND flash config */
263 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
264 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
265 | BR_PS_8 /* Port Size = 8 bit */ \
266 | BR_MS_FCM /* MSEL = FCM */ \
268 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
269 | OR_FCM_PGS /* Large Page*/ \
277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
280 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
281 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
284 #endif /* CONFIG_NAND_FSL_ELBC */
286 #define CONFIG_BOARD_EARLY_INIT_F
287 #define CONFIG_BOARD_EARLY_INIT_R
288 #define CONFIG_MISC_INIT_R
289 #define CONFIG_HWCONFIG
291 #define CONFIG_FSL_NGPIXIS
292 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
293 #ifdef CONFIG_PHYS_64BIT
294 #define PIXIS_BASE_PHYS 0xfffdf0000ull
296 #define PIXIS_BASE_PHYS PIXIS_BASE
299 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
300 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
302 #define PIXIS_LBMAP_SWITCH 7
303 #define PIXIS_LBMAP_MASK 0xF0
304 #define PIXIS_LBMAP_ALTBANK 0x20
305 #define PIXIS_SPD 0x07
306 #define PIXIS_SPD_SYSCLK_MASK 0x07
307 #define PIXIS_ELBC_SPI_MASK 0xc0
308 #define PIXIS_SPI 0x80
310 #define CONFIG_SYS_INIT_RAM_LOCK
311 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
312 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
314 #define CONFIG_SYS_GBL_DATA_OFFSET \
315 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
316 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
318 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
319 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
322 * Config the L2 Cache as L2 SRAM
324 #if defined(CONFIG_SPL_BUILD)
325 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
326 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
327 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
328 #define CONFIG_SYS_L2_SIZE (256 << 10)
329 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
330 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
331 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
332 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
333 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
334 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
335 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
336 #elif defined(CONFIG_NAND)
337 #ifdef CONFIG_TPL_BUILD
338 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
339 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
340 #define CONFIG_SYS_L2_SIZE (256 << 10)
341 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
342 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
343 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
344 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
345 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
346 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
348 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
349 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
350 #define CONFIG_SYS_L2_SIZE (256 << 10)
351 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
352 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
353 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
361 #define CONFIG_CONS_INDEX 1
362 #define CONFIG_SYS_NS16550_SERIAL
363 #define CONFIG_SYS_NS16550_REG_SIZE 1
364 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
365 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
366 #define CONFIG_NS16550_MIN_FUNCTIONS
369 #define CONFIG_SYS_BAUDRATE_TABLE \
370 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
372 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
373 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
377 #ifdef CONFIG_FSL_DIU_FB
378 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
379 #define CONFIG_CMD_BMP
380 #define CONFIG_VIDEO_LOGO
381 #define CONFIG_VIDEO_BMP_LOGO
382 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
384 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
385 * disable empty flash sector detection, which is I/O-intensive.
387 #undef CONFIG_SYS_FLASH_EMPTY_INFO
390 #ifndef CONFIG_FSL_DIU_FB
394 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
395 #define CONFIG_BIOSEMU
396 #define CONFIG_ATI_RADEON_FB
397 #define CONFIG_VIDEO_LOGO
398 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
402 #define CONFIG_SYS_I2C
403 #define CONFIG_SYS_I2C_FSL
404 #define CONFIG_SYS_FSL_I2C_SPEED 400000
405 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
406 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
407 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
408 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
409 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
410 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
415 #define CONFIG_ID_EEPROM
416 #define CONFIG_SYS_I2C_EEPROM_NXID
417 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
418 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
419 #define CONFIG_SYS_EEPROM_BUS_NUM 1
422 * eSPI - Enhanced SPI
425 #define CONFIG_HARD_SPI
427 #define CONFIG_SF_DEFAULT_SPEED 10000000
428 #define CONFIG_SF_DEFAULT_MODE 0
432 * Memory space is mapped 1-1, but I/O space must start from 0.
435 /* controller 1, Slot 2, tgtid 1, Base address a000 */
436 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
437 #ifdef CONFIG_PHYS_64BIT
438 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
439 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
441 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
442 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
444 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
445 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
446 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
450 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
452 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
454 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
455 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
456 #ifdef CONFIG_PHYS_64BIT
457 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
458 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
460 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
461 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
463 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
464 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
465 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
466 #ifdef CONFIG_PHYS_64BIT
467 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
469 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
471 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
473 /* controller 3, Slot 1, tgtid 3, Base address b000 */
474 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
475 #ifdef CONFIG_PHYS_64BIT
476 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
477 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
479 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
480 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
482 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
483 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
484 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
485 #ifdef CONFIG_PHYS_64BIT
486 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
488 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
490 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
493 #define CONFIG_PCI_INDIRECT_BRIDGE
494 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
498 #define CONFIG_LIBATA
499 #define CONFIG_FSL_SATA
500 #define CONFIG_FSL_SATA_V2
502 #define CONFIG_SYS_SATA_MAX_DEVICE 2
504 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
505 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
507 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
508 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
510 #ifdef CONFIG_FSL_SATA
512 #define CONFIG_CMD_SATA
513 #define CONFIG_DOS_PARTITION
518 #define CONFIG_FSL_ESDHC
519 #define CONFIG_GENERIC_MMC
520 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
523 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
524 #define CONFIG_DOS_PARTITION
527 #define CONFIG_TSEC_ENET
528 #ifdef CONFIG_TSEC_ENET
530 #define CONFIG_TSECV2
532 #define CONFIG_MII /* MII PHY management */
533 #define CONFIG_TSEC1 1
534 #define CONFIG_TSEC1_NAME "eTSEC1"
535 #define CONFIG_TSEC2 1
536 #define CONFIG_TSEC2_NAME "eTSEC2"
538 #define TSEC1_PHY_ADDR 1
539 #define TSEC2_PHY_ADDR 2
541 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
542 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
544 #define TSEC1_PHYIDX 0
545 #define TSEC2_PHYIDX 0
547 #define CONFIG_ETHPRIME "eTSEC1"
549 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
553 * Dynamic MTD Partition support with mtdparts
555 #define CONFIG_MTD_DEVICE
556 #define CONFIG_MTD_PARTITIONS
557 #define CONFIG_CMD_MTDPARTS
558 #define CONFIG_FLASH_CFI_MTD
559 #ifdef CONFIG_PHYS_64BIT
560 #define MTDIDS_DEFAULT "nor0=fe8000000.nor"
561 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
562 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
563 "512k(dtb),768k(u-boot)"
565 #define MTDIDS_DEFAULT "nor0=e8000000.nor"
566 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
567 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
568 "512k(dtb),768k(u-boot)"
574 #ifdef CONFIG_SPIFLASH
575 #define CONFIG_ENV_IS_IN_SPI_FLASH
576 #define CONFIG_ENV_SPI_BUS 0
577 #define CONFIG_ENV_SPI_CS 0
578 #define CONFIG_ENV_SPI_MAX_HZ 10000000
579 #define CONFIG_ENV_SPI_MODE 0
580 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
581 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
582 #define CONFIG_ENV_SECT_SIZE 0x10000
583 #elif defined(CONFIG_SDCARD)
584 #define CONFIG_ENV_IS_IN_MMC
585 #define CONFIG_FSL_FIXED_MMC_LOCATION
586 #define CONFIG_ENV_SIZE 0x2000
587 #define CONFIG_SYS_MMC_ENV_DEV 0
588 #elif defined(CONFIG_NAND)
589 #ifdef CONFIG_TPL_BUILD
590 #define CONFIG_ENV_SIZE 0x2000
591 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
593 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
595 #define CONFIG_ENV_IS_IN_NAND
596 #define CONFIG_ENV_OFFSET (1024 * 1024)
597 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
598 #elif defined(CONFIG_SYS_RAMBOOT)
599 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
600 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
601 #define CONFIG_ENV_SIZE 0x2000
603 #define CONFIG_ENV_IS_IN_FLASH
604 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
605 #define CONFIG_ENV_SIZE 0x2000
606 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
609 #define CONFIG_LOADS_ECHO
610 #define CONFIG_SYS_LOADS_BAUD_CHANGE
613 * Command line configuration.
615 #define CONFIG_CMD_ERRATA
616 #define CONFIG_CMD_IRQ
617 #define CONFIG_CMD_REGINFO
620 #define CONFIG_CMD_PCI
626 #define CONFIG_HAS_FSL_DR_USB
627 #ifdef CONFIG_HAS_FSL_DR_USB
628 #define CONFIG_USB_EHCI
630 #ifdef CONFIG_USB_EHCI
631 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
632 #define CONFIG_USB_EHCI_FSL
637 * Miscellaneous configurable options
639 #define CONFIG_SYS_LONGHELP /* undef to save memory */
640 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
641 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
642 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
643 #ifdef CONFIG_CMD_KGDB
644 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
646 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
648 /* Print Buffer Size */
649 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
650 #define CONFIG_SYS_MAXARGS 16
651 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
654 * For booting Linux, the board info and command line data
655 * have to be in the first 64 MB of memory, since this is
656 * the maximum mapped by the Linux kernel during initialization.
658 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
659 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
661 #ifdef CONFIG_CMD_KGDB
662 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
666 * Environment Configuration
669 #define CONFIG_HOSTNAME p1022ds
670 #define CONFIG_ROOTPATH "/opt/nfsroot"
671 #define CONFIG_BOOTFILE "uImage"
672 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
674 #define CONFIG_LOADADDR 1000000
677 #define CONFIG_BAUDRATE 115200
679 #define CONFIG_EXTRA_ENV_SETTINGS \
681 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
682 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
683 "tftpflash=tftpboot $loadaddr $uboot && " \
684 "protect off $ubootaddr +$filesize && " \
685 "erase $ubootaddr +$filesize && " \
686 "cp.b $loadaddr $ubootaddr $filesize && " \
687 "protect on $ubootaddr +$filesize && " \
688 "cmp.b $loadaddr $ubootaddr $filesize\0" \
689 "consoledev=ttyS0\0" \
690 "ramdiskaddr=2000000\0" \
691 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
692 "fdtaddr=1e00000\0" \
693 "fdtfile=p1022ds.dtb\0" \
695 "hwconfig=esdhc;audclk:12\0"
697 #define CONFIG_HDBOOT \
698 "setenv bootargs root=/dev/$bdev rw " \
699 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
700 "tftp $loadaddr $bootfile;" \
701 "tftp $fdtaddr $fdtfile;" \
702 "bootm $loadaddr - $fdtaddr"
704 #define CONFIG_NFSBOOTCOMMAND \
705 "setenv bootargs root=/dev/nfs rw " \
706 "nfsroot=$serverip:$rootpath " \
707 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
708 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
709 "tftp $loadaddr $bootfile;" \
710 "tftp $fdtaddr $fdtfile;" \
711 "bootm $loadaddr - $fdtaddr"
713 #define CONFIG_RAMBOOTCOMMAND \
714 "setenv bootargs root=/dev/ram rw " \
715 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
716 "tftp $ramdiskaddr $ramdiskfile;" \
717 "tftp $loadaddr $bootfile;" \
718 "tftp $fdtaddr $fdtfile;" \
719 "bootm $loadaddr $ramdiskaddr $fdtaddr"
721 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND