2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "../board/freescale/common/ics307_clk.h"
15 #define CONFIG_SPL_MMC_MINIMAL
16 #define CONFIG_SPL_FLUSH_IMAGE
17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
18 #define CONFIG_SYS_TEXT_BASE 0x11001000
19 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
20 #define CONFIG_SPL_PAD_TO 0x20000
21 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
22 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
25 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
27 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
28 #define CONFIG_SPL_MMC_BOOT
29 #ifdef CONFIG_SPL_BUILD
30 #define CONFIG_SPL_COMMON_INIT_DDR
34 #ifdef CONFIG_SPIFLASH
35 #define CONFIG_SPL_SPI_FLASH_MINIMAL
36 #define CONFIG_SPL_FLUSH_IMAGE
37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
38 #define CONFIG_SYS_TEXT_BASE 0x11001000
39 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
40 #define CONFIG_SPL_PAD_TO 0x20000
41 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
48 #define CONFIG_SPL_SPI_BOOT
49 #ifdef CONFIG_SPL_BUILD
50 #define CONFIG_SPL_COMMON_INIT_DDR
54 #define CONFIG_NAND_FSL_ELBC
55 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
56 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
59 #ifdef CONFIG_TPL_BUILD
60 #define CONFIG_SPL_NAND_BOOT
61 #define CONFIG_SPL_FLUSH_IMAGE
62 #define CONFIG_SPL_NAND_INIT
63 #define CONFIG_SPL_COMMON_INIT_DDR
64 #define CONFIG_SPL_MAX_SIZE (128 << 10)
65 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
67 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
68 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
69 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
70 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
71 #elif defined(CONFIG_SPL_BUILD)
72 #define CONFIG_SPL_INIT_MINIMAL
73 #define CONFIG_SPL_FLUSH_IMAGE
74 #define CONFIG_SPL_TEXT_BASE 0xff800000
75 #define CONFIG_SPL_MAX_SIZE 4096
76 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
77 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
78 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
79 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
81 #define CONFIG_SPL_PAD_TO 0x20000
82 #define CONFIG_TPL_PAD_TO 0x20000
83 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
84 #define CONFIG_SYS_TEXT_BASE 0x11001000
85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
88 /* High Level Configuration Options */
89 #define CONFIG_MP /* support multiple processors */
91 #ifndef CONFIG_SYS_TEXT_BASE
92 #define CONFIG_SYS_TEXT_BASE 0xeff40000
95 #ifndef CONFIG_RESET_VECTOR_ADDRESS
96 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
99 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
100 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
101 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
102 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
103 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
104 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
105 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
107 #define CONFIG_ENABLE_36BIT_PHYS
109 #ifdef CONFIG_PHYS_64BIT
110 #define CONFIG_ADDR_MAP
111 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
114 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
115 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
116 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
119 * These can be toggled for performance analysis, otherwise use default.
121 #define CONFIG_L2_CACHE
124 #define CONFIG_SYS_MEMTEST_START 0x00000000
125 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
127 #define CONFIG_SYS_CCSRBAR 0xffe00000
128 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
130 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
132 #ifdef CONFIG_SPL_BUILD
133 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
137 #define CONFIG_DDR_SPD
138 #define CONFIG_VERY_BIG_RAM
139 #define CONFIG_SYS_FSL_DDR3
141 #ifdef CONFIG_DDR_ECC
142 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
143 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
149 #define CONFIG_NUM_DDR_CONTROLLERS 1
150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
151 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
153 /* I2C addresses of SPD EEPROMs */
154 #define CONFIG_SYS_SPD_BUS_NUM 1
155 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
157 /* These are used when DDR doesn't use SPD. */
158 #define CONFIG_SYS_SDRAM_SIZE 2048
159 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
160 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
161 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
162 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
163 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
164 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
165 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
166 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
167 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
168 #define CONFIG_SYS_DDR_MODE_1 0x00441221
169 #define CONFIG_SYS_DDR_MODE_2 0x00000000
170 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
171 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
172 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
173 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
174 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
175 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
176 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
177 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
178 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
183 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
184 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
185 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
187 * Localbus cacheable (TBD)
188 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
190 * Localbus non-cacheable
191 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
192 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
193 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
194 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
195 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
196 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
200 * Local Bus Definitions
202 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
203 #ifdef CONFIG_PHYS_64BIT
204 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
206 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
209 #define CONFIG_FLASH_BR_PRELIM \
210 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
211 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
214 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
215 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
217 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
218 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
222 #define CONFIG_SYS_FLASH_QUIET_TEST
223 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
225 #define CONFIG_SYS_MAX_FLASH_BANKS 1
226 #define CONFIG_SYS_MAX_FLASH_SECT 1024
228 #ifndef CONFIG_SYS_MONITOR_BASE
229 #ifdef CONFIG_SPL_BUILD
230 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
236 #define CONFIG_FLASH_CFI_DRIVER
237 #define CONFIG_SYS_FLASH_CFI
238 #define CONFIG_SYS_FLASH_EMPTY_INFO
241 #if defined(CONFIG_NAND_FSL_ELBC)
242 #define CONFIG_SYS_NAND_BASE 0xff800000
243 #ifdef CONFIG_PHYS_64BIT
244 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
246 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
249 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
250 #define CONFIG_SYS_MAX_NAND_DEVICE 1
251 #define CONFIG_CMD_NAND 1
252 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
253 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
255 /* NAND flash config */
256 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
257 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
258 | BR_PS_8 /* Port Size = 8 bit */ \
259 | BR_MS_FCM /* MSEL = FCM */ \
261 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
262 | OR_FCM_PGS /* Large Page*/ \
270 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
271 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
273 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
274 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
277 #endif /* CONFIG_NAND_FSL_ELBC */
279 #define CONFIG_BOARD_EARLY_INIT_F
280 #define CONFIG_BOARD_EARLY_INIT_R
281 #define CONFIG_MISC_INIT_R
282 #define CONFIG_HWCONFIG
284 #define CONFIG_FSL_NGPIXIS
285 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
286 #ifdef CONFIG_PHYS_64BIT
287 #define PIXIS_BASE_PHYS 0xfffdf0000ull
289 #define PIXIS_BASE_PHYS PIXIS_BASE
292 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
293 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
295 #define PIXIS_LBMAP_SWITCH 7
296 #define PIXIS_LBMAP_MASK 0xF0
297 #define PIXIS_LBMAP_ALTBANK 0x20
298 #define PIXIS_SPD 0x07
299 #define PIXIS_SPD_SYSCLK_MASK 0x07
300 #define PIXIS_ELBC_SPI_MASK 0xc0
301 #define PIXIS_SPI 0x80
303 #define CONFIG_SYS_INIT_RAM_LOCK
304 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
305 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
307 #define CONFIG_SYS_GBL_DATA_OFFSET \
308 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
309 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
311 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
312 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
315 * Config the L2 Cache as L2 SRAM
317 #if defined(CONFIG_SPL_BUILD)
318 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
319 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
320 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
321 #define CONFIG_SYS_L2_SIZE (256 << 10)
322 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
323 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
324 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
325 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
326 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
327 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
328 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
329 #elif defined(CONFIG_NAND)
330 #ifdef CONFIG_TPL_BUILD
331 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
332 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
333 #define CONFIG_SYS_L2_SIZE (256 << 10)
334 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
335 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
336 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
337 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
338 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
339 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
341 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
342 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
343 #define CONFIG_SYS_L2_SIZE (256 << 10)
344 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
345 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
346 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
354 #define CONFIG_CONS_INDEX 1
355 #define CONFIG_SYS_NS16550_SERIAL
356 #define CONFIG_SYS_NS16550_REG_SIZE 1
357 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
358 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
359 #define CONFIG_NS16550_MIN_FUNCTIONS
362 #define CONFIG_SYS_BAUDRATE_TABLE \
363 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
365 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
366 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
370 #ifdef CONFIG_FSL_DIU_FB
371 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
372 #define CONFIG_CMD_BMP
373 #define CONFIG_VIDEO_LOGO
374 #define CONFIG_VIDEO_BMP_LOGO
375 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
377 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
378 * disable empty flash sector detection, which is I/O-intensive.
380 #undef CONFIG_SYS_FLASH_EMPTY_INFO
383 #ifndef CONFIG_FSL_DIU_FB
387 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
388 #define CONFIG_BIOSEMU
389 #define CONFIG_ATI_RADEON_FB
390 #define CONFIG_VIDEO_LOGO
391 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
395 #define CONFIG_SYS_I2C
396 #define CONFIG_SYS_I2C_FSL
397 #define CONFIG_SYS_FSL_I2C_SPEED 400000
398 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
399 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
400 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
401 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
402 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
403 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
408 #define CONFIG_ID_EEPROM
409 #define CONFIG_SYS_I2C_EEPROM_NXID
410 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
411 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
412 #define CONFIG_SYS_EEPROM_BUS_NUM 1
415 * eSPI - Enhanced SPI
418 #define CONFIG_HARD_SPI
420 #define CONFIG_SF_DEFAULT_SPEED 10000000
421 #define CONFIG_SF_DEFAULT_MODE 0
425 * Memory space is mapped 1-1, but I/O space must start from 0.
428 /* controller 1, Slot 2, tgtid 1, Base address a000 */
429 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
430 #ifdef CONFIG_PHYS_64BIT
431 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
432 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
434 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
435 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
437 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
438 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
439 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
440 #ifdef CONFIG_PHYS_64BIT
441 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
443 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
445 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
447 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
448 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
449 #ifdef CONFIG_PHYS_64BIT
450 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
451 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
453 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
454 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
456 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
457 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
458 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
459 #ifdef CONFIG_PHYS_64BIT
460 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
462 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
464 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
466 /* controller 3, Slot 1, tgtid 3, Base address b000 */
467 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
468 #ifdef CONFIG_PHYS_64BIT
469 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
470 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
472 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
473 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
475 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
476 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
477 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
478 #ifdef CONFIG_PHYS_64BIT
479 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
481 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
483 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
486 #define CONFIG_PCI_INDIRECT_BRIDGE
487 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
491 #define CONFIG_LIBATA
492 #define CONFIG_FSL_SATA
493 #define CONFIG_FSL_SATA_V2
495 #define CONFIG_SYS_SATA_MAX_DEVICE 2
497 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
498 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
500 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
501 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
503 #ifdef CONFIG_FSL_SATA
505 #define CONFIG_CMD_SATA
506 #define CONFIG_DOS_PARTITION
510 #define CONFIG_FSL_ESDHC
511 #define CONFIG_GENERIC_MMC
512 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
515 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
516 #define CONFIG_DOS_PARTITION
519 #define CONFIG_TSEC_ENET
520 #ifdef CONFIG_TSEC_ENET
522 #define CONFIG_TSECV2
524 #define CONFIG_MII /* MII PHY management */
525 #define CONFIG_TSEC1 1
526 #define CONFIG_TSEC1_NAME "eTSEC1"
527 #define CONFIG_TSEC2 1
528 #define CONFIG_TSEC2_NAME "eTSEC2"
530 #define TSEC1_PHY_ADDR 1
531 #define TSEC2_PHY_ADDR 2
533 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
534 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
536 #define TSEC1_PHYIDX 0
537 #define TSEC2_PHYIDX 0
539 #define CONFIG_ETHPRIME "eTSEC1"
541 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
545 * Dynamic MTD Partition support with mtdparts
547 #define CONFIG_MTD_DEVICE
548 #define CONFIG_MTD_PARTITIONS
549 #define CONFIG_CMD_MTDPARTS
550 #define CONFIG_FLASH_CFI_MTD
551 #ifdef CONFIG_PHYS_64BIT
552 #define MTDIDS_DEFAULT "nor0=fe8000000.nor"
553 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
554 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
555 "512k(dtb),768k(u-boot)"
557 #define MTDIDS_DEFAULT "nor0=e8000000.nor"
558 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
559 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
560 "512k(dtb),768k(u-boot)"
566 #ifdef CONFIG_SPIFLASH
567 #define CONFIG_ENV_IS_IN_SPI_FLASH
568 #define CONFIG_ENV_SPI_BUS 0
569 #define CONFIG_ENV_SPI_CS 0
570 #define CONFIG_ENV_SPI_MAX_HZ 10000000
571 #define CONFIG_ENV_SPI_MODE 0
572 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
573 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
574 #define CONFIG_ENV_SECT_SIZE 0x10000
575 #elif defined(CONFIG_SDCARD)
576 #define CONFIG_ENV_IS_IN_MMC
577 #define CONFIG_FSL_FIXED_MMC_LOCATION
578 #define CONFIG_ENV_SIZE 0x2000
579 #define CONFIG_SYS_MMC_ENV_DEV 0
580 #elif defined(CONFIG_NAND)
581 #ifdef CONFIG_TPL_BUILD
582 #define CONFIG_ENV_SIZE 0x2000
583 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
585 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
587 #define CONFIG_ENV_IS_IN_NAND
588 #define CONFIG_ENV_OFFSET (1024 * 1024)
589 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
590 #elif defined(CONFIG_SYS_RAMBOOT)
591 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
592 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
593 #define CONFIG_ENV_SIZE 0x2000
595 #define CONFIG_ENV_IS_IN_FLASH
596 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
597 #define CONFIG_ENV_SIZE 0x2000
598 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
601 #define CONFIG_LOADS_ECHO
602 #define CONFIG_SYS_LOADS_BAUD_CHANGE
605 * Command line configuration.
607 #define CONFIG_CMD_ERRATA
608 #define CONFIG_CMD_IRQ
609 #define CONFIG_CMD_REGINFO
612 #define CONFIG_CMD_PCI
618 #define CONFIG_HAS_FSL_DR_USB
619 #ifdef CONFIG_HAS_FSL_DR_USB
620 #define CONFIG_USB_EHCI
622 #ifdef CONFIG_USB_EHCI
623 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
624 #define CONFIG_USB_EHCI_FSL
629 * Miscellaneous configurable options
631 #define CONFIG_SYS_LONGHELP /* undef to save memory */
632 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
633 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
634 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
635 #ifdef CONFIG_CMD_KGDB
636 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
638 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
640 /* Print Buffer Size */
641 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
642 #define CONFIG_SYS_MAXARGS 16
643 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
646 * For booting Linux, the board info and command line data
647 * have to be in the first 64 MB of memory, since this is
648 * the maximum mapped by the Linux kernel during initialization.
650 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
651 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
653 #ifdef CONFIG_CMD_KGDB
654 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
658 * Environment Configuration
661 #define CONFIG_HOSTNAME p1022ds
662 #define CONFIG_ROOTPATH "/opt/nfsroot"
663 #define CONFIG_BOOTFILE "uImage"
664 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
666 #define CONFIG_LOADADDR 1000000
669 #define CONFIG_BAUDRATE 115200
671 #define CONFIG_EXTRA_ENV_SETTINGS \
673 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
674 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
675 "tftpflash=tftpboot $loadaddr $uboot && " \
676 "protect off $ubootaddr +$filesize && " \
677 "erase $ubootaddr +$filesize && " \
678 "cp.b $loadaddr $ubootaddr $filesize && " \
679 "protect on $ubootaddr +$filesize && " \
680 "cmp.b $loadaddr $ubootaddr $filesize\0" \
681 "consoledev=ttyS0\0" \
682 "ramdiskaddr=2000000\0" \
683 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
684 "fdtaddr=1e00000\0" \
685 "fdtfile=p1022ds.dtb\0" \
687 "hwconfig=esdhc;audclk:12\0"
689 #define CONFIG_HDBOOT \
690 "setenv bootargs root=/dev/$bdev rw " \
691 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
692 "tftp $loadaddr $bootfile;" \
693 "tftp $fdtaddr $fdtfile;" \
694 "bootm $loadaddr - $fdtaddr"
696 #define CONFIG_NFSBOOTCOMMAND \
697 "setenv bootargs root=/dev/nfs rw " \
698 "nfsroot=$serverip:$rootpath " \
699 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
700 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
701 "tftp $loadaddr $bootfile;" \
702 "tftp $fdtaddr $fdtfile;" \
703 "bootm $loadaddr - $fdtaddr"
705 #define CONFIG_RAMBOOTCOMMAND \
706 "setenv bootargs root=/dev/ram rw " \
707 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
708 "tftp $ramdiskaddr $ramdiskfile;" \
709 "tftp $loadaddr $bootfile;" \
710 "tftp $fdtaddr $fdtfile;" \
711 "bootm $loadaddr $ramdiskaddr $fdtaddr"
713 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND