include/configs/P1022DS.h

   1 /*
   2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #ifdef CONFIG_36BIT
  17 #define CONFIG_PHYS_64BIT
  18 #endif
  19
  20 #ifdef CONFIG_SDCARD
  21 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  22 #define CONFIG_SPL_ENV_SUPPORT
  23 #define CONFIG_SPL_SERIAL_SUPPORT
  24 #define CONFIG_SPL_MMC_SUPPORT
  25 #define CONFIG_SPL_MMC_MINIMAL
  26 #define CONFIG_SPL_FLUSH_IMAGE
  27 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  28 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  29 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  30 #define CONFIG_SPL_I2C_SUPPORT
  31 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  32 #define CONFIG_SYS_TEXT_BASE            0x11001000
  33 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  34 #define CONFIG_SPL_PAD_TO               0x20000
  35 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  36 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  37 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  38 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  39 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
  40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  41 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  42 #define CONFIG_SPL_MMC_BOOT
  43 #ifdef CONFIG_SPL_BUILD
  44 #define CONFIG_SPL_COMMON_INIT_DDR
  45 #endif
  46 #endif
  47
  48 #ifdef CONFIG_SPIFLASH
  49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  50 #define CONFIG_SPL_ENV_SUPPORT
  51 #define CONFIG_SPL_SERIAL_SUPPORT
  52 #define CONFIG_SPL_SPI_SUPPORT
  53 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  54 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  55 #define CONFIG_SPL_FLUSH_IMAGE
  56 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  57 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  58 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  59 #define CONFIG_SPL_I2C_SUPPORT
  60 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  61 #define CONFIG_SYS_TEXT_BASE            0x11001000
  62 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  63 #define CONFIG_SPL_PAD_TO               0x20000
  64 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
  69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  70 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  71 #define CONFIG_SPL_SPI_BOOT
  72 #ifdef CONFIG_SPL_BUILD
  73 #define CONFIG_SPL_COMMON_INIT_DDR
  74 #endif
  75 #endif
  76
  77 #define CONFIG_NAND_FSL_ELBC
  78 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  79 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
  80
  81 #ifdef CONFIG_NAND
  82 #ifdef CONFIG_TPL_BUILD
  83 #define CONFIG_SPL_NAND_BOOT
  84 #define CONFIG_SPL_FLUSH_IMAGE
  85 #define CONFIG_SPL_ENV_SUPPORT
  86 #define CONFIG_SPL_NAND_INIT
  87 #define CONFIG_SPL_SERIAL_SUPPORT
  88 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  89 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  90 #define CONFIG_SPL_I2C_SUPPORT
  91 #define CONFIG_SPL_NAND_SUPPORT
  92 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  93 #define CONFIG_SPL_COMMON_INIT_DDR
  94 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  95 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  97 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  98 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  99 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 100 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 101 #elif defined(CONFIG_SPL_BUILD)
 102 #define CONFIG_SPL_INIT_MINIMAL
 103 #define CONFIG_SPL_SERIAL_SUPPORT
 104 #define CONFIG_SPL_NAND_SUPPORT
 105 #define CONFIG_SPL_FLUSH_IMAGE
 106 #define CONFIG_SPL_TEXT_BASE            0xff800000
 107 #define CONFIG_SPL_MAX_SIZE             4096
 108 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 109 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
 110 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
 111 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 112 #endif
 113 #define CONFIG_SPL_PAD_TO               0x20000
 114 #define CONFIG_TPL_PAD_TO               0x20000
 115 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 116 #define CONFIG_SYS_TEXT_BASE            0x11001000
 117 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 118 #endif
 119
 120 /* High Level Configuration Options */
 121 #define CONFIG_BOOKE                    /* BOOKE */
 122 #define CONFIG_E500                     /* BOOKE e500 family */
 123 #define CONFIG_P1022
 124 #define CONFIG_P1022DS
 125 #define CONFIG_MP                       /* support multiple processors */
 126
 127 #ifndef CONFIG_SYS_TEXT_BASE
 128 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 129 #endif
 130
 131 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 132 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 133 #endif
 134
 135 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
 136 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 137 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
 138 #define CONFIG_PCIE2                    /* PCIE controler 2 (slot 2) */
 139 #define CONFIG_PCIE3                    /* PCIE controler 3 (ULI bridge) */
 140 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 141 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 142 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 143
 144 #define CONFIG_ENABLE_36BIT_PHYS
 145
 146 #ifdef CONFIG_PHYS_64BIT
 147 #define CONFIG_ADDR_MAP
 148 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 149 #endif
 150
 151 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 152
 153 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 154 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 155 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
 156
 157 /*
 158  * These can be toggled for performance analysis, otherwise use default.
 159  */
 160 #define CONFIG_L2_CACHE
 161 #define CONFIG_BTB
 162
 163 #define CONFIG_SYS_MEMTEST_START        0x00000000
 164 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
 165
 166 #define CONFIG_SYS_CCSRBAR              0xffe00000
 167 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 168
 169 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 170        SPL code*/
 171 #ifdef CONFIG_SPL_BUILD
 172 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 173 #endif
 174
 175 /* DDR Setup */
 176 #define CONFIG_DDR_SPD
 177 #define CONFIG_VERY_BIG_RAM
 178 #define CONFIG_SYS_FSL_DDR3
 179
 180 #ifdef CONFIG_DDR_ECC
 181 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 182 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 183 #endif
 184
 185 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 186 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 187
 188 #define CONFIG_NUM_DDR_CONTROLLERS      1
 189 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 190 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 191
 192 /* I2C addresses of SPD EEPROMs */
 193 #define CONFIG_SYS_SPD_BUS_NUM          1
 194 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
 195
 196 /* These are used when DDR doesn't use SPD.  */
 197 #define CONFIG_SYS_SDRAM_SIZE           2048
 198 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 199 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 200 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 201 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 202 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
 203 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
 204 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 205 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
 206 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
 207 #define CONFIG_SYS_DDR_MODE_1           0x00441221
 208 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 209 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
 210 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 211 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
 212 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
 213 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
 214 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 215 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 216 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 217 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
 218
 219 /*
 220  * Memory map
 221  *
 222  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 223  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
 224  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
 225  *
 226  * Localbus cacheable (TBD)
 227  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 228  *
 229  * Localbus non-cacheable
 230  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 231  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 232  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
 233  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 234  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 235  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 236  */
 237
 238 /*
 239  * Local Bus Definitions
 240  */
 241 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
 242 #ifdef CONFIG_PHYS_64BIT
 243 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 244 #else
 245 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 246 #endif
 247
 248 #define CONFIG_FLASH_BR_PRELIM  \
 249         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 250 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 251
 252 #ifdef CONFIG_NAND
 253 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 254 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 255 #else
 256 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 257 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 258 #endif
 259
 260 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 261 #define CONFIG_SYS_FLASH_QUIET_TEST
 262 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 263
 264 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 265 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 266
 267 #ifndef CONFIG_SYS_MONITOR_BASE
 268 #ifdef CONFIG_SPL_BUILD
 269 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 270 #else
 271 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 272 #endif
 273 #endif
 274
 275 #define CONFIG_FLASH_CFI_DRIVER
 276 #define CONFIG_SYS_FLASH_CFI
 277 #define CONFIG_SYS_FLASH_EMPTY_INFO
 278
 279 /* Nand Flash */
 280 #if defined(CONFIG_NAND_FSL_ELBC)
 281 #define CONFIG_SYS_NAND_BASE            0xff800000
 282 #ifdef CONFIG_PHYS_64BIT
 283 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 284 #else
 285 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 286 #endif
 287
 288 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 289 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 290 #define CONFIG_CMD_NAND                 1
 291 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 292 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 293
 294 /* NAND flash config */
 295 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 296                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 297                                | BR_PS_8               /* Port Size = 8 bit */ \
 298                                | BR_MS_FCM             /* MSEL = FCM */ \
 299                                | BR_V)                 /* valid */
 300 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
 301                                | OR_FCM_PGS            /* Large Page*/ \
 302                                | OR_FCM_CSCT \
 303                                | OR_FCM_CST \
 304                                | OR_FCM_CHT \
 305                                | OR_FCM_SCY_1 \
 306                                | OR_FCM_TRLX \
 307                                | OR_FCM_EHTR)
 308 #ifdef CONFIG_NAND
 309 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 310 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 311 #else
 312 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 313 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 314 #endif
 315
 316 #endif /* CONFIG_NAND_FSL_ELBC */
 317
 318 #define CONFIG_BOARD_EARLY_INIT_F
 319 #define CONFIG_BOARD_EARLY_INIT_R
 320 #define CONFIG_MISC_INIT_R
 321 #define CONFIG_HWCONFIG
 322
 323 #define CONFIG_FSL_NGPIXIS
 324 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 325 #ifdef CONFIG_PHYS_64BIT
 326 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 327 #else
 328 #define PIXIS_BASE_PHYS         PIXIS_BASE
 329 #endif
 330
 331 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 332 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 333
 334 #define PIXIS_LBMAP_SWITCH      7
 335 #define PIXIS_LBMAP_MASK        0xF0
 336 #define PIXIS_LBMAP_ALTBANK     0x20
 337 #define PIXIS_SPD               0x07
 338 #define PIXIS_SPD_SYSCLK_MASK   0x07
 339 #define PIXIS_ELBC_SPI_MASK     0xc0
 340 #define PIXIS_SPI               0x80
 341
 342 #define CONFIG_SYS_INIT_RAM_LOCK
 343 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 344 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
 345
 346 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 347         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 348 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 349
 350 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 351 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 352
 353 /*
 354  * Config the L2 Cache as L2 SRAM
 355 */
 356 #if defined(CONFIG_SPL_BUILD)
 357 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 358 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
 359 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 360 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 361 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 362 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 363 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 364 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 365 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 366 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 367 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 368 #elif defined(CONFIG_NAND)
 369 #ifdef CONFIG_TPL_BUILD
 370 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 371 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 372 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 373 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 374 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 375 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 376 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 377 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 378 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 379 #else
 380 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 381 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 382 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 383 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 384 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 385 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 386 #endif
 387 #endif
 388 #endif
 389
 390 /*
 391  * Serial Port
 392  */
 393 #define CONFIG_CONS_INDEX               1
 394 #define CONFIG_SYS_NS16550_SERIAL
 395 #define CONFIG_SYS_NS16550_REG_SIZE     1
 396 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 397 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 398 #define CONFIG_NS16550_MIN_FUNCTIONS
 399 #endif
 400
 401 #define CONFIG_SYS_BAUDRATE_TABLE       \
 402         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 403
 404 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 405 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 406
 407 /* Video */
 408
 409 #ifdef CONFIG_FSL_DIU_FB
 410 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 411 #define CONFIG_VIDEO
 412 #define CONFIG_CMD_BMP
 413 #define CONFIG_CFB_CONSOLE
 414 #define CONFIG_VIDEO_SW_CURSOR
 415 #define CONFIG_VGA_AS_SINGLE_DEVICE
 416 #define CONFIG_VIDEO_LOGO
 417 #define CONFIG_VIDEO_BMP_LOGO
 418 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 419 /*
 420  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 421  * disable empty flash sector detection, which is I/O-intensive.
 422  */
 423 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 424 #endif
 425
 426 #ifndef CONFIG_FSL_DIU_FB
 427 #endif
 428
 429 #ifdef CONFIG_ATI
 430 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 431 #define CONFIG_VIDEO
 432 #define CONFIG_BIOSEMU
 433 #define CONFIG_VIDEO_SW_CURSOR
 434 #define CONFIG_ATI_RADEON_FB
 435 #define CONFIG_VIDEO_LOGO
 436 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 437 #define CONFIG_CFB_CONSOLE
 438 #define CONFIG_VGA_AS_SINGLE_DEVICE
 439 #endif
 440
 441 /* I2C */
 442 #define CONFIG_SYS_I2C
 443 #define CONFIG_SYS_I2C_FSL
 444 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 445 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 446 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 447 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 448 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 449 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 450 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 451
 452 /*
 453  * I2C2 EEPROM
 454  */
 455 #define CONFIG_ID_EEPROM
 456 #define CONFIG_SYS_I2C_EEPROM_NXID
 457 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 458 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 459 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 460
 461 /*
 462  * eSPI - Enhanced SPI
 463  */
 464
 465 #define CONFIG_HARD_SPI
 466
 467 #define CONFIG_SF_DEFAULT_SPEED         10000000
 468 #define CONFIG_SF_DEFAULT_MODE          0
 469
 470 /*
 471  * General PCI
 472  * Memory space is mapped 1-1, but I/O space must start from 0.
 473  */
 474
 475 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 476 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 477 #ifdef CONFIG_PHYS_64BIT
 478 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 479 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 480 #else
 481 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 482 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 483 #endif
 484 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 485 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 486 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 487 #ifdef CONFIG_PHYS_64BIT
 488 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 489 #else
 490 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 491 #endif
 492 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 493
 494 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 495 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 496 #ifdef CONFIG_PHYS_64BIT
 497 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 498 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 499 #else
 500 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 501 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 502 #endif
 503 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 504 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 505 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 506 #ifdef CONFIG_PHYS_64BIT
 507 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 508 #else
 509 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 510 #endif
 511 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 512
 513 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 514 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 515 #ifdef CONFIG_PHYS_64BIT
 516 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 517 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 518 #else
 519 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 520 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 521 #endif
 522 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 523 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 524 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 525 #ifdef CONFIG_PHYS_64BIT
 526 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 527 #else
 528 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 529 #endif
 530 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 531
 532 #ifdef CONFIG_PCI
 533 #define CONFIG_PCI_INDIRECT_BRIDGE
 534 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 535 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 536 #endif
 537
 538 /* SATA */
 539 #define CONFIG_LIBATA
 540 #define CONFIG_FSL_SATA
 541 #define CONFIG_FSL_SATA_V2
 542
 543 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 544 #define CONFIG_SATA1
 545 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 546 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 547 #define CONFIG_SATA2
 548 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 549 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 550
 551 #ifdef CONFIG_FSL_SATA
 552 #define CONFIG_LBA48
 553 #define CONFIG_CMD_SATA
 554 #define CONFIG_DOS_PARTITION
 555 #endif
 556
 557 #define CONFIG_MMC
 558 #ifdef CONFIG_MMC
 559 #define CONFIG_FSL_ESDHC
 560 #define CONFIG_GENERIC_MMC
 561 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 562 #endif
 563
 564 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 565 #define CONFIG_DOS_PARTITION
 566 #endif
 567
 568 #define CONFIG_TSEC_ENET
 569 #ifdef CONFIG_TSEC_ENET
 570
 571 #define CONFIG_TSECV2
 572
 573 #define CONFIG_MII                      /* MII PHY management */
 574 #define CONFIG_TSEC1            1
 575 #define CONFIG_TSEC1_NAME       "eTSEC1"
 576 #define CONFIG_TSEC2            1
 577 #define CONFIG_TSEC2_NAME       "eTSEC2"
 578
 579 #define TSEC1_PHY_ADDR          1
 580 #define TSEC2_PHY_ADDR          2
 581
 582 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 583 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 584
 585 #define TSEC1_PHYIDX            0
 586 #define TSEC2_PHYIDX            0
 587
 588 #define CONFIG_ETHPRIME         "eTSEC1"
 589
 590 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 591 #endif
 592
 593 /*
 594  * Dynamic MTD Partition support with mtdparts
 595  */
 596 #define CONFIG_MTD_DEVICE
 597 #define CONFIG_MTD_PARTITIONS
 598 #define CONFIG_CMD_MTDPARTS
 599 #define CONFIG_FLASH_CFI_MTD
 600 #ifdef CONFIG_PHYS_64BIT
 601 #define MTDIDS_DEFAULT "nor0=fe8000000.nor"
 602 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
 603                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
 604                         "512k(dtb),768k(u-boot)"
 605 #else
 606 #define MTDIDS_DEFAULT "nor0=e8000000.nor"
 607 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
 608                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
 609                         "512k(dtb),768k(u-boot)"
 610 #endif
 611
 612 /*
 613  * Environment
 614  */
 615 #ifdef CONFIG_SPIFLASH
 616 #define CONFIG_ENV_IS_IN_SPI_FLASH
 617 #define CONFIG_ENV_SPI_BUS      0
 618 #define CONFIG_ENV_SPI_CS       0
 619 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 620 #define CONFIG_ENV_SPI_MODE     0
 621 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 622 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 623 #define CONFIG_ENV_SECT_SIZE    0x10000
 624 #elif defined(CONFIG_SDCARD)
 625 #define CONFIG_ENV_IS_IN_MMC
 626 #define CONFIG_FSL_FIXED_MMC_LOCATION
 627 #define CONFIG_ENV_SIZE         0x2000
 628 #define CONFIG_SYS_MMC_ENV_DEV  0
 629 #elif defined(CONFIG_NAND)
 630 #ifdef CONFIG_TPL_BUILD
 631 #define CONFIG_ENV_SIZE         0x2000
 632 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 633 #else
 634 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 635 #endif
 636 #define CONFIG_ENV_IS_IN_NAND
 637 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 638 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 639 #elif defined(CONFIG_SYS_RAMBOOT)
 640 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 641 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 642 #define CONFIG_ENV_SIZE         0x2000
 643 #else
 644 #define CONFIG_ENV_IS_IN_FLASH
 645 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 646 #define CONFIG_ENV_SIZE         0x2000
 647 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 648 #endif
 649
 650 #define CONFIG_LOADS_ECHO
 651 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 652
 653 /*
 654  * Command line configuration.
 655  */
 656 #define CONFIG_CMD_ERRATA
 657 #define CONFIG_CMD_IRQ
 658 #define CONFIG_CMD_REGINFO
 659
 660 #ifdef CONFIG_PCI
 661 #define CONFIG_CMD_PCI
 662 #endif
 663
 664 /*
 665  * USB
 666  */
 667 #define CONFIG_HAS_FSL_DR_USB
 668 #ifdef CONFIG_HAS_FSL_DR_USB
 669 #define CONFIG_USB_EHCI
 670
 671 #ifdef CONFIG_USB_EHCI
 672 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 673 #define CONFIG_USB_EHCI_FSL
 674 #define CONFIG_USB_STORAGE
 675 #endif
 676 #endif
 677
 678 /*
 679  * Miscellaneous configurable options
 680  */
 681 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 682 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 683 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 684 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 685 #ifdef CONFIG_CMD_KGDB
 686 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 687 #else
 688 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 689 #endif
 690 /* Print Buffer Size */
 691 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 692 #define CONFIG_SYS_MAXARGS      16
 693 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 694
 695 /*
 696  * For booting Linux, the board info and command line data
 697  * have to be in the first 64 MB of memory, since this is
 698  * the maximum mapped by the Linux kernel during initialization.
 699  */
 700 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 701 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 702
 703 #ifdef CONFIG_CMD_KGDB
 704 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 705 #endif
 706
 707 /*
 708  * Environment Configuration
 709  */
 710
 711 #define CONFIG_HOSTNAME         p1022ds
 712 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 713 #define CONFIG_BOOTFILE         "uImage"
 714 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 715
 716 #define CONFIG_LOADADDR         1000000
 717
 718 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 719
 720 #define CONFIG_BAUDRATE 115200
 721
 722 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 723         "netdev=eth0\0"                                         \
 724         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 725         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 726         "tftpflash=tftpboot $loadaddr $uboot && "               \
 727                 "protect off $ubootaddr +$filesize && "         \
 728                 "erase $ubootaddr +$filesize && "               \
 729                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 730                 "protect on $ubootaddr +$filesize && "          \
 731                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 732         "consoledev=ttyS0\0"                                    \
 733         "ramdiskaddr=2000000\0"                                 \
 734         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 735         "fdtaddr=c00000\0"                                      \
 736         "fdtfile=p1022ds.dtb\0"                                 \
 737         "bdev=sda3\0"                                           \
 738         "hwconfig=esdhc;audclk:12\0"
 739
 740 #define CONFIG_HDBOOT                                   \
 741         "setenv bootargs root=/dev/$bdev rw "           \
 742         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 743         "tftp $loadaddr $bootfile;"                     \
 744         "tftp $fdtaddr $fdtfile;"                       \
 745         "bootm $loadaddr - $fdtaddr"
 746
 747 #define CONFIG_NFSBOOTCOMMAND                                           \
 748         "setenv bootargs root=/dev/nfs rw "                             \
 749         "nfsroot=$serverip:$rootpath "                                  \
 750         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 751         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 752         "tftp $loadaddr $bootfile;"                                     \
 753         "tftp $fdtaddr $fdtfile;"                                       \
 754         "bootm $loadaddr - $fdtaddr"
 755
 756 #define CONFIG_RAMBOOTCOMMAND                                           \
 757         "setenv bootargs root=/dev/ram rw "                             \
 758         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 759         "tftp $ramdiskaddr $ramdiskfile;"                               \
 760         "tftp $loadaddr $bootfile;"                                     \
 761         "tftp $fdtaddr $fdtfile;"                                       \
 762         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 763
 764 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 765
 766 #endif