2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "../board/freescale/common/ics307_clk.h"
14 #define CONFIG_DISPLAY_BOARDINFO
17 #define CONFIG_SPL_MMC_MINIMAL
18 #define CONFIG_SPL_FLUSH_IMAGE
19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
20 #define CONFIG_FSL_LAW /* Use common FSL init code */
21 #define CONFIG_SYS_TEXT_BASE 0x11001000
22 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
23 #define CONFIG_SPL_PAD_TO 0x20000
24 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
25 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
28 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
31 #define CONFIG_SPL_MMC_BOOT
32 #ifdef CONFIG_SPL_BUILD
33 #define CONFIG_SPL_COMMON_INIT_DDR
37 #ifdef CONFIG_SPIFLASH
38 #define CONFIG_SPL_SPI_SUPPORT
39 #define CONFIG_SPL_SPI_FLASH_MINIMAL
40 #define CONFIG_SPL_FLUSH_IMAGE
41 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
42 #define CONFIG_FSL_LAW /* Use common FSL init code */
43 #define CONFIG_SYS_TEXT_BASE 0x11001000
44 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
45 #define CONFIG_SPL_PAD_TO 0x20000
46 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
51 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
53 #define CONFIG_SPL_SPI_BOOT
54 #ifdef CONFIG_SPL_BUILD
55 #define CONFIG_SPL_COMMON_INIT_DDR
59 #define CONFIG_NAND_FSL_ELBC
60 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
61 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
64 #ifdef CONFIG_TPL_BUILD
65 #define CONFIG_SPL_NAND_BOOT
66 #define CONFIG_SPL_FLUSH_IMAGE
67 #define CONFIG_SPL_NAND_INIT
68 #define CONFIG_SPL_COMMON_INIT_DDR
69 #define CONFIG_SPL_MAX_SIZE (128 << 10)
70 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
72 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
73 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
74 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
75 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
76 #elif defined(CONFIG_SPL_BUILD)
77 #define CONFIG_SPL_INIT_MINIMAL
78 #define CONFIG_SPL_FLUSH_IMAGE
79 #define CONFIG_SPL_TEXT_BASE 0xff800000
80 #define CONFIG_SPL_MAX_SIZE 4096
81 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
82 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
83 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
84 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
86 #define CONFIG_SPL_PAD_TO 0x20000
87 #define CONFIG_TPL_PAD_TO 0x20000
88 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
89 #define CONFIG_SYS_TEXT_BASE 0x11001000
90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
93 /* High Level Configuration Options */
94 #define CONFIG_BOOKE /* BOOKE */
95 #define CONFIG_E500 /* BOOKE e500 family */
97 #define CONFIG_P1022DS
98 #define CONFIG_MP /* support multiple processors */
100 #ifndef CONFIG_SYS_TEXT_BASE
101 #define CONFIG_SYS_TEXT_BASE 0xeff40000
104 #ifndef CONFIG_RESET_VECTOR_ADDRESS
105 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
108 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
109 #define CONFIG_PCI /* Enable PCI/PCIE */
110 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
111 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
112 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
113 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
114 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
115 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
117 #define CONFIG_ENABLE_36BIT_PHYS
119 #ifdef CONFIG_PHYS_64BIT
120 #define CONFIG_ADDR_MAP
121 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
124 #define CONFIG_FSL_LAW /* Use common FSL init code */
126 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
127 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
128 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
131 * These can be toggled for performance analysis, otherwise use default.
133 #define CONFIG_L2_CACHE
136 #define CONFIG_SYS_MEMTEST_START 0x00000000
137 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
139 #define CONFIG_SYS_CCSRBAR 0xffe00000
140 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
142 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
144 #ifdef CONFIG_SPL_BUILD
145 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
149 #define CONFIG_DDR_SPD
150 #define CONFIG_VERY_BIG_RAM
151 #define CONFIG_SYS_FSL_DDR3
153 #ifdef CONFIG_DDR_ECC
154 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
155 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
158 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
159 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
161 #define CONFIG_NUM_DDR_CONTROLLERS 1
162 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
163 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
165 /* I2C addresses of SPD EEPROMs */
166 #define CONFIG_SYS_SPD_BUS_NUM 1
167 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
169 /* These are used when DDR doesn't use SPD. */
170 #define CONFIG_SYS_SDRAM_SIZE 2048
171 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
172 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
173 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
174 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
175 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
176 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
177 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
178 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
179 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
180 #define CONFIG_SYS_DDR_MODE_1 0x00441221
181 #define CONFIG_SYS_DDR_MODE_2 0x00000000
182 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
183 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
184 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
185 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
186 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
187 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
188 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
189 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
190 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
195 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
196 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
197 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
199 * Localbus cacheable (TBD)
200 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
202 * Localbus non-cacheable
203 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
204 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
205 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
206 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
207 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
208 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
212 * Local Bus Definitions
214 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
215 #ifdef CONFIG_PHYS_64BIT
216 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
218 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
221 #define CONFIG_FLASH_BR_PRELIM \
222 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
223 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
226 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
227 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
229 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
230 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
233 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
234 #define CONFIG_SYS_FLASH_QUIET_TEST
235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
237 #define CONFIG_SYS_MAX_FLASH_BANKS 1
238 #define CONFIG_SYS_MAX_FLASH_SECT 1024
240 #ifndef CONFIG_SYS_MONITOR_BASE
241 #ifdef CONFIG_SPL_BUILD
242 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
244 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
248 #define CONFIG_FLASH_CFI_DRIVER
249 #define CONFIG_SYS_FLASH_CFI
250 #define CONFIG_SYS_FLASH_EMPTY_INFO
253 #if defined(CONFIG_NAND_FSL_ELBC)
254 #define CONFIG_SYS_NAND_BASE 0xff800000
255 #ifdef CONFIG_PHYS_64BIT
256 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
258 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
261 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
262 #define CONFIG_SYS_MAX_NAND_DEVICE 1
263 #define CONFIG_CMD_NAND 1
264 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
265 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
267 /* NAND flash config */
268 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
269 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
270 | BR_PS_8 /* Port Size = 8 bit */ \
271 | BR_MS_FCM /* MSEL = FCM */ \
273 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
274 | OR_FCM_PGS /* Large Page*/ \
282 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
283 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
285 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
286 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
289 #endif /* CONFIG_NAND_FSL_ELBC */
291 #define CONFIG_BOARD_EARLY_INIT_F
292 #define CONFIG_BOARD_EARLY_INIT_R
293 #define CONFIG_MISC_INIT_R
294 #define CONFIG_HWCONFIG
296 #define CONFIG_FSL_NGPIXIS
297 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
298 #ifdef CONFIG_PHYS_64BIT
299 #define PIXIS_BASE_PHYS 0xfffdf0000ull
301 #define PIXIS_BASE_PHYS PIXIS_BASE
304 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
305 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
307 #define PIXIS_LBMAP_SWITCH 7
308 #define PIXIS_LBMAP_MASK 0xF0
309 #define PIXIS_LBMAP_ALTBANK 0x20
310 #define PIXIS_SPD 0x07
311 #define PIXIS_SPD_SYSCLK_MASK 0x07
312 #define PIXIS_ELBC_SPI_MASK 0xc0
313 #define PIXIS_SPI 0x80
315 #define CONFIG_SYS_INIT_RAM_LOCK
316 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
317 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
319 #define CONFIG_SYS_GBL_DATA_OFFSET \
320 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
321 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
323 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
324 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
327 * Config the L2 Cache as L2 SRAM
329 #if defined(CONFIG_SPL_BUILD)
330 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
331 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
332 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
333 #define CONFIG_SYS_L2_SIZE (256 << 10)
334 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
335 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
336 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
337 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
338 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
339 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
340 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
341 #elif defined(CONFIG_NAND)
342 #ifdef CONFIG_TPL_BUILD
343 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
344 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
345 #define CONFIG_SYS_L2_SIZE (256 << 10)
346 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
347 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
348 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
349 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
350 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
351 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
353 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
354 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
355 #define CONFIG_SYS_L2_SIZE (256 << 10)
356 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
357 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
358 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
366 #define CONFIG_CONS_INDEX 1
367 #define CONFIG_SYS_NS16550_SERIAL
368 #define CONFIG_SYS_NS16550_REG_SIZE 1
369 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
370 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
371 #define CONFIG_NS16550_MIN_FUNCTIONS
374 #define CONFIG_SYS_BAUDRATE_TABLE \
375 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
377 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
378 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
382 #ifdef CONFIG_FSL_DIU_FB
383 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
385 #define CONFIG_CMD_BMP
386 #define CONFIG_CFB_CONSOLE
387 #define CONFIG_VIDEO_SW_CURSOR
388 #define CONFIG_VGA_AS_SINGLE_DEVICE
389 #define CONFIG_VIDEO_LOGO
390 #define CONFIG_VIDEO_BMP_LOGO
391 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
393 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
394 * disable empty flash sector detection, which is I/O-intensive.
396 #undef CONFIG_SYS_FLASH_EMPTY_INFO
399 #ifndef CONFIG_FSL_DIU_FB
403 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
405 #define CONFIG_BIOSEMU
406 #define CONFIG_VIDEO_SW_CURSOR
407 #define CONFIG_ATI_RADEON_FB
408 #define CONFIG_VIDEO_LOGO
409 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
410 #define CONFIG_CFB_CONSOLE
411 #define CONFIG_VGA_AS_SINGLE_DEVICE
415 #define CONFIG_SYS_I2C
416 #define CONFIG_SYS_I2C_FSL
417 #define CONFIG_SYS_FSL_I2C_SPEED 400000
418 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
419 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
420 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
421 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
422 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
423 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
428 #define CONFIG_ID_EEPROM
429 #define CONFIG_SYS_I2C_EEPROM_NXID
430 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
431 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
432 #define CONFIG_SYS_EEPROM_BUS_NUM 1
435 * eSPI - Enhanced SPI
438 #define CONFIG_HARD_SPI
440 #define CONFIG_SF_DEFAULT_SPEED 10000000
441 #define CONFIG_SF_DEFAULT_MODE 0
445 * Memory space is mapped 1-1, but I/O space must start from 0.
448 /* controller 1, Slot 2, tgtid 1, Base address a000 */
449 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
450 #ifdef CONFIG_PHYS_64BIT
451 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
452 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
454 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
455 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
457 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
458 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
459 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
460 #ifdef CONFIG_PHYS_64BIT
461 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
463 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
465 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
467 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
468 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
469 #ifdef CONFIG_PHYS_64BIT
470 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
471 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
473 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
474 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
476 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
477 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
478 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
479 #ifdef CONFIG_PHYS_64BIT
480 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
482 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
484 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
486 /* controller 3, Slot 1, tgtid 3, Base address b000 */
487 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
488 #ifdef CONFIG_PHYS_64BIT
489 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
490 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
492 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
493 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
495 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
496 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
497 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
498 #ifdef CONFIG_PHYS_64BIT
499 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
501 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
503 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
506 #define CONFIG_PCI_INDIRECT_BRIDGE
507 #define CONFIG_PCI_PNP /* do pci plug-and-play */
508 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
512 #define CONFIG_LIBATA
513 #define CONFIG_FSL_SATA
514 #define CONFIG_FSL_SATA_V2
516 #define CONFIG_SYS_SATA_MAX_DEVICE 2
518 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
519 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
521 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
522 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
524 #ifdef CONFIG_FSL_SATA
526 #define CONFIG_CMD_SATA
527 #define CONFIG_DOS_PARTITION
532 #define CONFIG_FSL_ESDHC
533 #define CONFIG_GENERIC_MMC
534 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
537 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
538 #define CONFIG_DOS_PARTITION
541 #define CONFIG_TSEC_ENET
542 #ifdef CONFIG_TSEC_ENET
544 #define CONFIG_TSECV2
546 #define CONFIG_MII /* MII PHY management */
547 #define CONFIG_TSEC1 1
548 #define CONFIG_TSEC1_NAME "eTSEC1"
549 #define CONFIG_TSEC2 1
550 #define CONFIG_TSEC2_NAME "eTSEC2"
552 #define TSEC1_PHY_ADDR 1
553 #define TSEC2_PHY_ADDR 2
555 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
556 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
558 #define TSEC1_PHYIDX 0
559 #define TSEC2_PHYIDX 0
561 #define CONFIG_ETHPRIME "eTSEC1"
563 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
567 * Dynamic MTD Partition support with mtdparts
569 #define CONFIG_MTD_DEVICE
570 #define CONFIG_MTD_PARTITIONS
571 #define CONFIG_CMD_MTDPARTS
572 #define CONFIG_FLASH_CFI_MTD
573 #ifdef CONFIG_PHYS_64BIT
574 #define MTDIDS_DEFAULT "nor0=fe8000000.nor"
575 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
576 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
577 "512k(dtb),768k(u-boot)"
579 #define MTDIDS_DEFAULT "nor0=e8000000.nor"
580 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
581 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
582 "512k(dtb),768k(u-boot)"
588 #ifdef CONFIG_SPIFLASH
589 #define CONFIG_ENV_IS_IN_SPI_FLASH
590 #define CONFIG_ENV_SPI_BUS 0
591 #define CONFIG_ENV_SPI_CS 0
592 #define CONFIG_ENV_SPI_MAX_HZ 10000000
593 #define CONFIG_ENV_SPI_MODE 0
594 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
595 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
596 #define CONFIG_ENV_SECT_SIZE 0x10000
597 #elif defined(CONFIG_SDCARD)
598 #define CONFIG_ENV_IS_IN_MMC
599 #define CONFIG_FSL_FIXED_MMC_LOCATION
600 #define CONFIG_ENV_SIZE 0x2000
601 #define CONFIG_SYS_MMC_ENV_DEV 0
602 #elif defined(CONFIG_NAND)
603 #ifdef CONFIG_TPL_BUILD
604 #define CONFIG_ENV_SIZE 0x2000
605 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
607 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
609 #define CONFIG_ENV_IS_IN_NAND
610 #define CONFIG_ENV_OFFSET (1024 * 1024)
611 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
612 #elif defined(CONFIG_SYS_RAMBOOT)
613 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
614 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
615 #define CONFIG_ENV_SIZE 0x2000
617 #define CONFIG_ENV_IS_IN_FLASH
618 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
619 #define CONFIG_ENV_SIZE 0x2000
620 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
623 #define CONFIG_LOADS_ECHO
624 #define CONFIG_SYS_LOADS_BAUD_CHANGE
627 * Command line configuration.
629 #define CONFIG_CMD_ERRATA
630 #define CONFIG_CMD_IRQ
631 #define CONFIG_CMD_REGINFO
634 #define CONFIG_CMD_PCI
640 #define CONFIG_HAS_FSL_DR_USB
641 #ifdef CONFIG_HAS_FSL_DR_USB
642 #define CONFIG_USB_EHCI
644 #ifdef CONFIG_USB_EHCI
645 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
646 #define CONFIG_USB_EHCI_FSL
651 * Miscellaneous configurable options
653 #define CONFIG_SYS_LONGHELP /* undef to save memory */
654 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
655 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
656 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
657 #ifdef CONFIG_CMD_KGDB
658 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
660 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
662 /* Print Buffer Size */
663 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
664 #define CONFIG_SYS_MAXARGS 16
665 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
668 * For booting Linux, the board info and command line data
669 * have to be in the first 64 MB of memory, since this is
670 * the maximum mapped by the Linux kernel during initialization.
672 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
673 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
675 #ifdef CONFIG_CMD_KGDB
676 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
680 * Environment Configuration
683 #define CONFIG_HOSTNAME p1022ds
684 #define CONFIG_ROOTPATH "/opt/nfsroot"
685 #define CONFIG_BOOTFILE "uImage"
686 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
688 #define CONFIG_LOADADDR 1000000
691 #define CONFIG_BAUDRATE 115200
693 #define CONFIG_EXTRA_ENV_SETTINGS \
695 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
696 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
697 "tftpflash=tftpboot $loadaddr $uboot && " \
698 "protect off $ubootaddr +$filesize && " \
699 "erase $ubootaddr +$filesize && " \
700 "cp.b $loadaddr $ubootaddr $filesize && " \
701 "protect on $ubootaddr +$filesize && " \
702 "cmp.b $loadaddr $ubootaddr $filesize\0" \
703 "consoledev=ttyS0\0" \
704 "ramdiskaddr=2000000\0" \
705 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
706 "fdtaddr=1e00000\0" \
707 "fdtfile=p1022ds.dtb\0" \
709 "hwconfig=esdhc;audclk:12\0"
711 #define CONFIG_HDBOOT \
712 "setenv bootargs root=/dev/$bdev rw " \
713 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
714 "tftp $loadaddr $bootfile;" \
715 "tftp $fdtaddr $fdtfile;" \
716 "bootm $loadaddr - $fdtaddr"
718 #define CONFIG_NFSBOOTCOMMAND \
719 "setenv bootargs root=/dev/nfs rw " \
720 "nfsroot=$serverip:$rootpath " \
721 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
722 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
723 "tftp $loadaddr $bootfile;" \
724 "tftp $fdtaddr $fdtfile;" \
725 "bootm $loadaddr - $fdtaddr"
727 #define CONFIG_RAMBOOTCOMMAND \
728 "setenv bootargs root=/dev/ram rw " \
729 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
730 "tftp $ramdiskaddr $ramdiskfile;" \
731 "tftp $loadaddr $bootfile;" \
732 "tftp $fdtaddr $fdtfile;" \
733 "bootm $loadaddr $ramdiskaddr $fdtaddr"
735 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND