include/configs/P1022DS.h

   1 /*
   2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #ifdef CONFIG_36BIT
  15 #define CONFIG_PHYS_64BIT
  16 #endif
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_SPL
  20 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  21 #define CONFIG_SPL_ENV_SUPPORT
  22 #define CONFIG_SPL_SERIAL_SUPPORT
  23 #define CONFIG_SPL_MMC_SUPPORT
  24 #define CONFIG_SPL_MMC_MINIMAL
  25 #define CONFIG_SPL_FLUSH_IMAGE
  26 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  27 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  28 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  29 #define CONFIG_SPL_I2C_SUPPORT
  30 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  31 #define CONFIG_SYS_TEXT_BASE            0x11001000
  32 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  33 #define CONFIG_SPL_PAD_TO               0x18000
  34 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  35 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  36 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  37 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  38 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  40 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  41 #define CONFIG_SPL_MMC_BOOT
  42 #ifdef CONFIG_SPL_BUILD
  43 #define CONFIG_SPL_COMMON_INIT_DDR
  44 #endif
  45 #endif
  46
  47 #ifdef CONFIG_SPIFLASH
  48 #define CONFIG_SPL
  49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  50 #define CONFIG_SPL_ENV_SUPPORT
  51 #define CONFIG_SPL_SERIAL_SUPPORT
  52 #define CONFIG_SPL_SPI_SUPPORT
  53 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  54 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  55 #define CONFIG_SPL_FLUSH_IMAGE
  56 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  57 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  58 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  59 #define CONFIG_SPL_I2C_SUPPORT
  60 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  61 #define CONFIG_SYS_TEXT_BASE            0x11001000
  62 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  63 #define CONFIG_SPL_PAD_TO               0x18000
  64 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  70 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  71 #define CONFIG_SPL_SPI_BOOT
  72 #ifdef CONFIG_SPL_BUILD
  73 #define CONFIG_SPL_COMMON_INIT_DDR
  74 #endif
  75 #endif
  76
  77 #define CONFIG_NAND_FSL_ELBC
  78
  79 #ifdef CONFIG_NAND
  80 #define CONFIG_SPL
  81 #define CONFIG_SPL_INIT_MINIMAL
  82 #define CONFIG_SPL_SERIAL_SUPPORT
  83 #define CONFIG_SPL_NAND_SUPPORT
  84 #define CONFIG_SPL_FLUSH_IMAGE
  85 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
  86
  87 #define CONFIG_SYS_TEXT_BASE           0x00201000
  88 #define CONFIG_SPL_TEXT_BASE           0xfffff000
  89 #define CONFIG_SPL_MAX_SIZE            4096
  90 #define CONFIG_SPL_RELOC_TEXT_BASE     0x00100000
  91 #define CONFIG_SPL_RELOC_STACK         0x00100000
  92 #define CONFIG_SYS_NAND_U_BOOT_SIZE    ((512 << 10) + CONFIG_SPL_MAX_SIZE)
  93 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x00200000 - CONFIG_SPL_MAX_SIZE)
  94 #define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
  95 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0
  96 #define CONFIG_SYS_LDSCRIPT            "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  97 #endif
  98
  99 /* High Level Configuration Options */
 100 #define CONFIG_BOOKE                    /* BOOKE */
 101 #define CONFIG_E500                     /* BOOKE e500 family */
 102 #define CONFIG_MPC85xx                  /* MPC8540/60/55/41/48 */
 103 #define CONFIG_P1022
 104 #define CONFIG_P1022DS
 105 #define CONFIG_MP                       /* support multiple processors */
 106
 107 #ifndef CONFIG_SYS_TEXT_BASE
 108 #define CONFIG_SYS_TEXT_BASE    0xeff80000
 109 #endif
 110
 111 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 112 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 113 #endif
 114
 115 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
 116 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 117 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
 118 #define CONFIG_PCIE2                    /* PCIE controler 2 (slot 2) */
 119 #define CONFIG_PCIE3                    /* PCIE controler 3 (ULI bridge) */
 120 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 121 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 122 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 123
 124 #define CONFIG_ENABLE_36BIT_PHYS
 125
 126 #ifdef CONFIG_PHYS_64BIT
 127 #define CONFIG_ADDR_MAP
 128 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 129 #endif
 130
 131 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 132
 133 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 134 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 135 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
 136
 137 /*
 138  * These can be toggled for performance analysis, otherwise use default.
 139  */
 140 #define CONFIG_L2_CACHE
 141 #define CONFIG_BTB
 142
 143 #define CONFIG_SYS_MEMTEST_START        0x00000000
 144 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
 145
 146 #define CONFIG_SYS_CCSRBAR              0xffe00000
 147 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 148
 149 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 150        SPL code*/
 151 #ifdef CONFIG_SPL_BUILD
 152 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 153 #endif
 154
 155
 156 /* DDR Setup */
 157 #define CONFIG_DDR_SPD
 158 #define CONFIG_VERY_BIG_RAM
 159 #define CONFIG_FSL_DDR3
 160
 161 #ifdef CONFIG_DDR_ECC
 162 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 163 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 164 #endif
 165
 166 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 167 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 168
 169 #define CONFIG_NUM_DDR_CONTROLLERS      1
 170 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 171 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 172
 173 /* I2C addresses of SPD EEPROMs */
 174 #define CONFIG_SYS_SPD_BUS_NUM          1
 175 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
 176
 177 /* These are used when DDR doesn't use SPD.  */
 178 #define CONFIG_SYS_SDRAM_SIZE           2048
 179 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 180 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 181 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 182 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 183 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
 184 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
 185 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 186 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
 187 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
 188 #define CONFIG_SYS_DDR_MODE_1           0x00441221
 189 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 190 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
 191 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 192 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
 193 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
 194 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
 195 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 196 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 197 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 198 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
 199
 200
 201 /*
 202  * Memory map
 203  *
 204  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 205  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
 206  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
 207  *
 208  * Localbus cacheable (TBD)
 209  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 210  *
 211  * Localbus non-cacheable
 212  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 213  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 214  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
 215  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 216  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 217  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 218  */
 219
 220 /*
 221  * Local Bus Definitions
 222  */
 223 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
 224 #ifdef CONFIG_PHYS_64BIT
 225 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 226 #else
 227 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 228 #endif
 229
 230 #define CONFIG_FLASH_BR_PRELIM  \
 231         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 232 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 233
 234 #ifdef CONFIG_NAND
 235 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 236 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 237 #else
 238 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 239 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 240 #endif
 241
 242 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 243 #define CONFIG_SYS_FLASH_QUIET_TEST
 244 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 245
 246 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 247 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 248
 249 #ifndef CONFIG_SYS_MONITOR_BASE
 250 #ifdef CONFIG_SPL_BUILD
 251 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 252 #else
 253 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 254 #endif
 255 #endif
 256
 257 #define CONFIG_FLASH_CFI_DRIVER
 258 #define CONFIG_SYS_FLASH_CFI
 259 #define CONFIG_SYS_FLASH_EMPTY_INFO
 260
 261 /* Nand Flash */
 262 #if defined(CONFIG_NAND_FSL_ELBC)
 263 #define CONFIG_SYS_NAND_BASE            0xff800000
 264 #ifdef CONFIG_PHYS_64BIT
 265 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 266 #else
 267 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 268 #endif
 269
 270 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE, }
 271 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 272 #define CONFIG_MTD_NAND_VERIFY_WRITE
 273 #define CONFIG_CMD_NAND                 1
 274 #define CONFIG_SYS_NAND_BLOCK_SIZE    (256 * 1024)
 275 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 276
 277 /* NAND flash config */
 278 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 279                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 280                                | BR_PS_8               /* Port Size = 8 bit */ \
 281                                | BR_MS_FCM             /* MSEL = FCM */ \
 282                                | BR_V)                 /* valid */
 283 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
 284                                | OR_FCM_PGS            /* Large Page*/ \
 285                                | OR_FCM_CSCT \
 286                                | OR_FCM_CST \
 287                                | OR_FCM_CHT \
 288                                | OR_FCM_SCY_1 \
 289                                | OR_FCM_TRLX \
 290                                | OR_FCM_EHTR)
 291 #ifdef CONFIG_NAND
 292 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 293 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 294 #else
 295 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 296 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 297 #endif
 298
 299 #endif /* CONFIG_NAND_FSL_ELBC */
 300
 301 #define CONFIG_BOARD_EARLY_INIT_F
 302 #define CONFIG_BOARD_EARLY_INIT_R
 303 #define CONFIG_MISC_INIT_R
 304 #define CONFIG_HWCONFIG
 305
 306 #define CONFIG_FSL_NGPIXIS
 307 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 308 #ifdef CONFIG_PHYS_64BIT
 309 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 310 #else
 311 #define PIXIS_BASE_PHYS         PIXIS_BASE
 312 #endif
 313
 314 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 315 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 316
 317 #define PIXIS_LBMAP_SWITCH      7
 318 #define PIXIS_LBMAP_MASK        0xF0
 319 #define PIXIS_LBMAP_ALTBANK     0x20
 320 #define PIXIS_SPD               0x07
 321 #define PIXIS_SPD_SYSCLK_MASK   0x07
 322 #define PIXIS_ELBC_SPI_MASK     0xc0
 323 #define PIXIS_SPI               0x80
 324
 325 #define CONFIG_SYS_INIT_RAM_LOCK
 326 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 327 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
 328
 329 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 330         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 331 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 332
 333 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 334 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 335
 336 /*
 337  * Config the L2 Cache as L2 SRAM
 338 */
 339 #if defined(CONFIG_SPL_BUILD)
 340 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 341 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
 342 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 343 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 344 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 345 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 346 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 347 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 348 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
 349 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (96 << 10)
 350 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 351 #endif
 352 #endif
 353
 354 /*
 355  * Serial Port
 356  */
 357 #define CONFIG_CONS_INDEX               1
 358 #define CONFIG_SYS_NS16550
 359 #define CONFIG_SYS_NS16550_SERIAL
 360 #define CONFIG_SYS_NS16550_REG_SIZE     1
 361 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 362 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 363 #define CONFIG_NS16550_MIN_FUNCTIONS
 364 #endif
 365
 366 #define CONFIG_SYS_BAUDRATE_TABLE       \
 367         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 368
 369 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 370 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 371
 372 /* Use the HUSH parser */
 373 #define CONFIG_SYS_HUSH_PARSER
 374
 375 /* Video */
 376
 377 #ifdef CONFIG_FSL_DIU_FB
 378 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 379 #define CONFIG_VIDEO
 380 #define CONFIG_CMD_BMP
 381 #define CONFIG_CFB_CONSOLE
 382 #define CONFIG_VIDEO_SW_CURSOR
 383 #define CONFIG_VGA_AS_SINGLE_DEVICE
 384 #define CONFIG_VIDEO_LOGO
 385 #define CONFIG_VIDEO_BMP_LOGO
 386 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 387 /*
 388  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 389  * disable empty flash sector detection, which is I/O-intensive.
 390  */
 391 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 392 #endif
 393
 394 #ifndef CONFIG_FSL_DIU_FB
 395 #endif
 396
 397 #ifdef CONFIG_ATI
 398 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 399 #define CONFIG_VIDEO
 400 #define CONFIG_BIOSEMU
 401 #define CONFIG_VIDEO_SW_CURSOR
 402 #define CONFIG_ATI_RADEON_FB
 403 #define CONFIG_VIDEO_LOGO
 404 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 405 #define CONFIG_CFB_CONSOLE
 406 #define CONFIG_VGA_AS_SINGLE_DEVICE
 407 #endif
 408
 409 /*
 410  * Pass open firmware flat tree
 411  */
 412 #define CONFIG_OF_LIBFDT
 413 #define CONFIG_OF_BOARD_SETUP
 414 #define CONFIG_OF_STDOUT_VIA_ALIAS
 415
 416 /* new uImage format support */
 417 #define CONFIG_FIT
 418 #define CONFIG_FIT_VERBOSE
 419
 420 /* I2C */
 421 #define CONFIG_SYS_I2C
 422 #define CONFIG_SYS_I2C_FSL
 423 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 424 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 425 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 426 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 427 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 428 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 429 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 430
 431 /*
 432  * I2C2 EEPROM
 433  */
 434 #define CONFIG_ID_EEPROM
 435 #define CONFIG_SYS_I2C_EEPROM_NXID
 436 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 437 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 438 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 439
 440 /*
 441  * eSPI - Enhanced SPI
 442  */
 443 #define CONFIG_SPI_FLASH
 444 #define CONFIG_SPI_FLASH_SPANSION
 445
 446 #define CONFIG_HARD_SPI
 447 #define CONFIG_FSL_ESPI
 448
 449 #define CONFIG_CMD_SF
 450 #define CONFIG_SF_DEFAULT_SPEED         10000000
 451 #define CONFIG_SF_DEFAULT_MODE          0
 452
 453 /*
 454  * General PCI
 455  * Memory space is mapped 1-1, but I/O space must start from 0.
 456  */
 457
 458 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 459 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 460 #ifdef CONFIG_PHYS_64BIT
 461 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 462 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 463 #else
 464 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 465 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 466 #endif
 467 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 468 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 469 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 470 #ifdef CONFIG_PHYS_64BIT
 471 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 472 #else
 473 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 474 #endif
 475 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 476
 477 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 478 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 479 #ifdef CONFIG_PHYS_64BIT
 480 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 481 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 482 #else
 483 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 484 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 485 #endif
 486 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 487 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 488 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 489 #ifdef CONFIG_PHYS_64BIT
 490 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 491 #else
 492 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 493 #endif
 494 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 495
 496 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 497 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 498 #ifdef CONFIG_PHYS_64BIT
 499 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 500 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 501 #else
 502 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 503 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 504 #endif
 505 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 506 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 507 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 508 #ifdef CONFIG_PHYS_64BIT
 509 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 510 #else
 511 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 512 #endif
 513 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 514
 515 #ifdef CONFIG_PCI
 516 #define CONFIG_PCI_INDIRECT_BRIDGE
 517 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 518 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 519 #define CONFIG_E1000                    /* Define e1000 pci Ethernet card */
 520 #endif
 521
 522 /* SATA */
 523 #define CONFIG_LIBATA
 524 #define CONFIG_FSL_SATA
 525 #define CONFIG_FSL_SATA_V2
 526
 527 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 528 #define CONFIG_SATA1
 529 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 530 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 531 #define CONFIG_SATA2
 532 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 533 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 534
 535 #ifdef CONFIG_FSL_SATA
 536 #define CONFIG_LBA48
 537 #define CONFIG_CMD_SATA
 538 #define CONFIG_DOS_PARTITION
 539 #define CONFIG_CMD_EXT2
 540 #endif
 541
 542 #define CONFIG_MMC
 543 #ifdef CONFIG_MMC
 544 #define CONFIG_CMD_MMC
 545 #define CONFIG_FSL_ESDHC
 546 #define CONFIG_GENERIC_MMC
 547 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 548 #endif
 549
 550 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 551 #define CONFIG_CMD_EXT2
 552 #define CONFIG_CMD_FAT
 553 #define CONFIG_DOS_PARTITION
 554 #endif
 555
 556 #define CONFIG_TSEC_ENET
 557 #ifdef CONFIG_TSEC_ENET
 558
 559 #define CONFIG_TSECV2
 560
 561 #define CONFIG_MII                      /* MII PHY management */
 562 #define CONFIG_TSEC1            1
 563 #define CONFIG_TSEC1_NAME       "eTSEC1"
 564 #define CONFIG_TSEC2            1
 565 #define CONFIG_TSEC2_NAME       "eTSEC2"
 566
 567 #define TSEC1_PHY_ADDR          1
 568 #define TSEC2_PHY_ADDR          2
 569
 570 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 571 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 572
 573 #define TSEC1_PHYIDX            0
 574 #define TSEC2_PHYIDX            0
 575
 576 #define CONFIG_ETHPRIME         "eTSEC1"
 577
 578 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 579 #endif
 580
 581 /*
 582  * Environment
 583  */
 584 #ifdef CONFIG_SPIFLASH
 585 #define CONFIG_ENV_IS_IN_SPI_FLASH
 586 #define CONFIG_ENV_SPI_BUS      0
 587 #define CONFIG_ENV_SPI_CS       0
 588 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 589 #define CONFIG_ENV_SPI_MODE     0
 590 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 591 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 592 #define CONFIG_ENV_SECT_SIZE    0x10000
 593 #elif defined(CONFIG_SDCARD)
 594 #define CONFIG_ENV_IS_IN_MMC
 595 #define CONFIG_FSL_FIXED_MMC_LOCATION
 596 #define CONFIG_ENV_SIZE         0x2000
 597 #define CONFIG_SYS_MMC_ENV_DEV  0
 598 #elif defined(CONFIG_NAND)
 599 #define CONFIG_ENV_IS_IN_NAND
 600 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 601 #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 602 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 603 #elif defined(CONFIG_SYS_RAMBOOT)
 604 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 605 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 606 #define CONFIG_ENV_SIZE         0x2000
 607 #else
 608 #define CONFIG_ENV_IS_IN_FLASH
 609 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 610 #define CONFIG_ENV_ADDR 0xfff80000
 611 #else
 612 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 613 #endif
 614 #define CONFIG_ENV_SIZE         0x2000
 615 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 616 #endif
 617
 618 #define CONFIG_LOADS_ECHO
 619 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 620
 621 /*
 622  * Command line configuration.
 623  */
 624 #include <config_cmd_default.h>
 625
 626 #define CONFIG_CMD_ELF
 627 #define CONFIG_CMD_ERRATA
 628 #define CONFIG_CMD_IRQ
 629 #define CONFIG_CMD_I2C
 630 #define CONFIG_CMD_MII
 631 #define CONFIG_CMD_PING
 632 #define CONFIG_CMD_SETEXPR
 633 #define CONFIG_CMD_REGINFO
 634
 635 #ifdef CONFIG_PCI
 636 #define CONFIG_CMD_PCI
 637 #define CONFIG_CMD_NET
 638 #endif
 639
 640 /*
 641  * USB
 642  */
 643 #define CONFIG_HAS_FSL_DR_USB
 644 #ifdef CONFIG_HAS_FSL_DR_USB
 645 #define CONFIG_USB_EHCI
 646
 647 #ifdef CONFIG_USB_EHCI
 648 #define CONFIG_CMD_USB
 649 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 650 #define CONFIG_USB_EHCI_FSL
 651 #define CONFIG_USB_STORAGE
 652 #define CONFIG_CMD_FAT
 653 #endif
 654 #endif
 655
 656 /*
 657  * Miscellaneous configurable options
 658  */
 659 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 660 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 661 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 662 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 663 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 664 #ifdef CONFIG_CMD_KGDB
 665 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 666 #else
 667 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 668 #endif
 669 /* Print Buffer Size */
 670 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 671 #define CONFIG_SYS_MAXARGS      16
 672 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 673 #define CONFIG_SYS_HZ           1000
 674
 675 /*
 676  * For booting Linux, the board info and command line data
 677  * have to be in the first 64 MB of memory, since this is
 678  * the maximum mapped by the Linux kernel during initialization.
 679  */
 680 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 681 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 682
 683 #ifdef CONFIG_CMD_KGDB
 684 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 685 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 686 #endif
 687
 688 /*
 689  * Environment Configuration
 690  */
 691
 692 #define CONFIG_HOSTNAME         p1022ds
 693 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 694 #define CONFIG_BOOTFILE         "uImage"
 695 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 696
 697 #define CONFIG_LOADADDR         1000000
 698
 699 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 700
 701 #define CONFIG_BAUDRATE 115200
 702
 703 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 704         "netdev=eth0\0"                                         \
 705         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 706         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 707         "tftpflash=tftpboot $loadaddr $uboot && "               \
 708                 "protect off $ubootaddr +$filesize && "         \
 709                 "erase $ubootaddr +$filesize && "               \
 710                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 711                 "protect on $ubootaddr +$filesize && "          \
 712                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 713         "consoledev=ttyS0\0"                                    \
 714         "ramdiskaddr=2000000\0"                                 \
 715         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 716         "fdtaddr=c00000\0"                                      \
 717         "fdtfile=p1022ds.dtb\0"                                 \
 718         "bdev=sda3\0"                                           \
 719         "hwconfig=esdhc;audclk:12\0"
 720
 721 #define CONFIG_HDBOOT                                   \
 722         "setenv bootargs root=/dev/$bdev rw "           \
 723         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 724         "tftp $loadaddr $bootfile;"                     \
 725         "tftp $fdtaddr $fdtfile;"                       \
 726         "bootm $loadaddr - $fdtaddr"
 727
 728 #define CONFIG_NFSBOOTCOMMAND                                           \
 729         "setenv bootargs root=/dev/nfs rw "                             \
 730         "nfsroot=$serverip:$rootpath "                                  \
 731         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 732         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 733         "tftp $loadaddr $bootfile;"                                     \
 734         "tftp $fdtaddr $fdtfile;"                                       \
 735         "bootm $loadaddr - $fdtaddr"
 736
 737 #define CONFIG_RAMBOOTCOMMAND                                           \
 738         "setenv bootargs root=/dev/ram rw "                             \
 739         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 740         "tftp $ramdiskaddr $ramdiskfile;"                               \
 741         "tftp $loadaddr $bootfile;"                                     \
 742         "tftp $fdtaddr $fdtfile;"                                       \
 743         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 744
 745 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 746
 747 #endif