powerpc/85xx: Enable various errata on P1022/P1013 SoCs
[platform/kernel/u-boot.git] / include / configs / P1022DS.h
1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4  *          Timur Tabi <timur@freescale.com>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the Free
8  * Software Foundation; either version 2 of the License, or (at your option)
9  * any later version.
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 #include "../board/freescale/common/ics307_clk.h"
16
17 /* High Level Configuration Options */
18 #define CONFIG_BOOKE                    /* BOOKE */
19 #define CONFIG_E500                     /* BOOKE e500 family */
20 #define CONFIG_MPC85xx                  /* MPC8540/60/55/41/48 */
21 #define CONFIG_P1022
22 #define CONFIG_P1022DS
23 #define CONFIG_MP                       /* support multiple processors */
24
25 #ifndef CONFIG_SYS_TEXT_BASE
26 #define CONFIG_SYS_TEXT_BASE    0xeff80000
27 #endif
28
29 #ifndef CONFIG_RESET_VECTOR_ADDRESS
30 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
31 #endif
32
33 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
34 #define CONFIG_PCI                      /* Enable PCI/PCIE */
35 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
36 #define CONFIG_PCIE2                    /* PCIE controler 2 (slot 2) */
37 #define CONFIG_PCIE3                    /* PCIE controler 3 (ULI bridge) */
38 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
39 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
40 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
41
42 #define CONFIG_PHYS_64BIT
43 #define CONFIG_ENABLE_36BIT_PHYS
44 #define CONFIG_ADDR_MAP
45 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
46
47 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
48
49 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
50 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
51 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
52
53 /*
54  * These can be toggled for performance analysis, otherwise use default.
55  */
56 #define CONFIG_L2_CACHE
57 #define CONFIG_BTB
58
59 #define CONFIG_SYS_MEMTEST_START        0x00000000
60 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
61
62 /*
63  * Base addresses -- Note these are effective addresses where the
64  * actual resources get mapped (not physical addresses)
65  */
66 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
67 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
68 #define CONFIG_SYS_CCSRBAR_PHYS         0xfffe00000ull
69 #define CONFIG_SYS_IMMR                 CONFIG_SYS_CCSRBAR
70
71 /* DDR Setup */
72 #define CONFIG_DDR_SPD
73 #define CONFIG_VERY_BIG_RAM
74 #define CONFIG_FSL_DDR3
75
76 #ifdef CONFIG_DDR_ECC
77 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
78 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
79 #endif
80
81 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
82 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
83
84 #define CONFIG_NUM_DDR_CONTROLLERS      1
85 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
86 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
87
88 /* I2C addresses of SPD EEPROMs */
89 #define CONFIG_SYS_SPD_BUS_NUM          1
90 #define SPD_EEPROM_ADDRESS1             0x51    /* CTLR 0 DIMM 0 */
91
92 /*
93  * Memory map
94  *
95  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
96  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
97  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
98  *
99  * Localbus cacheable (TBD)
100  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
101  *
102  * Localbus non-cacheable
103  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
104  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
105  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
106  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
107  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
108  */
109
110 /*
111  * Local Bus Definitions
112  */
113 #define CONFIG_SYS_FLASH_BASE           0xe0000000 /* start of FLASH 128M */
114 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
115
116 #define CONFIG_FLASH_BR_PRELIM  \
117         (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
118 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
119
120 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
121 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
122
123 #define CONFIG_SYS_BR1_PRELIM   \
124         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
125 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM
126
127 #define CONFIG_SYS_FLASH_BANKS_LIST     \
128         {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
129 #define CONFIG_SYS_FLASH_QUIET_TEST
130 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
131
132 #define CONFIG_SYS_MAX_FLASH_BANKS      2
133 #define CONFIG_SYS_MAX_FLASH_SECT       1024
134
135 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
136
137 #define CONFIG_FLASH_CFI_DRIVER
138 #define CONFIG_SYS_FLASH_CFI
139 #define CONFIG_SYS_FLASH_EMPTY_INFO
140
141 #define CONFIG_BOARD_EARLY_INIT_F
142 #define CONFIG_BOARD_EARLY_INIT_R
143 #define CONFIG_MISC_INIT_R
144 #define CONFIG_HWCONFIG
145
146 #define CONFIG_FSL_NGPIXIS
147 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
148 #define PIXIS_BASE_PHYS         0xfffdf0000ull
149
150 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
151 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
152
153 #define PIXIS_LBMAP_SWITCH      7
154 #define PIXIS_LBMAP_MASK        0xF0
155 #define PIXIS_LBMAP_ALTBANK     0x20
156
157 #define CONFIG_SYS_INIT_RAM_LOCK
158 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
159 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
160
161 #define CONFIG_SYS_GBL_DATA_OFFSET      \
162         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
163 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
164
165 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
166 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)
167
168 /*
169  * Serial Port
170  */
171 #define CONFIG_CONS_INDEX               1
172 #define CONFIG_SYS_NS16550
173 #define CONFIG_SYS_NS16550_SERIAL
174 #define CONFIG_SYS_NS16550_REG_SIZE     1
175 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
176
177 #define CONFIG_SYS_BAUDRATE_TABLE       \
178         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
179
180 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
181 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
182
183 /* Use the HUSH parser */
184 #define CONFIG_SYS_HUSH_PARSER
185 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
186
187 /* Video */
188 #undef CONFIG_FSL_DIU_FB
189
190 #ifdef CONFIG_FSL_DIU_FB
191 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
192 #define CONFIG_VIDEO
193 #define CONFIG_CMD_BMP
194 #define CONFIG_CFB_CONSOLE
195 #define CONFIG_VGA_AS_SINGLE_DEVICE
196 #define CONFIG_VIDEO_LOGO
197 #define CONFIG_VIDEO_BMP_LOGO
198 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
199 /*
200  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
201  * disable empty flash sector detection, which is I/O-intensive.
202  */
203 #undef CONFIG_SYS_FLASH_EMPTY_INFO
204 #endif
205
206 /*
207  * Pass open firmware flat tree
208  */
209 #define CONFIG_OF_LIBFDT
210 #define CONFIG_OF_BOARD_SETUP
211 #define CONFIG_OF_STDOUT_VIA_ALIAS
212
213 /* new uImage format support */
214 #define CONFIG_FIT
215 #define CONFIG_FIT_VERBOSE
216
217 /* I2C */
218 #define CONFIG_FSL_I2C
219 #define CONFIG_HARD_I2C
220 #define CONFIG_I2C_MULTI_BUS
221 #define CONFIG_SYS_I2C_SPEED            400000
222 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
223 #define CONFIG_SYS_I2C_SLAVE            0x7F
224 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
225 #define CONFIG_SYS_I2C_OFFSET           0x3000
226 #define CONFIG_SYS_I2C2_OFFSET          0x3100
227
228 /*
229  * I2C2 EEPROM
230  */
231 #define CONFIG_ID_EEPROM
232 #define CONFIG_SYS_I2C_EEPROM_NXID
233 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
235 #define CONFIG_SYS_EEPROM_BUS_NUM       1
236
237 /*
238  * General PCI
239  * Memory space is mapped 1-1, but I/O space must start from 0.
240  */
241
242 /* controller 1, Slot 2, tgtid 1, Base address a000 */
243 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
244 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
245 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
246 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
247 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
248 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
249 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
250 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
251
252 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
253 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
254 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
255 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
256 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
257 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
258 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
259 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
260 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
261
262 /* controller 3, Slot 1, tgtid 3, Base address b000 */
263 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
264 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
265 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
266 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
267 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
268 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
269 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
270 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
271
272 #ifdef CONFIG_PCI
273 #define CONFIG_NET_MULTI
274 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
275 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
276 #define CONFIG_E1000                    /* Define e1000 pci Ethernet card */
277 #endif
278
279 /* SATA */
280 #define CONFIG_LIBATA
281 #define CONFIG_FSL_SATA
282 #define CONFIG_FSL_SATA_V2
283
284 #define CONFIG_SYS_SATA_MAX_DEVICE      2
285 #define CONFIG_SATA1
286 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
287 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
288 #define CONFIG_SATA2
289 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
290 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
291
292 #ifdef CONFIG_FSL_SATA
293 #define CONFIG_LBA48
294 #define CONFIG_CMD_SATA
295 #define CONFIG_DOS_PARTITION
296 #define CONFIG_CMD_EXT2
297 #endif
298
299 #define CONFIG_MMC
300 #ifdef CONFIG_MMC
301 #define CONFIG_CMD_MMC
302 #define CONFIG_FSL_ESDHC
303 #define CONFIG_GENERIC_MMC
304 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
305 #endif
306
307 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
308 #define CONFIG_CMD_EXT2
309 #define CONFIG_CMD_FAT
310 #define CONFIG_DOS_PARTITION
311 #endif
312
313 #define CONFIG_TSEC_ENET
314 #ifdef CONFIG_TSEC_ENET
315
316 #define CONFIG_TSECV2
317 #define CONFIG_NET_MULTI
318
319 #define CONFIG_MII                      /* MII PHY management */
320 #define CONFIG_TSEC1            1
321 #define CONFIG_TSEC1_NAME       "eTSEC1"
322 #define CONFIG_TSEC2            1
323 #define CONFIG_TSEC2_NAME       "eTSEC2"
324
325 #define TSEC1_PHY_ADDR          1
326 #define TSEC2_PHY_ADDR          2
327
328 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
329 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
330
331 #define TSEC1_PHYIDX            0
332 #define TSEC2_PHYIDX            0
333
334 #define CONFIG_ETHPRIME         "eTSEC1"
335
336 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
337 #endif
338
339 /*
340  * Environment
341  */
342 #define CONFIG_ENV_IS_IN_FLASH
343 #define CONFIG_ENV_OVERWRITE
344 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
345 #define CONFIG_ENV_SIZE         0x2000
346 #define CONFIG_ENV_SECT_SIZE    0x20000
347
348 #define CONFIG_LOADS_ECHO
349 #define CONFIG_SYS_LOADS_BAUD_CHANGE
350
351 /*
352  * Command line configuration.
353  */
354 #include <config_cmd_default.h>
355
356 #define CONFIG_CMD_ELF
357 #define CONFIG_CMD_ERRATA
358 #define CONFIG_CMD_IRQ
359 #define CONFIG_CMD_I2C
360 #define CONFIG_CMD_MII
361 #define CONFIG_CMD_PING
362 #define CONFIG_CMD_SETEXPR
363 #define CONFIG_CMD_REGINFO
364
365 #ifdef CONFIG_PCI
366 #define CONFIG_CMD_PCI
367 #define CONFIG_CMD_NET
368 #endif
369
370 /*
371  * USB
372  */
373 #define CONFIG_USB_EHCI
374
375 #ifdef CONFIG_USB_EHCI
376 #define CONFIG_CMD_USB
377 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
378 #define CONFIG_USB_EHCI_FSL
379 #define CONFIG_USB_STORAGE
380 #define CONFIG_CMD_FAT
381 #endif
382
383 /*
384  * Miscellaneous configurable options
385  */
386 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
387 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
388 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
389 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
390 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
391 #ifdef CONFIG_CMD_KGDB
392 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
393 #else
394 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
395 #endif
396 /* Print Buffer Size */
397 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
398 #define CONFIG_SYS_MAXARGS      16
399 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
400 #define CONFIG_SYS_HZ           1000
401
402 /*
403  * For booting Linux, the board info and command line data
404  * have to be in the first 16 MB of memory, since this is
405  * the maximum mapped by the Linux kernel during initialization.
406  */
407 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
408 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
409
410 #ifdef CONFIG_CMD_KGDB
411 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
412 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
413 #endif
414
415 /*
416  * Environment Configuration
417  */
418
419 #define CONFIG_HOSTNAME         p1022ds
420 #define CONFIG_ROOTPATH         /opt/nfsroot
421 #define CONFIG_BOOTFILE         uImage
422 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
423
424 #define CONFIG_LOADADDR         1000000
425
426 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
427 #define CONFIG_BOOTARGS
428
429 #define CONFIG_BAUDRATE 115200
430
431 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
432         "perf_mode=stable\0"                                            \
433         "memctl_intlv_ctl=2\0"                                          \
434         "netdev=eth0\0"                                                 \
435         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
436         "tftpflash=tftpboot $loadaddr $uboot; "                         \
437                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
438                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
439                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
440                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
441                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
442         "consoledev=ttyS0\0"                                            \
443         "ramdiskaddr=2000000\0"                                         \
444         "ramdiskfile=uramdisk\0"                                        \
445         "fdtaddr=c00000\0"                                              \
446         "fdtfile=p1022ds.dtb\0"                                         \
447         "bdev=sda3\0"                                                   \
448         "diuregs=md e002c000 1d\0"                                      \
449         "dium=mw e002c01c\0"                                            \
450         "diuerr=md e002c014 1\0"                                        \
451         "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
452         "monitor=0-DVI\0"
453
454 #define CONFIG_HDBOOT                                   \
455         "setenv bootargs root=/dev/$bdev rw "           \
456         "console=$consoledev,$baudrate $othbootargs;"   \
457         "tftp $loadaddr $bootfile;"                     \
458         "tftp $fdtaddr $fdtfile;"                       \
459         "bootm $loadaddr - $fdtaddr"
460
461 #define CONFIG_NFSBOOTCOMMAND                                           \
462         "setenv bootargs root=/dev/nfs rw "                             \
463         "nfsroot=$serverip:$rootpath "                                  \
464         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
465         "console=$consoledev,$baudrate $othbootargs;"                   \
466         "tftp $loadaddr $bootfile;"                                     \
467         "tftp $fdtaddr $fdtfile;"                                       \
468         "bootm $loadaddr - $fdtaddr"
469
470 #define CONFIG_RAMBOOTCOMMAND                                           \
471         "setenv bootargs root=/dev/ram rw "                             \
472         "console=$consoledev,$baudrate $othbootargs;"                   \
473         "tftp $ramdiskaddr $ramdiskfile;"                               \
474         "tftp $loadaddr $bootfile;"                                     \
475         "tftp $fdtaddr $fdtfile;"                                       \
476         "bootm $loadaddr $ramdiskaddr $fdtaddr"
477
478 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
479
480 #endif