cmd: Kconfig: Move CONFIG_MP to Kconfig
[platform/kernel/u-boot.git] / include / configs / P1022DS.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2010-2012 Freescale Semiconductor, Inc.
4  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5  *          Timur Tabi <timur@freescale.com>
6  */
7
8 #ifndef __CONFIG_H
9 #define __CONFIG_H
10
11 #include "../board/freescale/common/ics307_clk.h"
12
13 #ifdef CONFIG_SDCARD
14 #define CONFIG_SPL_FLUSH_IMAGE
15 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
16 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
17 #define CONFIG_SPL_PAD_TO               0x20000
18 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
19 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
20 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
21 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
23 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
24 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
25 #define CONFIG_SPL_MMC_BOOT
26 #ifdef CONFIG_SPL_BUILD
27 #define CONFIG_SPL_COMMON_INIT_DDR
28 #endif
29 #endif
30
31 #ifdef CONFIG_SPIFLASH
32 #define CONFIG_SPL_SPI_FLASH_MINIMAL
33 #define CONFIG_SPL_FLUSH_IMAGE
34 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
35 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
36 #define CONFIG_SPL_PAD_TO               0x20000
37 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
42 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
43 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
44 #define CONFIG_SPL_SPI_BOOT
45 #ifdef CONFIG_SPL_BUILD
46 #define CONFIG_SPL_COMMON_INIT_DDR
47 #endif
48 #endif
49
50 #define CONFIG_NAND_FSL_ELBC
51 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
52 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
53
54 #ifdef CONFIG_NAND
55 #ifdef CONFIG_TPL_BUILD
56 #define CONFIG_SPL_NAND_BOOT
57 #define CONFIG_SPL_FLUSH_IMAGE
58 #define CONFIG_SPL_NAND_INIT
59 #define CONFIG_SPL_COMMON_INIT_DDR
60 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
61 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
63 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
64 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
65 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
66 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
67 #elif defined(CONFIG_SPL_BUILD)
68 #define CONFIG_SPL_INIT_MINIMAL
69 #define CONFIG_SPL_FLUSH_IMAGE
70 #define CONFIG_SPL_TEXT_BASE            0xff800000
71 #define CONFIG_SPL_MAX_SIZE             4096
72 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
73 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
74 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
75 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
76 #endif
77 #define CONFIG_SPL_PAD_TO               0x20000
78 #define CONFIG_TPL_PAD_TO               0x20000
79 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
80 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
81 #endif
82
83 /* High Level Configuration Options */
84
85 #ifndef CONFIG_RESET_VECTOR_ADDRESS
86 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
87 #endif
88
89 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
90 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
91 #define CONFIG_PCIE3                    /* PCIE controller 3 (ULI bridge) */
92 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
93 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
94 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
95
96 #define CONFIG_ENABLE_36BIT_PHYS
97
98 #ifdef CONFIG_PHYS_64BIT
99 #define CONFIG_ADDR_MAP
100 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
101 #endif
102
103 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
104 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
105 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
106
107 /*
108  * These can be toggled for performance analysis, otherwise use default.
109  */
110 #define CONFIG_L2_CACHE
111 #define CONFIG_BTB
112
113 #define CONFIG_SYS_MEMTEST_START        0x00000000
114 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
115
116 #define CONFIG_SYS_CCSRBAR              0xffe00000
117 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
118
119 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
120        SPL code*/
121 #ifdef CONFIG_SPL_BUILD
122 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
123 #endif
124
125 /* DDR Setup */
126 #define CONFIG_DDR_SPD
127 #define CONFIG_VERY_BIG_RAM
128
129 #ifdef CONFIG_DDR_ECC
130 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
131 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
132 #endif
133
134 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
135 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
136
137 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
138 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
139
140 /* I2C addresses of SPD EEPROMs */
141 #define CONFIG_SYS_SPD_BUS_NUM          1
142 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
143
144 /* These are used when DDR doesn't use SPD.  */
145 #define CONFIG_SYS_SDRAM_SIZE           2048
146 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
147 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
148 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
149 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
150 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
151 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
152 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
153 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
154 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
155 #define CONFIG_SYS_DDR_MODE_1           0x00441221
156 #define CONFIG_SYS_DDR_MODE_2           0x00000000
157 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
158 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
159 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
160 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
161 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
162 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
163 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
164 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
165 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
166
167 /*
168  * Memory map
169  *
170  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
171  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
172  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
173  *
174  * Localbus cacheable (TBD)
175  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
176  *
177  * Localbus non-cacheable
178  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
179  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
180  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
181  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
182  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
183  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
184  */
185
186 /*
187  * Local Bus Definitions
188  */
189 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
190 #ifdef CONFIG_PHYS_64BIT
191 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
192 #else
193 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
194 #endif
195
196 #define CONFIG_FLASH_BR_PRELIM  \
197         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
198 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
199
200 #ifdef CONFIG_NAND
201 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
202 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
203 #else
204 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
205 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
206 #endif
207
208 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
209 #define CONFIG_SYS_FLASH_QUIET_TEST
210 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
211
212 #define CONFIG_SYS_MAX_FLASH_BANKS      1
213 #define CONFIG_SYS_MAX_FLASH_SECT       1024
214
215 #ifndef CONFIG_SYS_MONITOR_BASE
216 #ifdef CONFIG_SPL_BUILD
217 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
218 #else
219 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
220 #endif
221 #endif
222
223 #define CONFIG_FLASH_CFI_DRIVER
224 #define CONFIG_SYS_FLASH_CFI
225 #define CONFIG_SYS_FLASH_EMPTY_INFO
226
227 /* Nand Flash */
228 #if defined(CONFIG_NAND_FSL_ELBC)
229 #define CONFIG_SYS_NAND_BASE            0xff800000
230 #ifdef CONFIG_PHYS_64BIT
231 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
232 #else
233 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
234 #endif
235
236 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
237 #define CONFIG_SYS_MAX_NAND_DEVICE      1
238 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
239 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
240
241 /* NAND flash config */
242 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
243                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
244                                | BR_PS_8               /* Port Size = 8 bit */ \
245                                | BR_MS_FCM             /* MSEL = FCM */ \
246                                | BR_V)                 /* valid */
247 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
248                                | OR_FCM_PGS            /* Large Page*/ \
249                                | OR_FCM_CSCT \
250                                | OR_FCM_CST \
251                                | OR_FCM_CHT \
252                                | OR_FCM_SCY_1 \
253                                | OR_FCM_TRLX \
254                                | OR_FCM_EHTR)
255 #ifdef CONFIG_NAND
256 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
257 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
258 #else
259 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
260 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
261 #endif
262
263 #endif /* CONFIG_NAND_FSL_ELBC */
264
265 #define CONFIG_MISC_INIT_R
266 #define CONFIG_HWCONFIG
267
268 #define CONFIG_FSL_NGPIXIS
269 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
270 #ifdef CONFIG_PHYS_64BIT
271 #define PIXIS_BASE_PHYS         0xfffdf0000ull
272 #else
273 #define PIXIS_BASE_PHYS         PIXIS_BASE
274 #endif
275
276 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
277 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
278
279 #define PIXIS_LBMAP_SWITCH      7
280 #define PIXIS_LBMAP_MASK        0xF0
281 #define PIXIS_LBMAP_ALTBANK     0x20
282 #define PIXIS_SPD               0x07
283 #define PIXIS_SPD_SYSCLK_MASK   0x07
284 #define PIXIS_ELBC_SPI_MASK     0xc0
285 #define PIXIS_SPI               0x80
286
287 #define CONFIG_SYS_INIT_RAM_LOCK
288 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
289 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
290
291 #define CONFIG_SYS_GBL_DATA_OFFSET      \
292         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
293 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
294
295 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
296 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
297
298 /*
299  * Config the L2 Cache as L2 SRAM
300 */
301 #if defined(CONFIG_SPL_BUILD)
302 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
303 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
304 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
305 #define CONFIG_SYS_L2_SIZE              (256 << 10)
306 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
307 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
308 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
309 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
310 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
311 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
312 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
313 #elif defined(CONFIG_NAND)
314 #ifdef CONFIG_TPL_BUILD
315 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
316 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
317 #define CONFIG_SYS_L2_SIZE              (256 << 10)
318 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
319 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
320 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
321 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
322 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
323 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
324 #else
325 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
326 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
327 #define CONFIG_SYS_L2_SIZE              (256 << 10)
328 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
329 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
330 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
331 #endif
332 #endif
333 #endif
334
335 /*
336  * Serial Port
337  */
338 #define CONFIG_SYS_NS16550_SERIAL
339 #define CONFIG_SYS_NS16550_REG_SIZE     1
340 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
341 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
342 #define CONFIG_NS16550_MIN_FUNCTIONS
343 #endif
344
345 #define CONFIG_SYS_BAUDRATE_TABLE       \
346         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
347
348 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
349 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
350
351 /* Video */
352
353 #ifdef CONFIG_FSL_DIU_FB
354 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
355 #define CONFIG_VIDEO_LOGO
356 #define CONFIG_VIDEO_BMP_LOGO
357 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
358 /*
359  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
360  * disable empty flash sector detection, which is I/O-intensive.
361  */
362 #undef CONFIG_SYS_FLASH_EMPTY_INFO
363 #endif
364
365 #ifdef CONFIG_ATI
366 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
367 #define CONFIG_BIOSEMU
368 #define CONFIG_ATI_RADEON_FB
369 #define CONFIG_VIDEO_LOGO
370 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
371 #endif
372
373 /* I2C */
374 #define CONFIG_SYS_I2C
375 #define CONFIG_SYS_I2C_FSL
376 #define CONFIG_SYS_FSL_I2C_SPEED        400000
377 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
378 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
379 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
380 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
381 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
382 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
383
384 /*
385  * I2C2 EEPROM
386  */
387 #define CONFIG_ID_EEPROM
388 #define CONFIG_SYS_I2C_EEPROM_NXID
389 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
390 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
391 #define CONFIG_SYS_EEPROM_BUS_NUM       1
392
393 /*
394  * eSPI - Enhanced SPI
395  */
396
397 #define CONFIG_HARD_SPI
398
399 #define CONFIG_SF_DEFAULT_SPEED         10000000
400 #define CONFIG_SF_DEFAULT_MODE          0
401
402 /*
403  * General PCI
404  * Memory space is mapped 1-1, but I/O space must start from 0.
405  */
406
407 /* controller 1, Slot 2, tgtid 1, Base address a000 */
408 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
409 #ifdef CONFIG_PHYS_64BIT
410 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
411 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
412 #else
413 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
414 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
415 #endif
416 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
417 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
418 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
419 #ifdef CONFIG_PHYS_64BIT
420 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
421 #else
422 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
423 #endif
424 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
425
426 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
427 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
428 #ifdef CONFIG_PHYS_64BIT
429 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
430 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
431 #else
432 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
433 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
434 #endif
435 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
436 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
437 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
438 #ifdef CONFIG_PHYS_64BIT
439 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
440 #else
441 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
442 #endif
443 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
444
445 /* controller 3, Slot 1, tgtid 3, Base address b000 */
446 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
449 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
450 #else
451 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
452 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
453 #endif
454 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
455 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
456 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
457 #ifdef CONFIG_PHYS_64BIT
458 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
459 #else
460 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
461 #endif
462 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
463
464 #ifdef CONFIG_PCI
465 #define CONFIG_PCI_INDIRECT_BRIDGE
466 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
467 #endif
468
469 /* SATA */
470 #define CONFIG_FSL_SATA_V2
471
472 #define CONFIG_SYS_SATA_MAX_DEVICE      2
473 #define CONFIG_SATA1
474 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
475 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
476 #define CONFIG_SATA2
477 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
478 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
479
480 #ifdef CONFIG_FSL_SATA
481 #define CONFIG_LBA48
482 #endif
483
484 #ifdef CONFIG_MMC
485 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
486 #endif
487
488 #ifdef CONFIG_TSEC_ENET
489
490 #define CONFIG_TSECV2
491
492 #define CONFIG_MII                      /* MII PHY management */
493 #define CONFIG_TSEC1            1
494 #define CONFIG_TSEC1_NAME       "eTSEC1"
495 #define CONFIG_TSEC2            1
496 #define CONFIG_TSEC2_NAME       "eTSEC2"
497
498 #define TSEC1_PHY_ADDR          1
499 #define TSEC2_PHY_ADDR          2
500
501 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
502 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
503
504 #define TSEC1_PHYIDX            0
505 #define TSEC2_PHYIDX            0
506
507 #define CONFIG_ETHPRIME         "eTSEC1"
508 #endif
509
510 /*
511  * Dynamic MTD Partition support with mtdparts
512  */
513 #define CONFIG_MTD_DEVICE
514 #define CONFIG_MTD_PARTITIONS
515 #define CONFIG_FLASH_CFI_MTD
516
517 /*
518  * Environment
519  */
520 #ifdef CONFIG_SPIFLASH
521 #define CONFIG_ENV_SPI_BUS      0
522 #define CONFIG_ENV_SPI_CS       0
523 #define CONFIG_ENV_SPI_MAX_HZ   10000000
524 #define CONFIG_ENV_SPI_MODE     0
525 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
526 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
527 #define CONFIG_ENV_SECT_SIZE    0x10000
528 #elif defined(CONFIG_SDCARD)
529 #define CONFIG_FSL_FIXED_MMC_LOCATION
530 #define CONFIG_ENV_SIZE         0x2000
531 #define CONFIG_SYS_MMC_ENV_DEV  0
532 #elif defined(CONFIG_NAND)
533 #ifdef CONFIG_TPL_BUILD
534 #define CONFIG_ENV_SIZE         0x2000
535 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
536 #else
537 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
538 #endif
539 #define CONFIG_ENV_OFFSET       (1024 * 1024)
540 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
541 #elif defined(CONFIG_SYS_RAMBOOT)
542 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
543 #define CONFIG_ENV_SIZE         0x2000
544 #else
545 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
546 #define CONFIG_ENV_SIZE         0x2000
547 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
548 #endif
549
550 #define CONFIG_LOADS_ECHO
551 #define CONFIG_SYS_LOADS_BAUD_CHANGE
552
553 /*
554  * USB
555  */
556 #define CONFIG_HAS_FSL_DR_USB
557 #ifdef CONFIG_HAS_FSL_DR_USB
558 #ifdef CONFIG_USB_EHCI_HCD
559 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
560 #define CONFIG_USB_EHCI_FSL
561 #endif
562 #endif
563
564 /*
565  * Miscellaneous configurable options
566  */
567 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
568
569 /*
570  * For booting Linux, the board info and command line data
571  * have to be in the first 64 MB of memory, since this is
572  * the maximum mapped by the Linux kernel during initialization.
573  */
574 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
575 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
576
577 #ifdef CONFIG_CMD_KGDB
578 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
579 #endif
580
581 /*
582  * Environment Configuration
583  */
584
585 #define CONFIG_HOSTNAME         "p1022ds"
586 #define CONFIG_ROOTPATH         "/opt/nfsroot"
587 #define CONFIG_BOOTFILE         "uImage"
588 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
589
590 #define CONFIG_LOADADDR         1000000
591
592 #define CONFIG_EXTRA_ENV_SETTINGS                               \
593         "netdev=eth0\0"                                         \
594         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
595         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
596         "tftpflash=tftpboot $loadaddr $uboot && "               \
597                 "protect off $ubootaddr +$filesize && "         \
598                 "erase $ubootaddr +$filesize && "               \
599                 "cp.b $loadaddr $ubootaddr $filesize && "       \
600                 "protect on $ubootaddr +$filesize && "          \
601                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
602         "consoledev=ttyS0\0"                                    \
603         "ramdiskaddr=2000000\0"                                 \
604         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
605         "fdtaddr=1e00000\0"                                     \
606         "fdtfile=p1022ds.dtb\0"                                 \
607         "bdev=sda3\0"                                           \
608         "hwconfig=esdhc;audclk:12\0"
609
610 #define CONFIG_HDBOOT                                   \
611         "setenv bootargs root=/dev/$bdev rw "           \
612         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
613         "tftp $loadaddr $bootfile;"                     \
614         "tftp $fdtaddr $fdtfile;"                       \
615         "bootm $loadaddr - $fdtaddr"
616
617 #define CONFIG_NFSBOOTCOMMAND                                           \
618         "setenv bootargs root=/dev/nfs rw "                             \
619         "nfsroot=$serverip:$rootpath "                                  \
620         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
621         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
622         "tftp $loadaddr $bootfile;"                                     \
623         "tftp $fdtaddr $fdtfile;"                                       \
624         "bootm $loadaddr - $fdtaddr"
625
626 #define CONFIG_RAMBOOTCOMMAND                                           \
627         "setenv bootargs root=/dev/ram rw "                             \
628         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
629         "tftp $ramdiskaddr $ramdiskfile;"                               \
630         "tftp $loadaddr $bootfile;"                                     \
631         "tftp $fdtaddr $fdtfile;"                                       \
632         "bootm $loadaddr $ramdiskaddr $fdtaddr"
633
634 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
635
636 #endif