bd080909a01c63cba8a862f1ebeac30e9ed6f865
[platform/kernel/u-boot.git] / include / configs / P1022DS.h
1 /*
2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4  *          Timur Tabi <timur@freescale.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #include "../board/freescale/common/ics307_clk.h"
13
14 #ifdef CONFIG_36BIT
15 #define CONFIG_PHYS_64BIT
16 #endif
17
18 #ifdef CONFIG_SDCARD
19 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
20 #define CONFIG_SPL_ENV_SUPPORT
21 #define CONFIG_SPL_SERIAL_SUPPORT
22 #define CONFIG_SPL_MMC_SUPPORT
23 #define CONFIG_SPL_MMC_MINIMAL
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
26 #define CONFIG_SPL_LIBGENERIC_SUPPORT
27 #define CONFIG_SPL_LIBCOMMON_SUPPORT
28 #define CONFIG_SPL_I2C_SUPPORT
29 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
30 #define CONFIG_SYS_TEXT_BASE            0x11001000
31 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
32 #define CONFIG_SPL_PAD_TO               0x20000
33 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
34 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
35 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
36 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
37 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
39 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
40 #define CONFIG_SPL_MMC_BOOT
41 #ifdef CONFIG_SPL_BUILD
42 #define CONFIG_SPL_COMMON_INIT_DDR
43 #endif
44 #endif
45
46 #ifdef CONFIG_SPIFLASH
47 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
48 #define CONFIG_SPL_ENV_SUPPORT
49 #define CONFIG_SPL_SERIAL_SUPPORT
50 #define CONFIG_SPL_SPI_SUPPORT
51 #define CONFIG_SPL_SPI_FLASH_SUPPORT
52 #define CONFIG_SPL_SPI_FLASH_MINIMAL
53 #define CONFIG_SPL_FLUSH_IMAGE
54 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
55 #define CONFIG_SPL_LIBGENERIC_SUPPORT
56 #define CONFIG_SPL_LIBCOMMON_SUPPORT
57 #define CONFIG_SPL_I2C_SUPPORT
58 #define CONFIG_FSL_LAW          /* Use common FSL init code */
59 #define CONFIG_SYS_TEXT_BASE            0x11001000
60 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
61 #define CONFIG_SPL_PAD_TO               0x20000
62 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
67 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
68 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
69 #define CONFIG_SPL_SPI_BOOT
70 #ifdef CONFIG_SPL_BUILD
71 #define CONFIG_SPL_COMMON_INIT_DDR
72 #endif
73 #endif
74
75 #define CONFIG_NAND_FSL_ELBC
76 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
77 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
78
79 #ifdef CONFIG_NAND
80 #ifdef CONFIG_TPL_BUILD
81 #define CONFIG_SPL_NAND_BOOT
82 #define CONFIG_SPL_FLUSH_IMAGE
83 #define CONFIG_SPL_ENV_SUPPORT
84 #define CONFIG_SPL_NAND_INIT
85 #define CONFIG_SPL_SERIAL_SUPPORT
86 #define CONFIG_SPL_LIBGENERIC_SUPPORT
87 #define CONFIG_SPL_LIBCOMMON_SUPPORT
88 #define CONFIG_SPL_I2C_SUPPORT
89 #define CONFIG_SPL_NAND_SUPPORT
90 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
91 #define CONFIG_SPL_COMMON_INIT_DDR
92 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
93 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
94 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
95 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
96 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
97 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
98 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
99 #elif defined(CONFIG_SPL_BUILD)
100 #define CONFIG_SPL_INIT_MINIMAL
101 #define CONFIG_SPL_SERIAL_SUPPORT
102 #define CONFIG_SPL_NAND_SUPPORT
103 #define CONFIG_SPL_FLUSH_IMAGE
104 #define CONFIG_SPL_TEXT_BASE            0xff800000
105 #define CONFIG_SPL_MAX_SIZE             4096
106 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
107 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
108 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
109 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
110 #endif
111 #define CONFIG_SPL_PAD_TO               0x20000
112 #define CONFIG_TPL_PAD_TO               0x20000
113 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
114 #define CONFIG_SYS_TEXT_BASE            0x11001000
115 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
116 #endif
117
118 /* High Level Configuration Options */
119 #define CONFIG_BOOKE                    /* BOOKE */
120 #define CONFIG_E500                     /* BOOKE e500 family */
121 #define CONFIG_P1022
122 #define CONFIG_P1022DS
123 #define CONFIG_MP                       /* support multiple processors */
124
125 #ifndef CONFIG_SYS_TEXT_BASE
126 #define CONFIG_SYS_TEXT_BASE    0xeff40000
127 #endif
128
129 #ifndef CONFIG_RESET_VECTOR_ADDRESS
130 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
131 #endif
132
133 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
134 #define CONFIG_PCI                      /* Enable PCI/PCIE */
135 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
136 #define CONFIG_PCIE2                    /* PCIE controler 2 (slot 2) */
137 #define CONFIG_PCIE3                    /* PCIE controler 3 (ULI bridge) */
138 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
139 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
140 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
141
142 #define CONFIG_ENABLE_36BIT_PHYS
143
144 #ifdef CONFIG_PHYS_64BIT
145 #define CONFIG_ADDR_MAP
146 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
147 #endif
148
149 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
150
151 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
152 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
153 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
154
155 /*
156  * These can be toggled for performance analysis, otherwise use default.
157  */
158 #define CONFIG_L2_CACHE
159 #define CONFIG_BTB
160
161 #define CONFIG_SYS_MEMTEST_START        0x00000000
162 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
163
164 #define CONFIG_SYS_CCSRBAR              0xffe00000
165 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
166
167 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
168        SPL code*/
169 #ifdef CONFIG_SPL_BUILD
170 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
171 #endif
172
173
174 /* DDR Setup */
175 #define CONFIG_DDR_SPD
176 #define CONFIG_VERY_BIG_RAM
177 #define CONFIG_SYS_FSL_DDR3
178
179 #ifdef CONFIG_DDR_ECC
180 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
181 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
182 #endif
183
184 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
185 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
186
187 #define CONFIG_NUM_DDR_CONTROLLERS      1
188 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
189 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
190
191 /* I2C addresses of SPD EEPROMs */
192 #define CONFIG_SYS_SPD_BUS_NUM          1
193 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
194
195 /* These are used when DDR doesn't use SPD.  */
196 #define CONFIG_SYS_SDRAM_SIZE           2048
197 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
198 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
199 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
200 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
201 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
202 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
203 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
204 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
205 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
206 #define CONFIG_SYS_DDR_MODE_1           0x00441221
207 #define CONFIG_SYS_DDR_MODE_2           0x00000000
208 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
209 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
210 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
211 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
212 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
213 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
214 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
215 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
216 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
217
218
219 /*
220  * Memory map
221  *
222  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
223  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
224  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
225  *
226  * Localbus cacheable (TBD)
227  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
228  *
229  * Localbus non-cacheable
230  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
231  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
232  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
233  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
234  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
235  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
236  */
237
238 /*
239  * Local Bus Definitions
240  */
241 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
242 #ifdef CONFIG_PHYS_64BIT
243 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
244 #else
245 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
246 #endif
247
248 #define CONFIG_FLASH_BR_PRELIM  \
249         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
250 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
251
252 #ifdef CONFIG_NAND
253 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
254 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
255 #else
256 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
257 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
258 #endif
259
260 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
261 #define CONFIG_SYS_FLASH_QUIET_TEST
262 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
263
264 #define CONFIG_SYS_MAX_FLASH_BANKS      1
265 #define CONFIG_SYS_MAX_FLASH_SECT       1024
266
267 #ifndef CONFIG_SYS_MONITOR_BASE
268 #ifdef CONFIG_SPL_BUILD
269 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
270 #else
271 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
272 #endif
273 #endif
274
275 #define CONFIG_FLASH_CFI_DRIVER
276 #define CONFIG_SYS_FLASH_CFI
277 #define CONFIG_SYS_FLASH_EMPTY_INFO
278
279 /* Nand Flash */
280 #if defined(CONFIG_NAND_FSL_ELBC)
281 #define CONFIG_SYS_NAND_BASE            0xff800000
282 #ifdef CONFIG_PHYS_64BIT
283 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
284 #else
285 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
286 #endif
287
288 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
289 #define CONFIG_SYS_MAX_NAND_DEVICE      1
290 #define CONFIG_MTD_NAND_VERIFY_WRITE
291 #define CONFIG_CMD_NAND                 1
292 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
293 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
294
295 /* NAND flash config */
296 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
297                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
298                                | BR_PS_8               /* Port Size = 8 bit */ \
299                                | BR_MS_FCM             /* MSEL = FCM */ \
300                                | BR_V)                 /* valid */
301 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
302                                | OR_FCM_PGS            /* Large Page*/ \
303                                | OR_FCM_CSCT \
304                                | OR_FCM_CST \
305                                | OR_FCM_CHT \
306                                | OR_FCM_SCY_1 \
307                                | OR_FCM_TRLX \
308                                | OR_FCM_EHTR)
309 #ifdef CONFIG_NAND
310 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
311 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
312 #else
313 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
314 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
315 #endif
316
317 #endif /* CONFIG_NAND_FSL_ELBC */
318
319 #define CONFIG_BOARD_EARLY_INIT_F
320 #define CONFIG_BOARD_EARLY_INIT_R
321 #define CONFIG_MISC_INIT_R
322 #define CONFIG_HWCONFIG
323
324 #define CONFIG_FSL_NGPIXIS
325 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
326 #ifdef CONFIG_PHYS_64BIT
327 #define PIXIS_BASE_PHYS         0xfffdf0000ull
328 #else
329 #define PIXIS_BASE_PHYS         PIXIS_BASE
330 #endif
331
332 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
333 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
334
335 #define PIXIS_LBMAP_SWITCH      7
336 #define PIXIS_LBMAP_MASK        0xF0
337 #define PIXIS_LBMAP_ALTBANK     0x20
338 #define PIXIS_SPD               0x07
339 #define PIXIS_SPD_SYSCLK_MASK   0x07
340 #define PIXIS_ELBC_SPI_MASK     0xc0
341 #define PIXIS_SPI               0x80
342
343 #define CONFIG_SYS_INIT_RAM_LOCK
344 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
345 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
346
347 #define CONFIG_SYS_GBL_DATA_OFFSET      \
348         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
349 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
350
351 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
352 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
353
354 /*
355  * Config the L2 Cache as L2 SRAM
356 */
357 #if defined(CONFIG_SPL_BUILD)
358 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
359 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
360 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
361 #define CONFIG_SYS_L2_SIZE              (256 << 10)
362 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
363 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
364 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
365 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
366 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
367 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
368 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
369 #elif defined(CONFIG_NAND)
370 #ifdef CONFIG_TPL_BUILD
371 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
372 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
373 #define CONFIG_SYS_L2_SIZE              (256 << 10)
374 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
375 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
376 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
377 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
378 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
379 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
380 #else
381 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
382 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
383 #define CONFIG_SYS_L2_SIZE              (256 << 10)
384 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
385 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
386 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
387 #endif
388 #endif
389 #endif
390
391 /*
392  * Serial Port
393  */
394 #define CONFIG_CONS_INDEX               1
395 #define CONFIG_SYS_NS16550
396 #define CONFIG_SYS_NS16550_SERIAL
397 #define CONFIG_SYS_NS16550_REG_SIZE     1
398 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
399 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
400 #define CONFIG_NS16550_MIN_FUNCTIONS
401 #endif
402
403 #define CONFIG_SYS_BAUDRATE_TABLE       \
404         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
405
406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
407 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
408
409 /* Use the HUSH parser */
410 #define CONFIG_SYS_HUSH_PARSER
411
412 /* Video */
413
414 #ifdef CONFIG_FSL_DIU_FB
415 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
416 #define CONFIG_VIDEO
417 #define CONFIG_CMD_BMP
418 #define CONFIG_CFB_CONSOLE
419 #define CONFIG_VIDEO_SW_CURSOR
420 #define CONFIG_VGA_AS_SINGLE_DEVICE
421 #define CONFIG_VIDEO_LOGO
422 #define CONFIG_VIDEO_BMP_LOGO
423 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
424 /*
425  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
426  * disable empty flash sector detection, which is I/O-intensive.
427  */
428 #undef CONFIG_SYS_FLASH_EMPTY_INFO
429 #endif
430
431 #ifndef CONFIG_FSL_DIU_FB
432 #endif
433
434 #ifdef CONFIG_ATI
435 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
436 #define CONFIG_VIDEO
437 #define CONFIG_BIOSEMU
438 #define CONFIG_VIDEO_SW_CURSOR
439 #define CONFIG_ATI_RADEON_FB
440 #define CONFIG_VIDEO_LOGO
441 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
442 #define CONFIG_CFB_CONSOLE
443 #define CONFIG_VGA_AS_SINGLE_DEVICE
444 #endif
445
446 /*
447  * Pass open firmware flat tree
448  */
449 #define CONFIG_OF_LIBFDT
450 #define CONFIG_OF_BOARD_SETUP
451 #define CONFIG_OF_STDOUT_VIA_ALIAS
452
453 /* new uImage format support */
454 #define CONFIG_FIT
455 #define CONFIG_FIT_VERBOSE
456
457 /* I2C */
458 #define CONFIG_SYS_I2C
459 #define CONFIG_SYS_I2C_FSL
460 #define CONFIG_SYS_FSL_I2C_SPEED        400000
461 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
462 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
463 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
464 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
465 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
466 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
467
468 /*
469  * I2C2 EEPROM
470  */
471 #define CONFIG_ID_EEPROM
472 #define CONFIG_SYS_I2C_EEPROM_NXID
473 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
474 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
475 #define CONFIG_SYS_EEPROM_BUS_NUM       1
476
477 /*
478  * eSPI - Enhanced SPI
479  */
480 #define CONFIG_SPI_FLASH
481 #define CONFIG_SPI_FLASH_SPANSION
482
483 #define CONFIG_HARD_SPI
484 #define CONFIG_FSL_ESPI
485
486 #define CONFIG_CMD_SF
487 #define CONFIG_SF_DEFAULT_SPEED         10000000
488 #define CONFIG_SF_DEFAULT_MODE          0
489
490 /*
491  * General PCI
492  * Memory space is mapped 1-1, but I/O space must start from 0.
493  */
494
495 /* controller 1, Slot 2, tgtid 1, Base address a000 */
496 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
497 #ifdef CONFIG_PHYS_64BIT
498 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
499 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
500 #else
501 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
502 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
503 #endif
504 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
505 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
506 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
507 #ifdef CONFIG_PHYS_64BIT
508 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
509 #else
510 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
511 #endif
512 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
513
514 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
515 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
516 #ifdef CONFIG_PHYS_64BIT
517 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
518 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
519 #else
520 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
521 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
522 #endif
523 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
524 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
525 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
526 #ifdef CONFIG_PHYS_64BIT
527 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
528 #else
529 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
530 #endif
531 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
532
533 /* controller 3, Slot 1, tgtid 3, Base address b000 */
534 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
535 #ifdef CONFIG_PHYS_64BIT
536 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
537 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
538 #else
539 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
540 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
541 #endif
542 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
543 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
544 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
545 #ifdef CONFIG_PHYS_64BIT
546 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
547 #else
548 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
549 #endif
550 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
551
552 #ifdef CONFIG_PCI
553 #define CONFIG_PCI_INDIRECT_BRIDGE
554 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
555 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
556 #define CONFIG_E1000                    /* Define e1000 pci Ethernet card */
557 #endif
558
559 /* SATA */
560 #define CONFIG_LIBATA
561 #define CONFIG_FSL_SATA
562 #define CONFIG_FSL_SATA_V2
563
564 #define CONFIG_SYS_SATA_MAX_DEVICE      2
565 #define CONFIG_SATA1
566 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
567 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
568 #define CONFIG_SATA2
569 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
570 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
571
572 #ifdef CONFIG_FSL_SATA
573 #define CONFIG_LBA48
574 #define CONFIG_CMD_SATA
575 #define CONFIG_DOS_PARTITION
576 #define CONFIG_CMD_EXT2
577 #endif
578
579 #define CONFIG_MMC
580 #ifdef CONFIG_MMC
581 #define CONFIG_CMD_MMC
582 #define CONFIG_FSL_ESDHC
583 #define CONFIG_GENERIC_MMC
584 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
585 #endif
586
587 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
588 #define CONFIG_CMD_EXT2
589 #define CONFIG_CMD_FAT
590 #define CONFIG_DOS_PARTITION
591 #endif
592
593 #define CONFIG_TSEC_ENET
594 #ifdef CONFIG_TSEC_ENET
595
596 #define CONFIG_TSECV2
597
598 #define CONFIG_MII                      /* MII PHY management */
599 #define CONFIG_TSEC1            1
600 #define CONFIG_TSEC1_NAME       "eTSEC1"
601 #define CONFIG_TSEC2            1
602 #define CONFIG_TSEC2_NAME       "eTSEC2"
603
604 #define TSEC1_PHY_ADDR          1
605 #define TSEC2_PHY_ADDR          2
606
607 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
608 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
609
610 #define TSEC1_PHYIDX            0
611 #define TSEC2_PHYIDX            0
612
613 #define CONFIG_ETHPRIME         "eTSEC1"
614
615 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
616 #endif
617
618 /*
619  * Dynamic MTD Partition support with mtdparts
620  */
621 #define CONFIG_MTD_DEVICE
622 #define CONFIG_MTD_PARTITIONS
623 #define CONFIG_CMD_MTDPARTS
624 #define CONFIG_FLASH_CFI_MTD
625 #ifdef CONFIG_PHYS_64BIT
626 #define MTDIDS_DEFAULT "nor0=fe8000000.nor"
627 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
628                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
629                         "512k(dtb),768k(u-boot)"
630 #else
631 #define MTDIDS_DEFAULT "nor0=e8000000.nor"
632 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
633                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
634                         "512k(dtb),768k(u-boot)"
635 #endif
636
637 /*
638  * Environment
639  */
640 #ifdef CONFIG_SPIFLASH
641 #define CONFIG_ENV_IS_IN_SPI_FLASH
642 #define CONFIG_ENV_SPI_BUS      0
643 #define CONFIG_ENV_SPI_CS       0
644 #define CONFIG_ENV_SPI_MAX_HZ   10000000
645 #define CONFIG_ENV_SPI_MODE     0
646 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
647 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
648 #define CONFIG_ENV_SECT_SIZE    0x10000
649 #elif defined(CONFIG_SDCARD)
650 #define CONFIG_ENV_IS_IN_MMC
651 #define CONFIG_FSL_FIXED_MMC_LOCATION
652 #define CONFIG_ENV_SIZE         0x2000
653 #define CONFIG_SYS_MMC_ENV_DEV  0
654 #elif defined(CONFIG_NAND)
655 #ifdef CONFIG_TPL_BUILD
656 #define CONFIG_ENV_SIZE         0x2000
657 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
658 #else
659 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
660 #endif
661 #define CONFIG_ENV_IS_IN_NAND
662 #define CONFIG_ENV_OFFSET       (1024 * 1024)
663 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
664 #elif defined(CONFIG_SYS_RAMBOOT)
665 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
666 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
667 #define CONFIG_ENV_SIZE         0x2000
668 #else
669 #define CONFIG_ENV_IS_IN_FLASH
670 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
671 #define CONFIG_ENV_SIZE         0x2000
672 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
673 #endif
674
675 #define CONFIG_LOADS_ECHO
676 #define CONFIG_SYS_LOADS_BAUD_CHANGE
677
678 /*
679  * Command line configuration.
680  */
681 #include <config_cmd_default.h>
682
683 #define CONFIG_CMD_ELF
684 #define CONFIG_CMD_ERRATA
685 #define CONFIG_CMD_IRQ
686 #define CONFIG_CMD_I2C
687 #define CONFIG_CMD_MII
688 #define CONFIG_CMD_PING
689 #define CONFIG_CMD_SETEXPR
690 #define CONFIG_CMD_REGINFO
691
692 #ifdef CONFIG_PCI
693 #define CONFIG_CMD_PCI
694 #define CONFIG_CMD_NET
695 #endif
696
697 /*
698  * USB
699  */
700 #define CONFIG_HAS_FSL_DR_USB
701 #ifdef CONFIG_HAS_FSL_DR_USB
702 #define CONFIG_USB_EHCI
703
704 #ifdef CONFIG_USB_EHCI
705 #define CONFIG_CMD_USB
706 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
707 #define CONFIG_USB_EHCI_FSL
708 #define CONFIG_USB_STORAGE
709 #define CONFIG_CMD_FAT
710 #endif
711 #endif
712
713 /*
714  * Miscellaneous configurable options
715  */
716 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
717 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
718 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
719 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
720 #ifdef CONFIG_CMD_KGDB
721 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
722 #else
723 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
724 #endif
725 /* Print Buffer Size */
726 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
727 #define CONFIG_SYS_MAXARGS      16
728 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
729
730 /*
731  * For booting Linux, the board info and command line data
732  * have to be in the first 64 MB of memory, since this is
733  * the maximum mapped by the Linux kernel during initialization.
734  */
735 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
736 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
737
738 #ifdef CONFIG_CMD_KGDB
739 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
740 #endif
741
742 /*
743  * Environment Configuration
744  */
745
746 #define CONFIG_HOSTNAME         p1022ds
747 #define CONFIG_ROOTPATH         "/opt/nfsroot"
748 #define CONFIG_BOOTFILE         "uImage"
749 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
750
751 #define CONFIG_LOADADDR         1000000
752
753 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
754
755 #define CONFIG_BAUDRATE 115200
756
757 #define CONFIG_EXTRA_ENV_SETTINGS                               \
758         "netdev=eth0\0"                                         \
759         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
760         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
761         "tftpflash=tftpboot $loadaddr $uboot && "               \
762                 "protect off $ubootaddr +$filesize && "         \
763                 "erase $ubootaddr +$filesize && "               \
764                 "cp.b $loadaddr $ubootaddr $filesize && "       \
765                 "protect on $ubootaddr +$filesize && "          \
766                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
767         "consoledev=ttyS0\0"                                    \
768         "ramdiskaddr=2000000\0"                                 \
769         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
770         "fdtaddr=c00000\0"                                      \
771         "fdtfile=p1022ds.dtb\0"                                 \
772         "bdev=sda3\0"                                           \
773         "hwconfig=esdhc;audclk:12\0"
774
775 #define CONFIG_HDBOOT                                   \
776         "setenv bootargs root=/dev/$bdev rw "           \
777         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
778         "tftp $loadaddr $bootfile;"                     \
779         "tftp $fdtaddr $fdtfile;"                       \
780         "bootm $loadaddr - $fdtaddr"
781
782 #define CONFIG_NFSBOOTCOMMAND                                           \
783         "setenv bootargs root=/dev/nfs rw "                             \
784         "nfsroot=$serverip:$rootpath "                                  \
785         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
786         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
787         "tftp $loadaddr $bootfile;"                                     \
788         "tftp $fdtaddr $fdtfile;"                                       \
789         "bootm $loadaddr - $fdtaddr"
790
791 #define CONFIG_RAMBOOTCOMMAND                                           \
792         "setenv bootargs root=/dev/ram rw "                             \
793         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
794         "tftp $ramdiskaddr $ramdiskfile;"                               \
795         "tftp $loadaddr $bootfile;"                                     \
796         "tftp $fdtaddr $fdtfile;"                                       \
797         "bootm $loadaddr $ramdiskaddr $fdtaddr"
798
799 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
800
801 #endif