1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5 * Timur Tabi <timur@freescale.com>
11 #include "../board/freescale/common/ics307_clk.h"
14 #define CONFIG_SPL_FLUSH_IMAGE
15 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
16 #define CONFIG_SPL_PAD_TO 0x20000
17 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
18 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
19 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
20 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
21 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
22 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
23 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
24 #define CONFIG_SPL_MMC_BOOT
25 #ifdef CONFIG_SPL_BUILD
26 #define CONFIG_SPL_COMMON_INIT_DDR
30 #ifdef CONFIG_SPIFLASH
31 #define CONFIG_SPL_SPI_FLASH_MINIMAL
32 #define CONFIG_SPL_FLUSH_IMAGE
33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34 #define CONFIG_SPL_PAD_TO 0x20000
35 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
41 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
42 #define CONFIG_SPL_SPI_BOOT
43 #ifdef CONFIG_SPL_BUILD
44 #define CONFIG_SPL_COMMON_INIT_DDR
48 #define CONFIG_NAND_FSL_ELBC
49 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
50 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
53 #ifdef CONFIG_TPL_BUILD
54 #define CONFIG_SPL_NAND_BOOT
55 #define CONFIG_SPL_FLUSH_IMAGE
56 #define CONFIG_SPL_NAND_INIT
57 #define CONFIG_SPL_COMMON_INIT_DDR
58 #define CONFIG_SPL_MAX_SIZE (128 << 10)
59 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
60 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
61 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
62 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
63 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
64 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
65 #elif defined(CONFIG_SPL_BUILD)
66 #define CONFIG_SPL_INIT_MINIMAL
67 #define CONFIG_SPL_FLUSH_IMAGE
68 #define CONFIG_SPL_MAX_SIZE 4096
69 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
70 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
71 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
72 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
74 #define CONFIG_SPL_PAD_TO 0x20000
75 #define CONFIG_TPL_PAD_TO 0x20000
76 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
80 /* High Level Configuration Options */
82 #ifndef CONFIG_RESET_VECTOR_ADDRESS
83 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
86 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
87 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
88 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
89 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
90 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
91 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
93 #define CONFIG_ENABLE_36BIT_PHYS
95 #ifdef CONFIG_PHYS_64BIT
96 #define CONFIG_ADDR_MAP
97 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
100 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
101 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
102 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
105 * These can be toggled for performance analysis, otherwise use default.
107 #define CONFIG_L2_CACHE
110 #define CONFIG_SYS_MEMTEST_START 0x00000000
111 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
113 #define CONFIG_SYS_CCSRBAR 0xffe00000
114 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
116 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
118 #ifdef CONFIG_SPL_BUILD
119 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
123 #define CONFIG_DDR_SPD
124 #define CONFIG_VERY_BIG_RAM
126 #ifdef CONFIG_DDR_ECC
127 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
128 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
131 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
132 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
134 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
135 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
137 /* I2C addresses of SPD EEPROMs */
138 #define CONFIG_SYS_SPD_BUS_NUM 1
139 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
141 /* These are used when DDR doesn't use SPD. */
142 #define CONFIG_SYS_SDRAM_SIZE 2048
143 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
144 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
145 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
146 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
147 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
148 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
149 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
150 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
151 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
152 #define CONFIG_SYS_DDR_MODE_1 0x00441221
153 #define CONFIG_SYS_DDR_MODE_2 0x00000000
154 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
155 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
156 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
157 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
158 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
159 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
160 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
161 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
162 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
167 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
168 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
169 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
171 * Localbus cacheable (TBD)
172 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
174 * Localbus non-cacheable
175 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
176 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
177 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
178 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
179 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
180 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
184 * Local Bus Definitions
186 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
187 #ifdef CONFIG_PHYS_64BIT
188 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
190 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
193 #define CONFIG_FLASH_BR_PRELIM \
194 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
195 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
198 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
199 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
201 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
202 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
205 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
206 #define CONFIG_SYS_FLASH_QUIET_TEST
207 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
209 #define CONFIG_SYS_MAX_FLASH_BANKS 1
210 #define CONFIG_SYS_MAX_FLASH_SECT 1024
212 #ifndef CONFIG_SYS_MONITOR_BASE
213 #ifdef CONFIG_TPL_BUILD
214 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
215 #elif defined(CONFIG_SPL_BUILD)
216 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
218 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
222 #define CONFIG_SYS_FLASH_EMPTY_INFO
225 #if defined(CONFIG_NAND_FSL_ELBC)
226 #define CONFIG_SYS_NAND_BASE 0xff800000
227 #ifdef CONFIG_PHYS_64BIT
228 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
230 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
233 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
234 #define CONFIG_SYS_MAX_NAND_DEVICE 1
235 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
236 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
238 /* NAND flash config */
239 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
240 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
241 | BR_PS_8 /* Port Size = 8 bit */ \
242 | BR_MS_FCM /* MSEL = FCM */ \
244 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
245 | OR_FCM_PGS /* Large Page*/ \
253 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
254 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
256 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
257 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
260 #endif /* CONFIG_NAND_FSL_ELBC */
262 #define CONFIG_HWCONFIG
264 #define CONFIG_FSL_NGPIXIS
265 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
266 #ifdef CONFIG_PHYS_64BIT
267 #define PIXIS_BASE_PHYS 0xfffdf0000ull
269 #define PIXIS_BASE_PHYS PIXIS_BASE
272 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
273 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
275 #define PIXIS_LBMAP_SWITCH 7
276 #define PIXIS_LBMAP_MASK 0xF0
277 #define PIXIS_LBMAP_ALTBANK 0x20
278 #define PIXIS_SPD 0x07
279 #define PIXIS_SPD_SYSCLK_MASK 0x07
280 #define PIXIS_ELBC_SPI_MASK 0xc0
281 #define PIXIS_SPI 0x80
283 #define CONFIG_SYS_INIT_RAM_LOCK
284 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
285 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
287 #define CONFIG_SYS_GBL_DATA_OFFSET \
288 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
289 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
291 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
292 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
295 * Config the L2 Cache as L2 SRAM
297 #if defined(CONFIG_SPL_BUILD)
298 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
299 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
300 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
301 #define CONFIG_SYS_L2_SIZE (256 << 10)
302 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
303 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
304 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
305 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
306 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
307 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
308 #elif defined(CONFIG_NAND)
309 #ifdef CONFIG_TPL_BUILD
310 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
311 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
312 #define CONFIG_SYS_L2_SIZE (256 << 10)
313 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
314 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
315 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
316 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
317 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
318 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
320 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
321 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
322 #define CONFIG_SYS_L2_SIZE (256 << 10)
323 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
324 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
325 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
333 #define CONFIG_SYS_NS16550_SERIAL
334 #define CONFIG_SYS_NS16550_REG_SIZE 1
335 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
336 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
337 #define CONFIG_NS16550_MIN_FUNCTIONS
340 #define CONFIG_SYS_BAUDRATE_TABLE \
341 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
343 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
344 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
348 #ifdef CONFIG_FSL_DIU_FB
349 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
350 #define CONFIG_VIDEO_LOGO
351 #define CONFIG_VIDEO_BMP_LOGO
352 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
354 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
355 * disable empty flash sector detection, which is I/O-intensive.
357 #undef CONFIG_SYS_FLASH_EMPTY_INFO
361 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
362 #define CONFIG_BIOSEMU
363 #define CONFIG_ATI_RADEON_FB
364 #define CONFIG_VIDEO_LOGO
365 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
369 #define CONFIG_SYS_I2C
370 #define CONFIG_SYS_I2C_FSL
371 #define CONFIG_SYS_FSL_I2C_SPEED 400000
372 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
373 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
374 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
375 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
376 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
377 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
382 #define CONFIG_ID_EEPROM
383 #define CONFIG_SYS_I2C_EEPROM_NXID
384 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
385 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
386 #define CONFIG_SYS_EEPROM_BUS_NUM 1
390 * Memory space is mapped 1-1, but I/O space must start from 0.
393 /* controller 1, Slot 2, tgtid 1, Base address a000 */
394 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
395 #ifdef CONFIG_PHYS_64BIT
396 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
397 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
399 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
402 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
403 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
404 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
405 #ifdef CONFIG_PHYS_64BIT
406 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
408 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
410 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
412 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
413 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
414 #ifdef CONFIG_PHYS_64BIT
415 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
416 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
421 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
422 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
423 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
424 #ifdef CONFIG_PHYS_64BIT
425 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
427 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
429 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
431 /* controller 3, Slot 1, tgtid 3, Base address b000 */
432 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
433 #ifdef CONFIG_PHYS_64BIT
434 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
435 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
437 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
438 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
440 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
441 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
442 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
443 #ifdef CONFIG_PHYS_64BIT
444 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
446 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
448 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
451 #define CONFIG_PCI_INDIRECT_BRIDGE
452 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
456 #define CONFIG_FSL_SATA_V2
458 #define CONFIG_SYS_SATA_MAX_DEVICE 2
460 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
461 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
463 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
464 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
466 #ifdef CONFIG_FSL_SATA
471 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
474 #ifdef CONFIG_TSEC_ENET
476 #define CONFIG_TSECV2
478 #define CONFIG_TSEC1 1
479 #define CONFIG_TSEC1_NAME "eTSEC1"
480 #define CONFIG_TSEC2 1
481 #define CONFIG_TSEC2_NAME "eTSEC2"
483 #define TSEC1_PHY_ADDR 1
484 #define TSEC2_PHY_ADDR 2
486 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
487 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
489 #define TSEC1_PHYIDX 0
490 #define TSEC2_PHYIDX 0
492 #define CONFIG_ETHPRIME "eTSEC1"
496 * Dynamic MTD Partition support with mtdparts
502 #ifdef CONFIG_SPIFLASH
503 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
504 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
505 #define CONFIG_ENV_SECT_SIZE 0x10000
506 #elif defined(CONFIG_SDCARD)
507 #define CONFIG_FSL_FIXED_MMC_LOCATION
508 #define CONFIG_ENV_SIZE 0x2000
509 #define CONFIG_SYS_MMC_ENV_DEV 0
510 #elif defined(CONFIG_NAND)
511 #ifdef CONFIG_TPL_BUILD
512 #define CONFIG_ENV_SIZE 0x2000
513 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
515 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
517 #define CONFIG_ENV_OFFSET (1024 * 1024)
518 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
519 #elif defined(CONFIG_SYS_RAMBOOT)
520 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
521 #define CONFIG_ENV_SIZE 0x2000
523 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
524 #define CONFIG_ENV_SIZE 0x2000
525 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
528 #define CONFIG_LOADS_ECHO
529 #define CONFIG_SYS_LOADS_BAUD_CHANGE
534 #define CONFIG_HAS_FSL_DR_USB
535 #ifdef CONFIG_HAS_FSL_DR_USB
536 #ifdef CONFIG_USB_EHCI_HCD
537 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
538 #define CONFIG_USB_EHCI_FSL
543 * Miscellaneous configurable options
545 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
548 * For booting Linux, the board info and command line data
549 * have to be in the first 64 MB of memory, since this is
550 * the maximum mapped by the Linux kernel during initialization.
552 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
553 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
555 #ifdef CONFIG_CMD_KGDB
556 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
560 * Environment Configuration
563 #define CONFIG_HOSTNAME "p1022ds"
564 #define CONFIG_ROOTPATH "/opt/nfsroot"
565 #define CONFIG_BOOTFILE "uImage"
566 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
568 #define CONFIG_LOADADDR 1000000
570 #define CONFIG_EXTRA_ENV_SETTINGS \
572 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
573 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
574 "tftpflash=tftpboot $loadaddr $uboot && " \
575 "protect off $ubootaddr +$filesize && " \
576 "erase $ubootaddr +$filesize && " \
577 "cp.b $loadaddr $ubootaddr $filesize && " \
578 "protect on $ubootaddr +$filesize && " \
579 "cmp.b $loadaddr $ubootaddr $filesize\0" \
580 "consoledev=ttyS0\0" \
581 "ramdiskaddr=2000000\0" \
582 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
583 "fdtaddr=1e00000\0" \
584 "fdtfile=p1022ds.dtb\0" \
586 "hwconfig=esdhc;audclk:12\0"
588 #define CONFIG_HDBOOT \
589 "setenv bootargs root=/dev/$bdev rw " \
590 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
591 "tftp $loadaddr $bootfile;" \
592 "tftp $fdtaddr $fdtfile;" \
593 "bootm $loadaddr - $fdtaddr"
595 #define CONFIG_NFSBOOTCOMMAND \
596 "setenv bootargs root=/dev/nfs rw " \
597 "nfsroot=$serverip:$rootpath " \
598 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
599 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
600 "tftp $loadaddr $bootfile;" \
601 "tftp $fdtaddr $fdtfile;" \
602 "bootm $loadaddr - $fdtaddr"
604 #define CONFIG_RAMBOOTCOMMAND \
605 "setenv bootargs root=/dev/ram rw " \
606 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
607 "tftp $ramdiskaddr $ramdiskfile;" \
608 "tftp $loadaddr $bootfile;" \
609 "tftp $fdtaddr $fdtfile;" \
610 "bootm $loadaddr $ramdiskaddr $fdtaddr"
612 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND