6ddf4470b1879e890975da4de2f39046b45f2c00
[platform/kernel/u-boot.git] / include / configs / P1022DS.h
1 /*
2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4  *          Timur Tabi <timur@freescale.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #include "../board/freescale/common/ics307_clk.h"
13
14 #define CONFIG_SYS_GENERIC_BOARD
15 #define CONFIG_DISPLAY_BOARDINFO
16
17 #ifdef CONFIG_36BIT
18 #define CONFIG_PHYS_64BIT
19 #endif
20
21 #ifdef CONFIG_SDCARD
22 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
23 #define CONFIG_SPL_ENV_SUPPORT
24 #define CONFIG_SPL_SERIAL_SUPPORT
25 #define CONFIG_SPL_MMC_SUPPORT
26 #define CONFIG_SPL_MMC_MINIMAL
27 #define CONFIG_SPL_FLUSH_IMAGE
28 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
29 #define CONFIG_SPL_LIBGENERIC_SUPPORT
30 #define CONFIG_SPL_LIBCOMMON_SUPPORT
31 #define CONFIG_SPL_I2C_SUPPORT
32 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
33 #define CONFIG_SYS_TEXT_BASE            0x11001000
34 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
35 #define CONFIG_SPL_PAD_TO               0x20000
36 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
37 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
38 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
39 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
40 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
42 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
43 #define CONFIG_SPL_MMC_BOOT
44 #ifdef CONFIG_SPL_BUILD
45 #define CONFIG_SPL_COMMON_INIT_DDR
46 #endif
47 #endif
48
49 #ifdef CONFIG_SPIFLASH
50 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
51 #define CONFIG_SPL_ENV_SUPPORT
52 #define CONFIG_SPL_SERIAL_SUPPORT
53 #define CONFIG_SPL_SPI_SUPPORT
54 #define CONFIG_SPL_SPI_FLASH_SUPPORT
55 #define CONFIG_SPL_SPI_FLASH_MINIMAL
56 #define CONFIG_SPL_FLUSH_IMAGE
57 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
58 #define CONFIG_SPL_LIBGENERIC_SUPPORT
59 #define CONFIG_SPL_LIBCOMMON_SUPPORT
60 #define CONFIG_SPL_I2C_SUPPORT
61 #define CONFIG_FSL_LAW          /* Use common FSL init code */
62 #define CONFIG_SYS_TEXT_BASE            0x11001000
63 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
64 #define CONFIG_SPL_PAD_TO               0x20000
65 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
71 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
72 #define CONFIG_SPL_SPI_BOOT
73 #ifdef CONFIG_SPL_BUILD
74 #define CONFIG_SPL_COMMON_INIT_DDR
75 #endif
76 #endif
77
78 #define CONFIG_NAND_FSL_ELBC
79 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
80 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
81
82 #ifdef CONFIG_NAND
83 #ifdef CONFIG_TPL_BUILD
84 #define CONFIG_SPL_NAND_BOOT
85 #define CONFIG_SPL_FLUSH_IMAGE
86 #define CONFIG_SPL_ENV_SUPPORT
87 #define CONFIG_SPL_NAND_INIT
88 #define CONFIG_SPL_SERIAL_SUPPORT
89 #define CONFIG_SPL_LIBGENERIC_SUPPORT
90 #define CONFIG_SPL_LIBCOMMON_SUPPORT
91 #define CONFIG_SPL_I2C_SUPPORT
92 #define CONFIG_SPL_NAND_SUPPORT
93 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
94 #define CONFIG_SPL_COMMON_INIT_DDR
95 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
96 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
97 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
98 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
99 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
100 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
101 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
102 #elif defined(CONFIG_SPL_BUILD)
103 #define CONFIG_SPL_INIT_MINIMAL
104 #define CONFIG_SPL_SERIAL_SUPPORT
105 #define CONFIG_SPL_NAND_SUPPORT
106 #define CONFIG_SPL_FLUSH_IMAGE
107 #define CONFIG_SPL_TEXT_BASE            0xff800000
108 #define CONFIG_SPL_MAX_SIZE             4096
109 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
110 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
111 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
112 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
113 #endif
114 #define CONFIG_SPL_PAD_TO               0x20000
115 #define CONFIG_TPL_PAD_TO               0x20000
116 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
117 #define CONFIG_SYS_TEXT_BASE            0x11001000
118 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
119 #endif
120
121 /* High Level Configuration Options */
122 #define CONFIG_BOOKE                    /* BOOKE */
123 #define CONFIG_E500                     /* BOOKE e500 family */
124 #define CONFIG_P1022
125 #define CONFIG_P1022DS
126 #define CONFIG_MP                       /* support multiple processors */
127
128 #ifndef CONFIG_SYS_TEXT_BASE
129 #define CONFIG_SYS_TEXT_BASE    0xeff40000
130 #endif
131
132 #ifndef CONFIG_RESET_VECTOR_ADDRESS
133 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
134 #endif
135
136 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
137 #define CONFIG_PCI                      /* Enable PCI/PCIE */
138 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
139 #define CONFIG_PCIE2                    /* PCIE controler 2 (slot 2) */
140 #define CONFIG_PCIE3                    /* PCIE controler 3 (ULI bridge) */
141 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
142 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
143 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
144
145 #define CONFIG_ENABLE_36BIT_PHYS
146
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_ADDR_MAP
149 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
150 #endif
151
152 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
153
154 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
155 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
156 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
157
158 /*
159  * These can be toggled for performance analysis, otherwise use default.
160  */
161 #define CONFIG_L2_CACHE
162 #define CONFIG_BTB
163
164 #define CONFIG_SYS_MEMTEST_START        0x00000000
165 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
166
167 #define CONFIG_SYS_CCSRBAR              0xffe00000
168 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
169
170 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
171        SPL code*/
172 #ifdef CONFIG_SPL_BUILD
173 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
174 #endif
175
176
177 /* DDR Setup */
178 #define CONFIG_DDR_SPD
179 #define CONFIG_VERY_BIG_RAM
180 #define CONFIG_SYS_FSL_DDR3
181
182 #ifdef CONFIG_DDR_ECC
183 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
184 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
185 #endif
186
187 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
188 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
189
190 #define CONFIG_NUM_DDR_CONTROLLERS      1
191 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
192 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
193
194 /* I2C addresses of SPD EEPROMs */
195 #define CONFIG_SYS_SPD_BUS_NUM          1
196 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
197
198 /* These are used when DDR doesn't use SPD.  */
199 #define CONFIG_SYS_SDRAM_SIZE           2048
200 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
201 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
202 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
203 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
204 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
205 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
206 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
207 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
208 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
209 #define CONFIG_SYS_DDR_MODE_1           0x00441221
210 #define CONFIG_SYS_DDR_MODE_2           0x00000000
211 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
212 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
213 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
214 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
215 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
216 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
217 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
218 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
219 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
220
221
222 /*
223  * Memory map
224  *
225  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
226  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
227  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
228  *
229  * Localbus cacheable (TBD)
230  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
231  *
232  * Localbus non-cacheable
233  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
234  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
235  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
236  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
237  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
238  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
239  */
240
241 /*
242  * Local Bus Definitions
243  */
244 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
245 #ifdef CONFIG_PHYS_64BIT
246 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
247 #else
248 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
249 #endif
250
251 #define CONFIG_FLASH_BR_PRELIM  \
252         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
253 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
254
255 #ifdef CONFIG_NAND
256 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
257 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
258 #else
259 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
260 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
261 #endif
262
263 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
264 #define CONFIG_SYS_FLASH_QUIET_TEST
265 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
266
267 #define CONFIG_SYS_MAX_FLASH_BANKS      1
268 #define CONFIG_SYS_MAX_FLASH_SECT       1024
269
270 #ifndef CONFIG_SYS_MONITOR_BASE
271 #ifdef CONFIG_SPL_BUILD
272 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
273 #else
274 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
275 #endif
276 #endif
277
278 #define CONFIG_FLASH_CFI_DRIVER
279 #define CONFIG_SYS_FLASH_CFI
280 #define CONFIG_SYS_FLASH_EMPTY_INFO
281
282 /* Nand Flash */
283 #if defined(CONFIG_NAND_FSL_ELBC)
284 #define CONFIG_SYS_NAND_BASE            0xff800000
285 #ifdef CONFIG_PHYS_64BIT
286 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
287 #else
288 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
289 #endif
290
291 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
292 #define CONFIG_SYS_MAX_NAND_DEVICE      1
293 #define CONFIG_CMD_NAND                 1
294 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
295 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
296
297 /* NAND flash config */
298 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
299                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
300                                | BR_PS_8               /* Port Size = 8 bit */ \
301                                | BR_MS_FCM             /* MSEL = FCM */ \
302                                | BR_V)                 /* valid */
303 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
304                                | OR_FCM_PGS            /* Large Page*/ \
305                                | OR_FCM_CSCT \
306                                | OR_FCM_CST \
307                                | OR_FCM_CHT \
308                                | OR_FCM_SCY_1 \
309                                | OR_FCM_TRLX \
310                                | OR_FCM_EHTR)
311 #ifdef CONFIG_NAND
312 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
313 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
314 #else
315 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
316 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
317 #endif
318
319 #endif /* CONFIG_NAND_FSL_ELBC */
320
321 #define CONFIG_BOARD_EARLY_INIT_F
322 #define CONFIG_BOARD_EARLY_INIT_R
323 #define CONFIG_MISC_INIT_R
324 #define CONFIG_HWCONFIG
325
326 #define CONFIG_FSL_NGPIXIS
327 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
328 #ifdef CONFIG_PHYS_64BIT
329 #define PIXIS_BASE_PHYS         0xfffdf0000ull
330 #else
331 #define PIXIS_BASE_PHYS         PIXIS_BASE
332 #endif
333
334 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
335 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
336
337 #define PIXIS_LBMAP_SWITCH      7
338 #define PIXIS_LBMAP_MASK        0xF0
339 #define PIXIS_LBMAP_ALTBANK     0x20
340 #define PIXIS_SPD               0x07
341 #define PIXIS_SPD_SYSCLK_MASK   0x07
342 #define PIXIS_ELBC_SPI_MASK     0xc0
343 #define PIXIS_SPI               0x80
344
345 #define CONFIG_SYS_INIT_RAM_LOCK
346 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
347 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
348
349 #define CONFIG_SYS_GBL_DATA_OFFSET      \
350         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
351 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
352
353 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
354 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
355
356 /*
357  * Config the L2 Cache as L2 SRAM
358 */
359 #if defined(CONFIG_SPL_BUILD)
360 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
361 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
362 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
363 #define CONFIG_SYS_L2_SIZE              (256 << 10)
364 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
365 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
366 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
367 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
368 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
369 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
370 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
371 #elif defined(CONFIG_NAND)
372 #ifdef CONFIG_TPL_BUILD
373 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
374 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
375 #define CONFIG_SYS_L2_SIZE              (256 << 10)
376 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
377 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
378 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
379 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
380 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
381 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
382 #else
383 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
384 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
385 #define CONFIG_SYS_L2_SIZE              (256 << 10)
386 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
387 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
388 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
389 #endif
390 #endif
391 #endif
392
393 /*
394  * Serial Port
395  */
396 #define CONFIG_CONS_INDEX               1
397 #define CONFIG_SYS_NS16550
398 #define CONFIG_SYS_NS16550_SERIAL
399 #define CONFIG_SYS_NS16550_REG_SIZE     1
400 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
401 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
402 #define CONFIG_NS16550_MIN_FUNCTIONS
403 #endif
404
405 #define CONFIG_SYS_BAUDRATE_TABLE       \
406         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
407
408 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
409 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
410
411 /* Use the HUSH parser */
412 #define CONFIG_SYS_HUSH_PARSER
413
414 /* Video */
415
416 #ifdef CONFIG_FSL_DIU_FB
417 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
418 #define CONFIG_VIDEO
419 #define CONFIG_CMD_BMP
420 #define CONFIG_CFB_CONSOLE
421 #define CONFIG_VIDEO_SW_CURSOR
422 #define CONFIG_VGA_AS_SINGLE_DEVICE
423 #define CONFIG_VIDEO_LOGO
424 #define CONFIG_VIDEO_BMP_LOGO
425 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
426 /*
427  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
428  * disable empty flash sector detection, which is I/O-intensive.
429  */
430 #undef CONFIG_SYS_FLASH_EMPTY_INFO
431 #endif
432
433 #ifndef CONFIG_FSL_DIU_FB
434 #endif
435
436 #ifdef CONFIG_ATI
437 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
438 #define CONFIG_VIDEO
439 #define CONFIG_BIOSEMU
440 #define CONFIG_VIDEO_SW_CURSOR
441 #define CONFIG_ATI_RADEON_FB
442 #define CONFIG_VIDEO_LOGO
443 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
444 #define CONFIG_CFB_CONSOLE
445 #define CONFIG_VGA_AS_SINGLE_DEVICE
446 #endif
447
448 /*
449  * Pass open firmware flat tree
450  */
451 #define CONFIG_OF_LIBFDT
452 #define CONFIG_OF_BOARD_SETUP
453 #define CONFIG_OF_STDOUT_VIA_ALIAS
454
455 /* new uImage format support */
456 #define CONFIG_FIT
457 #define CONFIG_FIT_VERBOSE
458
459 /* I2C */
460 #define CONFIG_SYS_I2C
461 #define CONFIG_SYS_I2C_FSL
462 #define CONFIG_SYS_FSL_I2C_SPEED        400000
463 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
464 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
465 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
466 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
467 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
468 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
469
470 /*
471  * I2C2 EEPROM
472  */
473 #define CONFIG_ID_EEPROM
474 #define CONFIG_SYS_I2C_EEPROM_NXID
475 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
476 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
477 #define CONFIG_SYS_EEPROM_BUS_NUM       1
478
479 /*
480  * eSPI - Enhanced SPI
481  */
482 #define CONFIG_SPI_FLASH_SPANSION
483
484 #define CONFIG_HARD_SPI
485 #define CONFIG_FSL_ESPI
486
487 #define CONFIG_CMD_SF
488 #define CONFIG_SF_DEFAULT_SPEED         10000000
489 #define CONFIG_SF_DEFAULT_MODE          0
490
491 /*
492  * General PCI
493  * Memory space is mapped 1-1, but I/O space must start from 0.
494  */
495
496 /* controller 1, Slot 2, tgtid 1, Base address a000 */
497 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
498 #ifdef CONFIG_PHYS_64BIT
499 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
500 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
501 #else
502 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
503 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
504 #endif
505 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
506 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
507 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
508 #ifdef CONFIG_PHYS_64BIT
509 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
510 #else
511 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
512 #endif
513 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
514
515 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
516 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
517 #ifdef CONFIG_PHYS_64BIT
518 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
519 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
520 #else
521 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
522 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
523 #endif
524 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
525 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
526 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
527 #ifdef CONFIG_PHYS_64BIT
528 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
529 #else
530 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
531 #endif
532 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
533
534 /* controller 3, Slot 1, tgtid 3, Base address b000 */
535 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
536 #ifdef CONFIG_PHYS_64BIT
537 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
538 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
539 #else
540 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
541 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
542 #endif
543 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
544 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
545 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
546 #ifdef CONFIG_PHYS_64BIT
547 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
548 #else
549 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
550 #endif
551 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
552
553 #ifdef CONFIG_PCI
554 #define CONFIG_PCI_INDIRECT_BRIDGE
555 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
556 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
557 #define CONFIG_E1000                    /* Define e1000 pci Ethernet card */
558 #endif
559
560 /* SATA */
561 #define CONFIG_LIBATA
562 #define CONFIG_FSL_SATA
563 #define CONFIG_FSL_SATA_V2
564
565 #define CONFIG_SYS_SATA_MAX_DEVICE      2
566 #define CONFIG_SATA1
567 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
568 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
569 #define CONFIG_SATA2
570 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
571 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
572
573 #ifdef CONFIG_FSL_SATA
574 #define CONFIG_LBA48
575 #define CONFIG_CMD_SATA
576 #define CONFIG_DOS_PARTITION
577 #define CONFIG_CMD_EXT2
578 #endif
579
580 #define CONFIG_MMC
581 #ifdef CONFIG_MMC
582 #define CONFIG_CMD_MMC
583 #define CONFIG_FSL_ESDHC
584 #define CONFIG_GENERIC_MMC
585 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
586 #endif
587
588 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
589 #define CONFIG_CMD_EXT2
590 #define CONFIG_CMD_FAT
591 #define CONFIG_DOS_PARTITION
592 #endif
593
594 #define CONFIG_TSEC_ENET
595 #ifdef CONFIG_TSEC_ENET
596
597 #define CONFIG_TSECV2
598
599 #define CONFIG_MII                      /* MII PHY management */
600 #define CONFIG_TSEC1            1
601 #define CONFIG_TSEC1_NAME       "eTSEC1"
602 #define CONFIG_TSEC2            1
603 #define CONFIG_TSEC2_NAME       "eTSEC2"
604
605 #define TSEC1_PHY_ADDR          1
606 #define TSEC2_PHY_ADDR          2
607
608 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
609 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
610
611 #define TSEC1_PHYIDX            0
612 #define TSEC2_PHYIDX            0
613
614 #define CONFIG_ETHPRIME         "eTSEC1"
615
616 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
617 #endif
618
619 /*
620  * Dynamic MTD Partition support with mtdparts
621  */
622 #define CONFIG_MTD_DEVICE
623 #define CONFIG_MTD_PARTITIONS
624 #define CONFIG_CMD_MTDPARTS
625 #define CONFIG_FLASH_CFI_MTD
626 #ifdef CONFIG_PHYS_64BIT
627 #define MTDIDS_DEFAULT "nor0=fe8000000.nor"
628 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
629                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
630                         "512k(dtb),768k(u-boot)"
631 #else
632 #define MTDIDS_DEFAULT "nor0=e8000000.nor"
633 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
634                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
635                         "512k(dtb),768k(u-boot)"
636 #endif
637
638 /*
639  * Environment
640  */
641 #ifdef CONFIG_SPIFLASH
642 #define CONFIG_ENV_IS_IN_SPI_FLASH
643 #define CONFIG_ENV_SPI_BUS      0
644 #define CONFIG_ENV_SPI_CS       0
645 #define CONFIG_ENV_SPI_MAX_HZ   10000000
646 #define CONFIG_ENV_SPI_MODE     0
647 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
648 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
649 #define CONFIG_ENV_SECT_SIZE    0x10000
650 #elif defined(CONFIG_SDCARD)
651 #define CONFIG_ENV_IS_IN_MMC
652 #define CONFIG_FSL_FIXED_MMC_LOCATION
653 #define CONFIG_ENV_SIZE         0x2000
654 #define CONFIG_SYS_MMC_ENV_DEV  0
655 #elif defined(CONFIG_NAND)
656 #ifdef CONFIG_TPL_BUILD
657 #define CONFIG_ENV_SIZE         0x2000
658 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
659 #else
660 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
661 #endif
662 #define CONFIG_ENV_IS_IN_NAND
663 #define CONFIG_ENV_OFFSET       (1024 * 1024)
664 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
665 #elif defined(CONFIG_SYS_RAMBOOT)
666 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
667 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
668 #define CONFIG_ENV_SIZE         0x2000
669 #else
670 #define CONFIG_ENV_IS_IN_FLASH
671 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
672 #define CONFIG_ENV_SIZE         0x2000
673 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
674 #endif
675
676 #define CONFIG_LOADS_ECHO
677 #define CONFIG_SYS_LOADS_BAUD_CHANGE
678
679 /*
680  * Command line configuration.
681  */
682 #define CONFIG_CMD_ELF
683 #define CONFIG_CMD_ERRATA
684 #define CONFIG_CMD_IRQ
685 #define CONFIG_CMD_I2C
686 #define CONFIG_CMD_MII
687 #define CONFIG_CMD_PING
688 #define CONFIG_CMD_REGINFO
689
690 #ifdef CONFIG_PCI
691 #define CONFIG_CMD_PCI
692 #endif
693
694 /*
695  * USB
696  */
697 #define CONFIG_HAS_FSL_DR_USB
698 #ifdef CONFIG_HAS_FSL_DR_USB
699 #define CONFIG_USB_EHCI
700
701 #ifdef CONFIG_USB_EHCI
702 #define CONFIG_CMD_USB
703 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
704 #define CONFIG_USB_EHCI_FSL
705 #define CONFIG_USB_STORAGE
706 #define CONFIG_CMD_FAT
707 #endif
708 #endif
709
710 /*
711  * Miscellaneous configurable options
712  */
713 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
714 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
715 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
716 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
717 #ifdef CONFIG_CMD_KGDB
718 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
719 #else
720 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
721 #endif
722 /* Print Buffer Size */
723 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
724 #define CONFIG_SYS_MAXARGS      16
725 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
726
727 /*
728  * For booting Linux, the board info and command line data
729  * have to be in the first 64 MB of memory, since this is
730  * the maximum mapped by the Linux kernel during initialization.
731  */
732 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
733 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
734
735 #ifdef CONFIG_CMD_KGDB
736 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
737 #endif
738
739 /*
740  * Environment Configuration
741  */
742
743 #define CONFIG_HOSTNAME         p1022ds
744 #define CONFIG_ROOTPATH         "/opt/nfsroot"
745 #define CONFIG_BOOTFILE         "uImage"
746 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
747
748 #define CONFIG_LOADADDR         1000000
749
750 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
751
752 #define CONFIG_BAUDRATE 115200
753
754 #define CONFIG_EXTRA_ENV_SETTINGS                               \
755         "netdev=eth0\0"                                         \
756         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
757         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
758         "tftpflash=tftpboot $loadaddr $uboot && "               \
759                 "protect off $ubootaddr +$filesize && "         \
760                 "erase $ubootaddr +$filesize && "               \
761                 "cp.b $loadaddr $ubootaddr $filesize && "       \
762                 "protect on $ubootaddr +$filesize && "          \
763                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
764         "consoledev=ttyS0\0"                                    \
765         "ramdiskaddr=2000000\0"                                 \
766         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
767         "fdtaddr=c00000\0"                                      \
768         "fdtfile=p1022ds.dtb\0"                                 \
769         "bdev=sda3\0"                                           \
770         "hwconfig=esdhc;audclk:12\0"
771
772 #define CONFIG_HDBOOT                                   \
773         "setenv bootargs root=/dev/$bdev rw "           \
774         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
775         "tftp $loadaddr $bootfile;"                     \
776         "tftp $fdtaddr $fdtfile;"                       \
777         "bootm $loadaddr - $fdtaddr"
778
779 #define CONFIG_NFSBOOTCOMMAND                                           \
780         "setenv bootargs root=/dev/nfs rw "                             \
781         "nfsroot=$serverip:$rootpath "                                  \
782         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
783         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
784         "tftp $loadaddr $bootfile;"                                     \
785         "tftp $fdtaddr $fdtfile;"                                       \
786         "bootm $loadaddr - $fdtaddr"
787
788 #define CONFIG_RAMBOOTCOMMAND                                           \
789         "setenv bootargs root=/dev/ram rw "                             \
790         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
791         "tftp $ramdiskaddr $ramdiskfile;"                               \
792         "tftp $loadaddr $bootfile;"                                     \
793         "tftp $fdtaddr $fdtfile;"                                       \
794         "bootm $loadaddr $ramdiskaddr $fdtaddr"
795
796 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
797
798 #endif