1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5 * Timur Tabi <timur@freescale.com>
11 #include "../board/freescale/common/ics307_clk.h"
14 #define CONFIG_SPL_FLUSH_IMAGE
15 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
16 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
17 #define CONFIG_SPL_PAD_TO 0x20000
18 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
19 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
20 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
23 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
24 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
25 #define CONFIG_SPL_MMC_BOOT
26 #ifdef CONFIG_SPL_BUILD
27 #define CONFIG_SPL_COMMON_INIT_DDR
31 #ifdef CONFIG_SPIFLASH
32 #define CONFIG_SPL_SPI_FLASH_MINIMAL
33 #define CONFIG_SPL_FLUSH_IMAGE
34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
36 #define CONFIG_SPL_PAD_TO 0x20000
37 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
42 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
44 #define CONFIG_SPL_SPI_BOOT
45 #ifdef CONFIG_SPL_BUILD
46 #define CONFIG_SPL_COMMON_INIT_DDR
50 #define CONFIG_NAND_FSL_ELBC
51 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
52 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
55 #ifdef CONFIG_TPL_BUILD
56 #define CONFIG_SPL_NAND_BOOT
57 #define CONFIG_SPL_FLUSH_IMAGE
58 #define CONFIG_SPL_NAND_INIT
59 #define CONFIG_SPL_COMMON_INIT_DDR
60 #define CONFIG_SPL_MAX_SIZE (128 << 10)
61 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
63 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
64 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
65 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
66 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
67 #elif defined(CONFIG_SPL_BUILD)
68 #define CONFIG_SPL_INIT_MINIMAL
69 #define CONFIG_SPL_FLUSH_IMAGE
70 #define CONFIG_SPL_TEXT_BASE 0xff800000
71 #define CONFIG_SPL_MAX_SIZE 4096
72 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
73 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
74 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
75 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
77 #define CONFIG_SPL_PAD_TO 0x20000
78 #define CONFIG_TPL_PAD_TO 0x20000
79 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
83 /* High Level Configuration Options */
84 #define CONFIG_MP /* support multiple processors */
86 #ifndef CONFIG_RESET_VECTOR_ADDRESS
87 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
90 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
91 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
92 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
93 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
94 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
95 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
97 #define CONFIG_ENABLE_36BIT_PHYS
99 #ifdef CONFIG_PHYS_64BIT
100 #define CONFIG_ADDR_MAP
101 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
104 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
105 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
106 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
109 * These can be toggled for performance analysis, otherwise use default.
111 #define CONFIG_L2_CACHE
114 #define CONFIG_SYS_MEMTEST_START 0x00000000
115 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
117 #define CONFIG_SYS_CCSRBAR 0xffe00000
118 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
120 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
122 #ifdef CONFIG_SPL_BUILD
123 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
127 #define CONFIG_DDR_SPD
128 #define CONFIG_VERY_BIG_RAM
130 #ifdef CONFIG_DDR_ECC
131 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
132 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
135 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
136 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
138 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
139 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
141 /* I2C addresses of SPD EEPROMs */
142 #define CONFIG_SYS_SPD_BUS_NUM 1
143 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
145 /* These are used when DDR doesn't use SPD. */
146 #define CONFIG_SYS_SDRAM_SIZE 2048
147 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
148 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
149 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
150 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
151 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
152 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
153 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
154 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
155 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
156 #define CONFIG_SYS_DDR_MODE_1 0x00441221
157 #define CONFIG_SYS_DDR_MODE_2 0x00000000
158 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
159 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
160 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
161 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
162 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
163 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
164 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
165 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
166 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
171 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
172 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
173 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
175 * Localbus cacheable (TBD)
176 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
178 * Localbus non-cacheable
179 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
180 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
181 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
182 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
183 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
184 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
188 * Local Bus Definitions
190 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
191 #ifdef CONFIG_PHYS_64BIT
192 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
194 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
197 #define CONFIG_FLASH_BR_PRELIM \
198 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
199 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
202 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
203 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
205 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
206 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
209 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
210 #define CONFIG_SYS_FLASH_QUIET_TEST
211 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
213 #define CONFIG_SYS_MAX_FLASH_BANKS 1
214 #define CONFIG_SYS_MAX_FLASH_SECT 1024
216 #ifndef CONFIG_SYS_MONITOR_BASE
217 #ifdef CONFIG_SPL_BUILD
218 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
224 #define CONFIG_FLASH_CFI_DRIVER
225 #define CONFIG_SYS_FLASH_CFI
226 #define CONFIG_SYS_FLASH_EMPTY_INFO
229 #if defined(CONFIG_NAND_FSL_ELBC)
230 #define CONFIG_SYS_NAND_BASE 0xff800000
231 #ifdef CONFIG_PHYS_64BIT
232 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
234 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
237 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
238 #define CONFIG_SYS_MAX_NAND_DEVICE 1
239 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
240 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
242 /* NAND flash config */
243 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
244 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
245 | BR_PS_8 /* Port Size = 8 bit */ \
246 | BR_MS_FCM /* MSEL = FCM */ \
248 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
249 | OR_FCM_PGS /* Large Page*/ \
257 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
258 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
260 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
261 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
264 #endif /* CONFIG_NAND_FSL_ELBC */
266 #define CONFIG_MISC_INIT_R
267 #define CONFIG_HWCONFIG
269 #define CONFIG_FSL_NGPIXIS
270 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
271 #ifdef CONFIG_PHYS_64BIT
272 #define PIXIS_BASE_PHYS 0xfffdf0000ull
274 #define PIXIS_BASE_PHYS PIXIS_BASE
277 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
278 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
280 #define PIXIS_LBMAP_SWITCH 7
281 #define PIXIS_LBMAP_MASK 0xF0
282 #define PIXIS_LBMAP_ALTBANK 0x20
283 #define PIXIS_SPD 0x07
284 #define PIXIS_SPD_SYSCLK_MASK 0x07
285 #define PIXIS_ELBC_SPI_MASK 0xc0
286 #define PIXIS_SPI 0x80
288 #define CONFIG_SYS_INIT_RAM_LOCK
289 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
290 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
292 #define CONFIG_SYS_GBL_DATA_OFFSET \
293 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
294 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
296 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
297 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
300 * Config the L2 Cache as L2 SRAM
302 #if defined(CONFIG_SPL_BUILD)
303 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
304 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
305 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
306 #define CONFIG_SYS_L2_SIZE (256 << 10)
307 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
308 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
309 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
310 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
311 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
312 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
313 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
314 #elif defined(CONFIG_NAND)
315 #ifdef CONFIG_TPL_BUILD
316 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
317 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
318 #define CONFIG_SYS_L2_SIZE (256 << 10)
319 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
320 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
321 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
322 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
323 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
324 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
326 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
327 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
328 #define CONFIG_SYS_L2_SIZE (256 << 10)
329 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
330 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
331 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
339 #define CONFIG_SYS_NS16550_SERIAL
340 #define CONFIG_SYS_NS16550_REG_SIZE 1
341 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
342 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
343 #define CONFIG_NS16550_MIN_FUNCTIONS
346 #define CONFIG_SYS_BAUDRATE_TABLE \
347 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
349 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
350 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
354 #ifdef CONFIG_FSL_DIU_FB
355 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
356 #define CONFIG_VIDEO_LOGO
357 #define CONFIG_VIDEO_BMP_LOGO
358 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
360 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
361 * disable empty flash sector detection, which is I/O-intensive.
363 #undef CONFIG_SYS_FLASH_EMPTY_INFO
366 #ifndef CONFIG_FSL_DIU_FB
370 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
371 #define CONFIG_BIOSEMU
372 #define CONFIG_ATI_RADEON_FB
373 #define CONFIG_VIDEO_LOGO
374 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
378 #define CONFIG_SYS_I2C
379 #define CONFIG_SYS_I2C_FSL
380 #define CONFIG_SYS_FSL_I2C_SPEED 400000
381 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
382 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
383 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
384 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
385 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
386 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
391 #define CONFIG_ID_EEPROM
392 #define CONFIG_SYS_I2C_EEPROM_NXID
393 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
394 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
395 #define CONFIG_SYS_EEPROM_BUS_NUM 1
398 * eSPI - Enhanced SPI
401 #define CONFIG_HARD_SPI
403 #define CONFIG_SF_DEFAULT_SPEED 10000000
404 #define CONFIG_SF_DEFAULT_MODE 0
408 * Memory space is mapped 1-1, but I/O space must start from 0.
411 /* controller 1, Slot 2, tgtid 1, Base address a000 */
412 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
413 #ifdef CONFIG_PHYS_64BIT
414 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
415 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
417 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
418 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
420 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
421 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
422 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
423 #ifdef CONFIG_PHYS_64BIT
424 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
426 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
428 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
430 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
431 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
432 #ifdef CONFIG_PHYS_64BIT
433 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
434 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
436 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
437 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
439 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
440 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
441 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
442 #ifdef CONFIG_PHYS_64BIT
443 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
445 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
447 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
449 /* controller 3, Slot 1, tgtid 3, Base address b000 */
450 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
451 #ifdef CONFIG_PHYS_64BIT
452 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
453 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
455 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
456 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
458 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
459 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
460 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
461 #ifdef CONFIG_PHYS_64BIT
462 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
464 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
466 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
469 #define CONFIG_PCI_INDIRECT_BRIDGE
470 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
474 #define CONFIG_FSL_SATA_V2
476 #define CONFIG_SYS_SATA_MAX_DEVICE 2
478 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
479 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
481 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
482 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
484 #ifdef CONFIG_FSL_SATA
489 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
492 #ifdef CONFIG_TSEC_ENET
494 #define CONFIG_TSECV2
496 #define CONFIG_MII /* MII PHY management */
497 #define CONFIG_TSEC1 1
498 #define CONFIG_TSEC1_NAME "eTSEC1"
499 #define CONFIG_TSEC2 1
500 #define CONFIG_TSEC2_NAME "eTSEC2"
502 #define TSEC1_PHY_ADDR 1
503 #define TSEC2_PHY_ADDR 2
505 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
506 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
508 #define TSEC1_PHYIDX 0
509 #define TSEC2_PHYIDX 0
511 #define CONFIG_ETHPRIME "eTSEC1"
515 * Dynamic MTD Partition support with mtdparts
517 #define CONFIG_MTD_DEVICE
518 #define CONFIG_MTD_PARTITIONS
519 #define CONFIG_FLASH_CFI_MTD
524 #ifdef CONFIG_SPIFLASH
525 #define CONFIG_ENV_SPI_BUS 0
526 #define CONFIG_ENV_SPI_CS 0
527 #define CONFIG_ENV_SPI_MAX_HZ 10000000
528 #define CONFIG_ENV_SPI_MODE 0
529 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
530 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
531 #define CONFIG_ENV_SECT_SIZE 0x10000
532 #elif defined(CONFIG_SDCARD)
533 #define CONFIG_FSL_FIXED_MMC_LOCATION
534 #define CONFIG_ENV_SIZE 0x2000
535 #define CONFIG_SYS_MMC_ENV_DEV 0
536 #elif defined(CONFIG_NAND)
537 #ifdef CONFIG_TPL_BUILD
538 #define CONFIG_ENV_SIZE 0x2000
539 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
541 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
543 #define CONFIG_ENV_OFFSET (1024 * 1024)
544 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
545 #elif defined(CONFIG_SYS_RAMBOOT)
546 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
547 #define CONFIG_ENV_SIZE 0x2000
549 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
550 #define CONFIG_ENV_SIZE 0x2000
551 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
554 #define CONFIG_LOADS_ECHO
555 #define CONFIG_SYS_LOADS_BAUD_CHANGE
560 #define CONFIG_HAS_FSL_DR_USB
561 #ifdef CONFIG_HAS_FSL_DR_USB
562 #ifdef CONFIG_USB_EHCI_HCD
563 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
564 #define CONFIG_USB_EHCI_FSL
569 * Miscellaneous configurable options
571 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
574 * For booting Linux, the board info and command line data
575 * have to be in the first 64 MB of memory, since this is
576 * the maximum mapped by the Linux kernel during initialization.
578 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
579 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
581 #ifdef CONFIG_CMD_KGDB
582 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
586 * Environment Configuration
589 #define CONFIG_HOSTNAME "p1022ds"
590 #define CONFIG_ROOTPATH "/opt/nfsroot"
591 #define CONFIG_BOOTFILE "uImage"
592 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
594 #define CONFIG_LOADADDR 1000000
596 #define CONFIG_EXTRA_ENV_SETTINGS \
598 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
599 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
600 "tftpflash=tftpboot $loadaddr $uboot && " \
601 "protect off $ubootaddr +$filesize && " \
602 "erase $ubootaddr +$filesize && " \
603 "cp.b $loadaddr $ubootaddr $filesize && " \
604 "protect on $ubootaddr +$filesize && " \
605 "cmp.b $loadaddr $ubootaddr $filesize\0" \
606 "consoledev=ttyS0\0" \
607 "ramdiskaddr=2000000\0" \
608 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
609 "fdtaddr=1e00000\0" \
610 "fdtfile=p1022ds.dtb\0" \
612 "hwconfig=esdhc;audclk:12\0"
614 #define CONFIG_HDBOOT \
615 "setenv bootargs root=/dev/$bdev rw " \
616 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
617 "tftp $loadaddr $bootfile;" \
618 "tftp $fdtaddr $fdtfile;" \
619 "bootm $loadaddr - $fdtaddr"
621 #define CONFIG_NFSBOOTCOMMAND \
622 "setenv bootargs root=/dev/nfs rw " \
623 "nfsroot=$serverip:$rootpath " \
624 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
625 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
626 "tftp $loadaddr $bootfile;" \
627 "tftp $fdtaddr $fdtfile;" \
628 "bootm $loadaddr - $fdtaddr"
630 #define CONFIG_RAMBOOTCOMMAND \
631 "setenv bootargs root=/dev/ram rw " \
632 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
633 "tftp $ramdiskaddr $ramdiskfile;" \
634 "tftp $loadaddr $bootfile;" \
635 "tftp $fdtaddr $fdtfile;" \
636 "bootm $loadaddr $ramdiskaddr $fdtaddr"
638 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND