2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * P010 RDB board configuration file
15 #define CONFIG_PHYS_64BIT
17 #define CONFIG_DISPLAY_BOARDINFO
20 #define CONFIG_E500 /* BOOKE e500 family */
21 #include <asm/config_mpc85xx.h>
22 #define CONFIG_NAND_FSL_IFC
25 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
26 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
27 #define CONFIG_SPL_ENV_SUPPORT
28 #define CONFIG_SPL_SERIAL_SUPPORT
29 #define CONFIG_SPL_MMC_SUPPORT
30 #define CONFIG_SPL_MMC_MINIMAL
31 #define CONFIG_SPL_FLUSH_IMAGE
32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
33 #define CONFIG_SPL_LIBGENERIC_SUPPORT
34 #define CONFIG_SPL_LIBCOMMON_SUPPORT
35 #define CONFIG_SPL_I2C_SUPPORT
36 #define CONFIG_FSL_LAW /* Use common FSL init code */
37 #define CONFIG_SYS_TEXT_BASE 0x11001000
38 #define CONFIG_SPL_TEXT_BASE 0xD0001000
39 #define CONFIG_SPL_PAD_TO 0x18000
40 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
41 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
42 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
43 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
44 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
45 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
46 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
47 #define CONFIG_SPL_MMC_BOOT
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SPL_COMMON_INIT_DDR
53 #ifdef CONFIG_SPIFLASH
54 #ifdef CONFIG_SECURE_BOOT
55 #define CONFIG_RAMBOOT_SPIFLASH
56 #define CONFIG_SYS_TEXT_BASE 0x11000000
57 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
59 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
60 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
61 #define CONFIG_SPL_ENV_SUPPORT
62 #define CONFIG_SPL_SERIAL_SUPPORT
63 #define CONFIG_SPL_SPI_SUPPORT
64 #define CONFIG_SPL_SPI_FLASH_SUPPORT
65 #define CONFIG_SPL_SPI_FLASH_MINIMAL
66 #define CONFIG_SPL_FLUSH_IMAGE
67 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
68 #define CONFIG_SPL_LIBGENERIC_SUPPORT
69 #define CONFIG_SPL_LIBCOMMON_SUPPORT
70 #define CONFIG_SPL_I2C_SUPPORT
71 #define CONFIG_FSL_LAW /* Use common FSL init code */
72 #define CONFIG_SYS_TEXT_BASE 0x11001000
73 #define CONFIG_SPL_TEXT_BASE 0xD0001000
74 #define CONFIG_SPL_PAD_TO 0x18000
75 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
80 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
82 #define CONFIG_SPL_SPI_BOOT
83 #ifdef CONFIG_SPL_BUILD
84 #define CONFIG_SPL_COMMON_INIT_DDR
90 #ifdef CONFIG_SECURE_BOOT
91 #define CONFIG_SPL_INIT_MINIMAL
92 #define CONFIG_SPL_SERIAL_SUPPORT
93 #define CONFIG_SPL_NAND_SUPPORT
94 #define CONFIG_SPL_NAND_BOOT
95 #define CONFIG_SPL_FLUSH_IMAGE
96 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
98 #define CONFIG_SYS_TEXT_BASE 0x00201000
99 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
100 #define CONFIG_SPL_MAX_SIZE 8192
101 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
102 #define CONFIG_SPL_RELOC_STACK 0x00100000
103 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
104 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
105 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
106 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
107 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
109 #ifdef CONFIG_TPL_BUILD
110 #define CONFIG_SPL_NAND_BOOT
111 #define CONFIG_SPL_FLUSH_IMAGE
112 #define CONFIG_SPL_ENV_SUPPORT
113 #define CONFIG_SPL_NAND_INIT
114 #define CONFIG_SPL_SERIAL_SUPPORT
115 #define CONFIG_SPL_LIBGENERIC_SUPPORT
116 #define CONFIG_SPL_LIBCOMMON_SUPPORT
117 #define CONFIG_SPL_I2C_SUPPORT
118 #define CONFIG_SPL_NAND_SUPPORT
119 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
120 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
121 #define CONFIG_SPL_COMMON_INIT_DDR
122 #define CONFIG_SPL_MAX_SIZE (128 << 10)
123 #define CONFIG_SPL_TEXT_BASE 0xD0001000
124 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
125 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
126 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
127 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
128 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
129 #elif defined(CONFIG_SPL_BUILD)
130 #define CONFIG_SPL_INIT_MINIMAL
131 #define CONFIG_SPL_SERIAL_SUPPORT
132 #define CONFIG_SPL_NAND_SUPPORT
133 #define CONFIG_SPL_NAND_MINIMAL
134 #define CONFIG_SPL_FLUSH_IMAGE
135 #define CONFIG_SPL_TEXT_BASE 0xff800000
136 #define CONFIG_SPL_MAX_SIZE 8192
137 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
138 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
139 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
140 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
142 #define CONFIG_SPL_PAD_TO 0x20000
143 #define CONFIG_TPL_PAD_TO 0x20000
144 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
145 #define CONFIG_SYS_TEXT_BASE 0x11001000
146 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
150 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
151 #define CONFIG_RAMBOOT_NAND
152 #define CONFIG_SYS_TEXT_BASE 0x11000000
153 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
156 #ifndef CONFIG_SYS_TEXT_BASE
157 #define CONFIG_SYS_TEXT_BASE 0xeff40000
160 #ifndef CONFIG_RESET_VECTOR_ADDRESS
161 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
164 #ifdef CONFIG_SPL_BUILD
165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
170 /* High Level Configuration Options */
171 #define CONFIG_BOOKE /* BOOKE */
172 #define CONFIG_E500 /* BOOKE e500 family */
173 #define CONFIG_FSL_IFC /* Enable IFC Support */
174 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
175 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
177 #define CONFIG_PCI /* Enable PCI/PCIE */
178 #if defined(CONFIG_PCI)
179 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
180 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
181 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
182 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
183 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
184 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
186 #define CONFIG_CMD_PCI
191 * Memory space is mapped 1-1, but I/O space must start from 0.
193 /* controller 1, Slot 1, tgtid 1, Base address a000 */
194 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
195 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
196 #ifdef CONFIG_PHYS_64BIT
197 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
198 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
200 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
201 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
203 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
204 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
205 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
206 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
207 #ifdef CONFIG_PHYS_64BIT
208 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
210 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
213 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
214 #if defined(CONFIG_P1010RDB_PA)
215 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
216 #elif defined(CONFIG_P1010RDB_PB)
217 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
219 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
220 #ifdef CONFIG_PHYS_64BIT
221 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
222 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
224 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
225 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
227 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
228 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
229 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
230 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
231 #ifdef CONFIG_PHYS_64BIT
232 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
234 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
237 #define CONFIG_PCI_PNP /* do pci plug-and-play */
239 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
240 #define CONFIG_DOS_PARTITION
243 #define CONFIG_FSL_LAW /* Use common FSL init code */
244 #define CONFIG_TSEC_ENET
245 #define CONFIG_ENV_OVERWRITE
247 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
248 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
250 #define CONFIG_MISC_INIT_R
251 #define CONFIG_HWCONFIG
253 * These can be toggled for performance analysis, otherwise use default.
255 #define CONFIG_L2_CACHE /* toggle L2 cache */
256 #define CONFIG_BTB /* toggle branch predition */
258 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
260 #define CONFIG_ENABLE_36BIT_PHYS
262 #ifdef CONFIG_PHYS_64BIT
263 #define CONFIG_ADDR_MAP 1
264 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
267 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
268 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
269 #define CONFIG_PANIC_HANG /* do not reset board on panic */
272 #define CONFIG_SYS_FSL_DDR3
273 #define CONFIG_SYS_DDR_RAW_TIMING
274 #define CONFIG_DDR_SPD
275 #define CONFIG_SYS_SPD_BUS_NUM 1
276 #define SPD_EEPROM_ADDRESS 0x52
278 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
281 extern unsigned long get_sdram_size(void);
283 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
284 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
285 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
287 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
288 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
290 /* DDR3 Controller Settings */
291 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
292 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
293 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
294 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
295 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
296 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
297 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
298 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
299 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
300 #define CONFIG_SYS_DDR_RCW_1 0x00000000
301 #define CONFIG_SYS_DDR_RCW_2 0x00000000
302 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
303 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
304 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
305 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
307 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
308 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
309 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
310 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
311 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
312 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
313 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
314 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
315 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
317 /* settings for DDR3 at 667MT/s */
318 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
319 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
320 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
321 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
322 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
323 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
324 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
325 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
326 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
328 #define CONFIG_SYS_CCSRBAR 0xffe00000
329 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
331 /* Don't relocate CCSRBAR while in NAND_SPL */
332 #ifdef CONFIG_SPL_BUILD
333 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
339 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
340 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
341 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
343 * Localbus non-cacheable
344 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
345 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
346 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
347 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
353 /* NOR Flash on IFC */
354 #ifdef CONFIG_SPL_BUILD
355 #define CONFIG_SYS_NO_FLASH
358 #define CONFIG_SYS_FLASH_BASE 0xee000000
359 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
361 #ifdef CONFIG_PHYS_64BIT
362 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
364 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
367 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
368 CSPR_PORT_SIZE_16 | \
371 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
372 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
373 /* NOR Flash Timing Params */
374 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
375 FTIM0_NOR_TEADC(0x5) | \
377 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
378 FTIM1_NOR_TRAD_NOR(0x0f)
379 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
380 FTIM2_NOR_TCH(0x4) | \
382 #define CONFIG_SYS_NOR_FTIM3 0x0
384 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
385 #define CONFIG_SYS_FLASH_QUIET_TEST
386 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
387 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
389 #undef CONFIG_SYS_FLASH_CHECKSUM
390 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
391 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
393 /* CFI for NOR Flash */
394 #define CONFIG_FLASH_CFI_DRIVER
395 #define CONFIG_SYS_FLASH_CFI
396 #define CONFIG_SYS_FLASH_EMPTY_INFO
397 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
399 /* NAND Flash on IFC */
400 #define CONFIG_SYS_NAND_BASE 0xff800000
401 #ifdef CONFIG_PHYS_64BIT
402 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
404 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
407 #define CONFIG_MTD_DEVICE
408 #define CONFIG_MTD_PARTITION
409 #define CONFIG_CMD_MTDPARTS
410 #define MTDIDS_DEFAULT "nand0=ff800000.flash"
411 #define MTDPARTS_DEFAULT \
412 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
414 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
418 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
420 #if defined(CONFIG_P1010RDB_PA)
421 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
422 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
423 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
424 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
425 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
426 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
427 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
428 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
430 #elif defined(CONFIG_P1010RDB_PB)
431 #define CONFIG_SYS_NAND_ONFI_DETECTION
432 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
433 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
434 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
435 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
436 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
437 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
438 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
439 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
442 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
443 #define CONFIG_SYS_MAX_NAND_DEVICE 1
444 #define CONFIG_CMD_NAND
446 #if defined(CONFIG_P1010RDB_PA)
447 /* NAND Flash Timing Params */
448 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
449 FTIM0_NAND_TWP(0x0C) | \
450 FTIM0_NAND_TWCHT(0x04) | \
452 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
453 FTIM1_NAND_TWBE(0x1d) | \
454 FTIM1_NAND_TRR(0x07) | \
456 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
457 FTIM2_NAND_TREH(0x05) | \
458 FTIM2_NAND_TWHRE(0x0f)
459 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
461 #elif defined(CONFIG_P1010RDB_PB)
462 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
463 /* ONFI NAND Flash mode0 Timing Params */
464 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
465 FTIM0_NAND_TWP(0x18) | \
466 FTIM0_NAND_TWCHT(0x07) | \
467 FTIM0_NAND_TWH(0x0a))
468 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
469 FTIM1_NAND_TWBE(0x39) | \
470 FTIM1_NAND_TRR(0x0e) | \
471 FTIM1_NAND_TRP(0x18))
472 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
473 FTIM2_NAND_TREH(0x0a) | \
474 FTIM2_NAND_TWHRE(0x1e))
475 #define CONFIG_SYS_NAND_FTIM3 0x0
478 #define CONFIG_SYS_NAND_DDR_LAW 11
480 /* Set up IFC registers for boot location NOR/NAND */
481 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
482 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
483 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
484 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
485 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
486 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
487 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
488 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
489 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
490 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
491 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
492 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
493 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
494 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
495 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
497 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
498 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
499 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
500 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
501 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
502 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
503 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
504 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
505 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
506 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
507 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
508 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
509 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
510 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
514 #define CONFIG_SYS_CPLD_BASE 0xffb00000
516 #ifdef CONFIG_PHYS_64BIT
517 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
519 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
522 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
526 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
527 #define CONFIG_SYS_CSOR3 0x0
528 /* CPLD Timing parameters for IFC CS3 */
529 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
530 FTIM0_GPCM_TEADC(0x0e) | \
531 FTIM0_GPCM_TEAHC(0x0e))
532 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
533 FTIM1_GPCM_TRAD(0x1f))
534 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
535 FTIM2_GPCM_TCH(0x8) | \
536 FTIM2_GPCM_TWP(0x1f))
537 #define CONFIG_SYS_CS3_FTIM3 0x0
539 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
540 defined(CONFIG_RAMBOOT_NAND)
541 #define CONFIG_SYS_RAMBOOT
542 #define CONFIG_SYS_EXTRA_ENV_RELOC
544 #undef CONFIG_SYS_RAMBOOT
547 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
548 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
549 #define CONFIG_A003399_NOR_WORKAROUND
553 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
554 #define CONFIG_BOARD_EARLY_INIT_R
556 #define CONFIG_SYS_INIT_RAM_LOCK
557 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
558 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
560 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
561 - GENERATED_GBL_DATA_SIZE)
562 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
564 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
565 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
568 * Config the L2 Cache as L2 SRAM
570 #if defined(CONFIG_SPL_BUILD)
571 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
572 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
573 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
574 #define CONFIG_SYS_L2_SIZE (256 << 10)
575 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
576 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
577 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
578 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
579 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
580 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
581 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
582 #elif defined(CONFIG_NAND)
583 #ifdef CONFIG_TPL_BUILD
584 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
585 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
586 #define CONFIG_SYS_L2_SIZE (256 << 10)
587 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
588 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
589 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
590 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
591 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
592 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
594 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
595 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
596 #define CONFIG_SYS_L2_SIZE (256 << 10)
597 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
598 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
599 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
605 #define CONFIG_CONS_INDEX 1
606 #undef CONFIG_SERIAL_SOFTWARE_FIFO
607 #define CONFIG_SYS_NS16550_SERIAL
608 #define CONFIG_SYS_NS16550_REG_SIZE 1
609 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
610 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
611 #define CONFIG_NS16550_MIN_FUNCTIONS
614 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
616 #define CONFIG_SYS_BAUDRATE_TABLE \
617 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
619 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
620 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
622 /* Use the HUSH parser */
623 #define CONFIG_SYS_HUSH_PARSER
626 * Pass open firmware flat tree
628 #define CONFIG_OF_LIBFDT
629 #define CONFIG_OF_BOARD_SETUP
630 #define CONFIG_OF_STDOUT_VIA_ALIAS
632 /* new uImage format support */
634 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
637 #define CONFIG_SYS_I2C
638 #define CONFIG_SYS_I2C_FSL
639 #define CONFIG_SYS_FSL_I2C_SPEED 400000
640 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
641 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
642 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
643 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
644 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
645 #define I2C_PCA9557_ADDR1 0x18
646 #define I2C_PCA9557_ADDR2 0x19
647 #define I2C_PCA9557_BUS_NUM 0
650 #if defined(CONFIG_P1010RDB_PB)
651 #define CONFIG_ID_EEPROM
652 #ifdef CONFIG_ID_EEPROM
653 #define CONFIG_SYS_I2C_EEPROM_NXID
655 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
656 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
657 #define CONFIG_SYS_EEPROM_BUS_NUM 0
658 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
660 /* enable read and write access to EEPROM */
661 #define CONFIG_CMD_EEPROM
662 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
663 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
664 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
667 #define CONFIG_RTC_PT7C4338
668 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
670 #define CONFIG_CMD_I2C
673 * SPI interface will not be available in case of NAND boot SPI CS0 will be
676 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
677 /* eSPI - Enhanced SPI */
678 #define CONFIG_FSL_ESPI
679 #define CONFIG_SPI_FLASH_SPANSION
680 #define CONFIG_CMD_SF
681 #define CONFIG_SF_DEFAULT_SPEED 10000000
682 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
685 #if defined(CONFIG_TSEC_ENET)
686 #define CONFIG_MII /* MII PHY management */
687 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
688 #define CONFIG_TSEC1 1
689 #define CONFIG_TSEC1_NAME "eTSEC1"
690 #define CONFIG_TSEC2 1
691 #define CONFIG_TSEC2_NAME "eTSEC2"
692 #define CONFIG_TSEC3 1
693 #define CONFIG_TSEC3_NAME "eTSEC3"
695 #define TSEC1_PHY_ADDR 1
696 #define TSEC2_PHY_ADDR 0
697 #define TSEC3_PHY_ADDR 2
699 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
700 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
701 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
703 #define TSEC1_PHYIDX 0
704 #define TSEC2_PHYIDX 0
705 #define TSEC3_PHYIDX 0
707 #define CONFIG_ETHPRIME "eTSEC1"
709 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
711 /* TBI PHY configuration for SGMII mode */
712 #define CONFIG_TSEC_TBICR_SETTINGS ( \
714 | TBICR_ANEG_ENABLE \
715 | TBICR_FULL_DUPLEX \
719 #endif /* CONFIG_TSEC_ENET */
723 #define CONFIG_FSL_SATA
724 #define CONFIG_FSL_SATA_V2
725 #define CONFIG_LIBATA
727 #ifdef CONFIG_FSL_SATA
728 #define CONFIG_SYS_SATA_MAX_DEVICE 2
730 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
731 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
733 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
734 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
736 #define CONFIG_CMD_SATA
738 #endif /* #ifdef CONFIG_FSL_SATA */
742 #define CONFIG_CMD_MMC
743 #define CONFIG_DOS_PARTITION
744 #define CONFIG_FSL_ESDHC
745 #define CONFIG_GENERIC_MMC
746 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
749 #define CONFIG_HAS_FSL_DR_USB
751 #if defined(CONFIG_HAS_FSL_DR_USB)
752 #define CONFIG_USB_EHCI
754 #ifdef CONFIG_USB_EHCI
755 #define CONFIG_CMD_USB
756 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
757 #define CONFIG_USB_EHCI_FSL
758 #define CONFIG_USB_STORAGE
765 #if defined(CONFIG_SDCARD)
766 #define CONFIG_ENV_IS_IN_MMC
767 #define CONFIG_FSL_FIXED_MMC_LOCATION
768 #define CONFIG_SYS_MMC_ENV_DEV 0
769 #define CONFIG_ENV_SIZE 0x2000
770 #elif defined(CONFIG_SPIFLASH)
771 #define CONFIG_ENV_IS_IN_SPI_FLASH
772 #define CONFIG_ENV_SPI_BUS 0
773 #define CONFIG_ENV_SPI_CS 0
774 #define CONFIG_ENV_SPI_MAX_HZ 10000000
775 #define CONFIG_ENV_SPI_MODE 0
776 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
777 #define CONFIG_ENV_SECT_SIZE 0x10000
778 #define CONFIG_ENV_SIZE 0x2000
779 #elif defined(CONFIG_NAND)
780 #define CONFIG_ENV_IS_IN_NAND
781 #ifdef CONFIG_TPL_BUILD
782 #define CONFIG_ENV_SIZE 0x2000
783 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
785 #if defined(CONFIG_P1010RDB_PA)
786 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
787 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
788 #elif defined(CONFIG_P1010RDB_PB)
789 #define CONFIG_ENV_SIZE (16 * 1024)
790 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
793 #define CONFIG_ENV_OFFSET (1024 * 1024)
794 #elif defined(CONFIG_SYS_RAMBOOT)
795 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
796 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
797 #define CONFIG_ENV_SIZE 0x2000
799 #define CONFIG_ENV_IS_IN_FLASH
800 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
801 #define CONFIG_ENV_SIZE 0x2000
802 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
805 #define CONFIG_LOADS_ECHO /* echo on for serial download */
806 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
809 * Command line configuration.
811 #define CONFIG_CMD_DATE
812 #define CONFIG_CMD_ERRATA
813 #define CONFIG_CMD_IRQ
814 #define CONFIG_CMD_MII
815 #define CONFIG_CMD_PING
816 #define CONFIG_CMD_REGINFO
818 #undef CONFIG_WATCHDOG /* watchdog disabled */
820 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
821 || defined(CONFIG_FSL_SATA)
822 #define CONFIG_CMD_EXT2
823 #define CONFIG_CMD_FAT
824 #define CONFIG_DOS_PARTITION
827 /* Hash command with SHA acceleration supported in hardware */
828 #ifdef CONFIG_FSL_CAAM
829 #define CONFIG_CMD_HASH
830 #define CONFIG_SHA_HW_ACCEL
834 * Miscellaneous configurable options
836 #define CONFIG_SYS_LONGHELP /* undef to save memory */
837 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
838 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
839 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
841 #if defined(CONFIG_CMD_KGDB)
842 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
844 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
846 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
847 /* Print Buffer Size */
848 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
849 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
852 * Internal Definitions
856 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
857 #define BOOTFLAG_WARM 0x02 /* Software reboot */
860 * For booting Linux, the board info and command line data
861 * have to be in the first 64 MB of memory, since this is
862 * the maximum mapped by the Linux kernel during initialization.
864 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
865 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
867 #if defined(CONFIG_CMD_KGDB)
868 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
872 * Environment Configuration
875 #if defined(CONFIG_TSEC_ENET)
876 #define CONFIG_HAS_ETH0
877 #define CONFIG_HAS_ETH1
878 #define CONFIG_HAS_ETH2
881 #define CONFIG_ROOTPATH "/opt/nfsroot"
882 #define CONFIG_BOOTFILE "uImage"
883 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
885 /* default location for tftp and bootm */
886 #define CONFIG_LOADADDR 1000000
888 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
889 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
891 #define CONFIG_BAUDRATE 115200
893 #define CONFIG_EXTRA_ENV_SETTINGS \
894 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
896 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
897 "loadaddr=1000000\0" \
898 "consoledev=ttyS0\0" \
899 "ramdiskaddr=2000000\0" \
900 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
902 "fdtfile=p1010rdb.dtb\0" \
904 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
905 "othbootargs=ramdisk_size=600000\0" \
906 "usbfatboot=setenv bootargs root=/dev/ram rw " \
907 "console=$consoledev,$baudrate $othbootargs; " \
909 "fatload usb 0:2 $loadaddr $bootfile;" \
910 "fatload usb 0:2 $fdtaddr $fdtfile;" \
911 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
912 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
913 "usbext2boot=setenv bootargs root=/dev/ram rw " \
914 "console=$consoledev,$baudrate $othbootargs; " \
916 "ext2load usb 0:4 $loadaddr $bootfile;" \
917 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
918 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
919 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
922 #if defined(CONFIG_P1010RDB_PA)
923 #define CONFIG_BOOTMODE \
924 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
925 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
926 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
927 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
928 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
929 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
931 #elif defined(CONFIG_P1010RDB_PB)
932 #define CONFIG_BOOTMODE \
933 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
934 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
935 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
936 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
937 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
938 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
939 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
940 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
941 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
942 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
945 #define CONFIG_RAMBOOTCOMMAND \
946 "setenv bootargs root=/dev/ram rw " \
947 "console=$consoledev,$baudrate $othbootargs; " \
948 "tftp $ramdiskaddr $ramdiskfile;" \
949 "tftp $loadaddr $bootfile;" \
950 "tftp $fdtaddr $fdtfile;" \
951 "bootm $loadaddr $ramdiskaddr $fdtaddr"
953 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
955 #include <asm/fsl_secure_boot.h>
957 #ifdef CONFIG_SECURE_BOOT
958 #define CONFIG_CMD_BLOB
961 #endif /* __CONFIG_H */