include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  20 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  21 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  22 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  23 #endif
  24
  25 #ifdef CONFIG_SPIFLASH
  26 #ifdef CONFIG_NXP_ESBC
  27 #define CONFIG_RAMBOOT_SPIFLASH
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  29 #else
  30 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  31 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  32 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  34 #endif
  35 #endif
  36
  37 #ifdef CONFIG_MTD_RAW_NAND
  38 #ifdef CONFIG_NXP_ESBC
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  41 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  42 #else
  43 #ifdef CONFIG_TPL_BUILD
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  46 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  47 #elif defined(CONFIG_SPL_BUILD)
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  49 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  50 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  51 #endif
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  56 #define CONFIG_RAMBOOT_NAND
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  58 #endif
  59
  60 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  61 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  62 #endif
  63
  64 /* High Level Configuration Options */
  65
  66 #if defined(CONFIG_PCI)
  67 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  68 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
  69
  70 /*
  71  * PCI Windows
  72  * Memory space is mapped 1-1, but I/O space must start from 0.
  73  */
  74 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  75 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
  76 #ifdef CONFIG_PHYS_64BIT
  77 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
  78 #else
  79 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
  80 #endif
  81 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
  82 #ifdef CONFIG_PHYS_64BIT
  83 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
  84 #else
  85 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
  86 #endif
  87
  88 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  89 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
  90 #ifdef CONFIG_PHYS_64BIT
  91 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
  92 #else
  93 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
  94 #endif
  95 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
  96 #ifdef CONFIG_PHYS_64BIT
  97 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
  98 #else
  99 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 100 #endif
 101
 102 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 103 #endif
 104
 105 #define CONFIG_HWCONFIG
 106 /*
 107  * These can be toggled for performance analysis, otherwise use default.
 108  */
 109 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 110
 111 /* DDR Setup */
 112 #define CONFIG_SYS_DDR_RAW_TIMING
 113 #define SPD_EEPROM_ADDRESS              0x52
 114
 115 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 116
 117 #ifndef __ASSEMBLY__
 118 extern unsigned long get_sdram_size(void);
 119 #endif
 120 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 121 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 122 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 123
 124 /* DDR3 Controller Settings */
 125 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 126 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 127 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 128 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 129 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 130 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 131 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 132 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 133 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 134 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 135 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 136 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 137 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 138 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 139 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 140
 141 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 142 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 143 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 144 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 145 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 146 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 147 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 148 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 149 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 150
 151 /* settings for DDR3 at 667MT/s */
 152 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 153 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 154 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 155 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 156 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 157 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 158 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 159 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 160 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 161
 162 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 163 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 164
 165 /*
 166  * Memory map
 167  *
 168  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 169  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 170  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 171  *
 172  * Localbus non-cacheable
 173  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 174  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 175  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 176  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 177  */
 178
 179 /*
 180  * IFC Definitions
 181  */
 182 /* NOR Flash on IFC */
 183
 184 #define CONFIG_SYS_FLASH_BASE           0xee000000
 185 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 186
 187 #ifdef CONFIG_PHYS_64BIT
 188 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 189 #else
 190 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 191 #endif
 192
 193 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 194                                 CSPR_PORT_SIZE_16 | \
 195                                 CSPR_MSEL_NOR | \
 196                                 CSPR_V)
 197 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 198 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 199 /* NOR Flash Timing Params */
 200 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 201                                 FTIM0_NOR_TEADC(0x5) | \
 202                                 FTIM0_NOR_TEAHC(0x5)
 203 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 204                                 FTIM1_NOR_TRAD_NOR(0x0f)
 205 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 206                                 FTIM2_NOR_TCH(0x4) | \
 207                                 FTIM2_NOR_TWP(0x1c)
 208 #define CONFIG_SYS_NOR_FTIM3    0x0
 209
 210 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 211 #define CONFIG_SYS_FLASH_QUIET_TEST
 212 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 213
 214 #undef CONFIG_SYS_FLASH_CHECKSUM
 215 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 216 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 217
 218 /* CFI for NOR Flash */
 219 #define CONFIG_SYS_FLASH_EMPTY_INFO
 220
 221 /* NAND Flash on IFC */
 222 #define CONFIG_SYS_NAND_BASE            0xff800000
 223 #ifdef CONFIG_PHYS_64BIT
 224 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 225 #else
 226 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 227 #endif
 228
 229 #define CONFIG_MTD_PARTITION
 230
 231 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 232                                 | CSPR_PORT_SIZE_8      \
 233                                 | CSPR_MSEL_NAND        \
 234                                 | CSPR_V)
 235 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 236
 237 #if defined(CONFIG_TARGET_P1010RDB_PA)
 238 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 239                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 240                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 241                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 242                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 243                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 244                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 245
 246 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 247 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 248                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 249                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 250                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 251                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 252                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 253                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 254 #endif
 255
 256 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 257 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 258
 259 #if defined(CONFIG_TARGET_P1010RDB_PA)
 260 /* NAND Flash Timing Params */
 261 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 262                                         FTIM0_NAND_TWP(0x0C)   | \
 263                                         FTIM0_NAND_TWCHT(0x04) | \
 264                                         FTIM0_NAND_TWH(0x05)
 265 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 266                                         FTIM1_NAND_TWBE(0x1d)  | \
 267                                         FTIM1_NAND_TRR(0x07)   | \
 268                                         FTIM1_NAND_TRP(0x0c)
 269 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 270                                         FTIM2_NAND_TREH(0x05) | \
 271                                         FTIM2_NAND_TWHRE(0x0f)
 272 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 273
 274 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 275 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 276 /* ONFI NAND Flash mode0 Timing Params */
 277 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 278                                         FTIM0_NAND_TWP(0x18)   | \
 279                                         FTIM0_NAND_TWCHT(0x07) | \
 280                                         FTIM0_NAND_TWH(0x0a))
 281 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 282                                         FTIM1_NAND_TWBE(0x39)  | \
 283                                         FTIM1_NAND_TRR(0x0e)   | \
 284                                         FTIM1_NAND_TRP(0x18))
 285 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 286                                         FTIM2_NAND_TREH(0x0a)  | \
 287                                         FTIM2_NAND_TWHRE(0x1e))
 288 #define CONFIG_SYS_NAND_FTIM3   0x0
 289 #endif
 290
 291 #define CONFIG_SYS_NAND_DDR_LAW         11
 292
 293 /* Set up IFC registers for boot location NOR/NAND */
 294 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 295 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 296 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 297 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 298 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 299 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 300 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 301 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 302 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 303 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 304 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 305 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 306 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 307 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 308 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 309 #else
 310 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 311 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 312 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 313 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 314 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 315 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 316 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 317 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 318 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 319 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 320 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 321 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 322 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 323 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 324 #endif
 325
 326 /* CPLD on IFC */
 327 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 328
 329 #ifdef CONFIG_PHYS_64BIT
 330 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 331 #else
 332 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 333 #endif
 334
 335 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 336                                 | CSPR_PORT_SIZE_8 \
 337                                 | CSPR_MSEL_GPCM \
 338                                 | CSPR_V)
 339 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 340 #define CONFIG_SYS_CSOR3                0x0
 341 /* CPLD Timing parameters for IFC CS3 */
 342 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 343                                         FTIM0_GPCM_TEADC(0x0e) | \
 344                                         FTIM0_GPCM_TEAHC(0x0e))
 345 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 346                                         FTIM1_GPCM_TRAD(0x1f))
 347 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 348                                         FTIM2_GPCM_TCH(0x8) | \
 349                                         FTIM2_GPCM_TWP(0x1f))
 350 #define CONFIG_SYS_CS3_FTIM3            0x0
 351
 352 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 353         defined(CONFIG_RAMBOOT_NAND)
 354 #define CONFIG_SYS_RAMBOOT
 355 #else
 356 #undef CONFIG_SYS_RAMBOOT
 357 #endif
 358
 359 #define CONFIG_SYS_INIT_RAM_LOCK
 360 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 361 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 362
 363 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 364
 365 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 366
 367 /*
 368  * Config the L2 Cache as L2 SRAM
 369  */
 370 #if defined(CONFIG_SPL_BUILD)
 371 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 372 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 373 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 374 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 375 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 376 #elif defined(CONFIG_MTD_RAW_NAND)
 377 #ifdef CONFIG_TPL_BUILD
 378 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 379 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 380 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 381 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 382 #else
 383 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 384 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 385 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 386 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 387 #endif
 388 #endif
 389 #endif
 390
 391 /* Serial Port */
 392 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 393 #define CONFIG_SYS_NS16550_SERIAL
 394 #define CONFIG_SYS_NS16550_REG_SIZE     1
 395 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 396 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
 397 #define CONFIG_NS16550_MIN_FUNCTIONS
 398 #endif
 399
 400 #define CONFIG_SYS_BAUDRATE_TABLE       \
 401         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 402
 403 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 404 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 405
 406 /* I2C */
 407 #define I2C_PCA9557_ADDR1               0x18
 408 #define I2C_PCA9557_ADDR2               0x19
 409 #define I2C_PCA9557_BUS_NUM             0
 410
 411 /* I2C EEPROM */
 412 #if defined(CONFIG_TARGET_P1010RDB_PB)
 413 #ifdef CONFIG_ID_EEPROM
 414 #define CONFIG_SYS_I2C_EEPROM_NXID
 415 #endif
 416 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 417 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 418 #endif
 419 /* enable read and write access to EEPROM */
 420
 421 /* RTC */
 422 #define CONFIG_RTC_PT7C4338
 423 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 424
 425 /*
 426  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 427  * used for SLIC
 428  */
 429 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 430 /* eSPI - Enhanced SPI */
 431 #endif
 432
 433 #if defined(CONFIG_TSEC_ENET)
 434 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 435 #define CONFIG_TSEC1    1
 436 #define CONFIG_TSEC1_NAME       "eTSEC1"
 437 #define CONFIG_TSEC2    1
 438 #define CONFIG_TSEC2_NAME       "eTSEC2"
 439 #define CONFIG_TSEC3    1
 440 #define CONFIG_TSEC3_NAME       "eTSEC3"
 441
 442 #define TSEC1_PHY_ADDR          1
 443 #define TSEC2_PHY_ADDR          0
 444 #define TSEC3_PHY_ADDR          2
 445
 446 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 447 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 448 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 449
 450 #define TSEC1_PHYIDX            0
 451 #define TSEC2_PHYIDX            0
 452 #define TSEC3_PHYIDX            0
 453
 454 /* TBI PHY configuration for SGMII mode */
 455 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 456                 TBICR_PHY_RESET \
 457                 | TBICR_ANEG_ENABLE \
 458                 | TBICR_FULL_DUPLEX \
 459                 | TBICR_SPEED1_SET \
 460                 )
 461
 462 #endif  /* CONFIG_TSEC_ENET */
 463
 464 #ifdef CONFIG_MMC
 465 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 466 #endif
 467
 468 /*
 469  * Environment
 470  */
 471 #if defined(CONFIG_SDCARD)
 472 #define CONFIG_FSL_FIXED_MMC_LOCATION
 473 #elif defined(CONFIG_MTD_RAW_NAND)
 474 #ifdef CONFIG_TPL_BUILD
 475 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 476 #endif
 477 #endif
 478
 479 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 480 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 481
 482 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 483                  || defined(CONFIG_FSL_SATA)
 484 #endif
 485
 486 /*
 487  * Miscellaneous configurable options
 488  */
 489
 490 /*
 491  * For booting Linux, the board info and command line data
 492  * have to be in the first 64 MB of memory, since this is
 493  * the maximum mapped by the Linux kernel during initialization.
 494  */
 495 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 496 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 497
 498 /*
 499  * Environment Configuration
 500  */
 501
 502 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 503 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 504
 505 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 506         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 507         "netdev=eth0\0"                                         \
 508         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 509         "loadaddr=1000000\0"                    \
 510         "consoledev=ttyS0\0"                            \
 511         "ramdiskaddr=2000000\0"                 \
 512         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 513         "fdtaddr=1e00000\0"                             \
 514         "fdtfile=p1010rdb.dtb\0"                \
 515         "bdev=sda1\0"   \
 516         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 517         "othbootargs=ramdisk_size=600000\0" \
 518         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 519         "console=$consoledev,$baudrate $othbootargs; "  \
 520         "usb start;"                    \
 521         "fatload usb 0:2 $loadaddr $bootfile;"          \
 522         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 523         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 524         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 525         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 526         "console=$consoledev,$baudrate $othbootargs; "  \
 527         "usb start;"                    \
 528         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 529         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 530         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 531         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 532         BOOTMODE
 533
 534 #if defined(CONFIG_TARGET_P1010RDB_PA)
 535 #define BOOTMODE \
 536         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 537         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 538         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 539         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 540         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 541         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 542
 543 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 544 #define BOOTMODE \
 545         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 546         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 547         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 548         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 549         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 550         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 551         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 552         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 553         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 554         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 555 #endif
 556
 557 #include <asm/fsl_secure_boot.h>
 558
 559 #endif  /* __CONFIG_H */