1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
20 #define CONFIG_SPL_PAD_TO 0x18000
21 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
22 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
25 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
27 #ifdef CONFIG_SPL_BUILD
28 #define CONFIG_SPL_COMMON_INIT_DDR
32 #ifdef CONFIG_SPIFLASH
33 #ifdef CONFIG_NXP_ESBC
34 #define CONFIG_RAMBOOT_SPIFLASH
35 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
37 #define CONFIG_SPL_SPI_FLASH_MINIMAL
38 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
39 #define CONFIG_SPL_PAD_TO 0x18000
40 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
45 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
46 #ifdef CONFIG_SPL_BUILD
47 #define CONFIG_SPL_COMMON_INIT_DDR
52 #ifdef CONFIG_MTD_RAW_NAND
53 #ifdef CONFIG_NXP_ESBC
54 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
56 #define CONFIG_SPL_MAX_SIZE 8192
57 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
58 #define CONFIG_SPL_RELOC_STACK 0x00100000
59 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
60 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
61 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
63 #ifdef CONFIG_TPL_BUILD
64 #define CONFIG_SPL_NAND_INIT
65 #define CONFIG_SPL_COMMON_INIT_DDR
66 #define CONFIG_SPL_MAX_SIZE (128 << 10)
67 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
68 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
69 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
70 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
71 #elif defined(CONFIG_SPL_BUILD)
72 #define CONFIG_SPL_MAX_SIZE 8192
73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
74 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
75 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
77 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
78 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
81 #define CONFIG_SPL_PAD_TO 0x20000
82 #define CONFIG_TPL_PAD_TO 0x20000
83 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
87 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
88 #define CONFIG_RAMBOOT_NAND
89 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
92 #ifndef CONFIG_RESET_VECTOR_ADDRESS
93 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
96 /* High Level Configuration Options */
98 #if defined(CONFIG_PCI)
99 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
100 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
104 * Memory space is mapped 1-1, but I/O space must start from 0.
106 /* controller 1, Slot 1, tgtid 1, Base address a000 */
107 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
108 #ifdef CONFIG_PHYS_64BIT
109 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
111 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
113 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
114 #ifdef CONFIG_PHYS_64BIT
115 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
117 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
120 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
121 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
122 #ifdef CONFIG_PHYS_64BIT
123 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
125 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
127 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
128 #ifdef CONFIG_PHYS_64BIT
129 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
131 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
134 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
137 #define CONFIG_HWCONFIG
139 * These can be toggled for performance analysis, otherwise use default.
141 #define CONFIG_L2_CACHE /* toggle L2 cache */
144 #define CONFIG_ENABLE_36BIT_PHYS
147 #define CONFIG_SYS_DDR_RAW_TIMING
148 #define CONFIG_SYS_SPD_BUS_NUM 1
149 #define SPD_EEPROM_ADDRESS 0x52
151 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
154 extern unsigned long get_sdram_size(void);
156 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
157 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
158 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
160 /* DDR3 Controller Settings */
161 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
162 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
163 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
164 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
165 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
166 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
167 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
168 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
169 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
170 #define CONFIG_SYS_DDR_RCW_1 0x00000000
171 #define CONFIG_SYS_DDR_RCW_2 0x00000000
172 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
173 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
174 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
175 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
177 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
178 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
179 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
180 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
181 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
182 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
183 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
184 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
185 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
187 /* settings for DDR3 at 667MT/s */
188 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
189 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
190 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
191 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
192 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
193 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
194 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
195 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
196 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
198 #define CONFIG_SYS_CCSRBAR 0xffe00000
199 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
201 /* Don't relocate CCSRBAR while in NAND_SPL */
202 #ifdef CONFIG_SPL_BUILD
203 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
209 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
210 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
211 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
213 * Localbus non-cacheable
214 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
215 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
216 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
217 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
223 /* NOR Flash on IFC */
225 #define CONFIG_SYS_FLASH_BASE 0xee000000
226 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
228 #ifdef CONFIG_PHYS_64BIT
229 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
231 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
234 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
235 CSPR_PORT_SIZE_16 | \
238 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
239 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
240 /* NOR Flash Timing Params */
241 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
242 FTIM0_NOR_TEADC(0x5) | \
244 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
245 FTIM1_NOR_TRAD_NOR(0x0f)
246 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
247 FTIM2_NOR_TCH(0x4) | \
249 #define CONFIG_SYS_NOR_FTIM3 0x0
251 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
252 #define CONFIG_SYS_FLASH_QUIET_TEST
253 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
255 #undef CONFIG_SYS_FLASH_CHECKSUM
256 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
257 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
259 /* CFI for NOR Flash */
260 #define CONFIG_SYS_FLASH_EMPTY_INFO
262 /* NAND Flash on IFC */
263 #define CONFIG_SYS_NAND_BASE 0xff800000
264 #ifdef CONFIG_PHYS_64BIT
265 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
267 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
270 #define CONFIG_MTD_PARTITION
272 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
276 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
278 #if defined(CONFIG_TARGET_P1010RDB_PA)
279 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
280 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
281 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
282 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
283 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
284 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
285 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
287 #elif defined(CONFIG_TARGET_P1010RDB_PB)
288 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
289 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
290 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
291 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
292 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
293 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
294 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
297 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
298 #define CONFIG_SYS_MAX_NAND_DEVICE 1
300 #if defined(CONFIG_TARGET_P1010RDB_PA)
301 /* NAND Flash Timing Params */
302 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
303 FTIM0_NAND_TWP(0x0C) | \
304 FTIM0_NAND_TWCHT(0x04) | \
306 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
307 FTIM1_NAND_TWBE(0x1d) | \
308 FTIM1_NAND_TRR(0x07) | \
310 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
311 FTIM2_NAND_TREH(0x05) | \
312 FTIM2_NAND_TWHRE(0x0f)
313 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
315 #elif defined(CONFIG_TARGET_P1010RDB_PB)
316 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
317 /* ONFI NAND Flash mode0 Timing Params */
318 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
319 FTIM0_NAND_TWP(0x18) | \
320 FTIM0_NAND_TWCHT(0x07) | \
321 FTIM0_NAND_TWH(0x0a))
322 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
323 FTIM1_NAND_TWBE(0x39) | \
324 FTIM1_NAND_TRR(0x0e) | \
325 FTIM1_NAND_TRP(0x18))
326 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
327 FTIM2_NAND_TREH(0x0a) | \
328 FTIM2_NAND_TWHRE(0x1e))
329 #define CONFIG_SYS_NAND_FTIM3 0x0
332 #define CONFIG_SYS_NAND_DDR_LAW 11
334 /* Set up IFC registers for boot location NOR/NAND */
335 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
336 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
337 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
338 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
339 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
340 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
341 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
342 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
343 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
344 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
345 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
346 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
347 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
348 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
349 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
351 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
352 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
353 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
354 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
355 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
356 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
357 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
358 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
359 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
360 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
361 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
362 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
363 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
364 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
368 #define CONFIG_SYS_CPLD_BASE 0xffb00000
370 #ifdef CONFIG_PHYS_64BIT
371 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
373 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
376 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
380 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
381 #define CONFIG_SYS_CSOR3 0x0
382 /* CPLD Timing parameters for IFC CS3 */
383 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
384 FTIM0_GPCM_TEADC(0x0e) | \
385 FTIM0_GPCM_TEAHC(0x0e))
386 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
387 FTIM1_GPCM_TRAD(0x1f))
388 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
389 FTIM2_GPCM_TCH(0x8) | \
390 FTIM2_GPCM_TWP(0x1f))
391 #define CONFIG_SYS_CS3_FTIM3 0x0
393 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
394 defined(CONFIG_RAMBOOT_NAND)
395 #define CONFIG_SYS_RAMBOOT
397 #undef CONFIG_SYS_RAMBOOT
400 #define CONFIG_SYS_INIT_RAM_LOCK
401 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
402 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
404 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
405 - GENERATED_GBL_DATA_SIZE)
406 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
408 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
411 * Config the L2 Cache as L2 SRAM
413 #if defined(CONFIG_SPL_BUILD)
414 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
415 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
416 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
417 #define CONFIG_SYS_L2_SIZE (256 << 10)
418 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
419 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
420 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
421 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
422 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
423 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
424 #elif defined(CONFIG_MTD_RAW_NAND)
425 #ifdef CONFIG_TPL_BUILD
426 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
427 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
428 #define CONFIG_SYS_L2_SIZE (256 << 10)
429 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
430 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
431 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
432 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
433 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
434 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
436 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
437 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
438 #define CONFIG_SYS_L2_SIZE (256 << 10)
439 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
440 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
441 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
447 #undef CONFIG_SERIAL_SOFTWARE_FIFO
448 #define CONFIG_SYS_NS16550_SERIAL
449 #define CONFIG_SYS_NS16550_REG_SIZE 1
450 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
451 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
452 #define CONFIG_NS16550_MIN_FUNCTIONS
455 #define CONFIG_SYS_BAUDRATE_TABLE \
456 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
458 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
459 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
462 #define I2C_PCA9557_ADDR1 0x18
463 #define I2C_PCA9557_ADDR2 0x19
464 #define I2C_PCA9557_BUS_NUM 0
467 #if defined(CONFIG_TARGET_P1010RDB_PB)
468 #ifdef CONFIG_ID_EEPROM
469 #define CONFIG_SYS_I2C_EEPROM_NXID
471 #define CONFIG_SYS_EEPROM_BUS_NUM 0
472 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
474 /* enable read and write access to EEPROM */
477 #define CONFIG_RTC_PT7C4338
478 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
481 * SPI interface will not be available in case of NAND boot SPI CS0 will be
484 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
485 /* eSPI - Enhanced SPI */
488 #if defined(CONFIG_TSEC_ENET)
489 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
490 #define CONFIG_TSEC1 1
491 #define CONFIG_TSEC1_NAME "eTSEC1"
492 #define CONFIG_TSEC2 1
493 #define CONFIG_TSEC2_NAME "eTSEC2"
494 #define CONFIG_TSEC3 1
495 #define CONFIG_TSEC3_NAME "eTSEC3"
497 #define TSEC1_PHY_ADDR 1
498 #define TSEC2_PHY_ADDR 0
499 #define TSEC3_PHY_ADDR 2
501 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
502 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
503 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
505 #define TSEC1_PHYIDX 0
506 #define TSEC2_PHYIDX 0
507 #define TSEC3_PHYIDX 0
509 /* TBI PHY configuration for SGMII mode */
510 #define CONFIG_TSEC_TBICR_SETTINGS ( \
512 | TBICR_ANEG_ENABLE \
513 | TBICR_FULL_DUPLEX \
517 #endif /* CONFIG_TSEC_ENET */
520 #define CONFIG_FSL_SATA_V2
522 #ifdef CONFIG_FSL_SATA
524 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
525 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
527 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
528 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
531 #endif /* #ifdef CONFIG_FSL_SATA */
534 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
537 #define CONFIG_HAS_FSL_DR_USB
539 #if defined(CONFIG_HAS_FSL_DR_USB)
540 #ifdef CONFIG_USB_EHCI_HCD
541 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
548 #if defined(CONFIG_SDCARD)
549 #define CONFIG_FSL_FIXED_MMC_LOCATION
550 #elif defined(CONFIG_MTD_RAW_NAND)
551 #ifdef CONFIG_TPL_BUILD
552 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
554 #if defined(CONFIG_TARGET_P1010RDB_PA)
555 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
556 #elif defined(CONFIG_TARGET_P1010RDB_PB)
557 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
562 #define CONFIG_LOADS_ECHO /* echo on for serial download */
563 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
565 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
566 || defined(CONFIG_FSL_SATA)
570 * Miscellaneous configurable options
574 * For booting Linux, the board info and command line data
575 * have to be in the first 64 MB of memory, since this is
576 * the maximum mapped by the Linux kernel during initialization.
578 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
579 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
582 * Environment Configuration
585 #define CONFIG_ROOTPATH "/opt/nfsroot"
586 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
588 #define CONFIG_EXTRA_ENV_SETTINGS \
589 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
591 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
592 "loadaddr=1000000\0" \
593 "consoledev=ttyS0\0" \
594 "ramdiskaddr=2000000\0" \
595 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
596 "fdtaddr=1e00000\0" \
597 "fdtfile=p1010rdb.dtb\0" \
599 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
600 "othbootargs=ramdisk_size=600000\0" \
601 "usbfatboot=setenv bootargs root=/dev/ram rw " \
602 "console=$consoledev,$baudrate $othbootargs; " \
604 "fatload usb 0:2 $loadaddr $bootfile;" \
605 "fatload usb 0:2 $fdtaddr $fdtfile;" \
606 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
607 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
608 "usbext2boot=setenv bootargs root=/dev/ram rw " \
609 "console=$consoledev,$baudrate $othbootargs; " \
611 "ext2load usb 0:4 $loadaddr $bootfile;" \
612 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
613 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
614 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
617 #if defined(CONFIG_TARGET_P1010RDB_PA)
619 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
620 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
621 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
622 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
623 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
624 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
626 #elif defined(CONFIG_TARGET_P1010RDB_PB)
628 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
629 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
630 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
631 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
632 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
633 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
634 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
635 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
636 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
637 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
640 #include <asm/fsl_secure_boot.h>
642 #endif /* __CONFIG_H */