include/configs/P1010RDB.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #define CONFIG_P1010
  17 #define CONFIG_E500                     /* BOOKE e500 family */
  18 #include <asm/config_mpc85xx.h>
  19 #define CONFIG_NAND_FSL_IFC
  20
  21 #ifdef CONFIG_SDCARD
  22 #define CONFIG_SPL_SERIAL_SUPPORT
  23 #define CONFIG_SPL_MMC_MINIMAL
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  26 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  27 #define CONFIG_SYS_TEXT_BASE            0x11001000
  28 #define CONFIG_SPL_TEXT_BASE            0xD0001000
  29 #define CONFIG_SPL_PAD_TO               0x18000
  30 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  31 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  32 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  33 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  34 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  35 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  36 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  37 #define CONFIG_SPL_MMC_BOOT
  38 #ifdef CONFIG_SPL_BUILD
  39 #define CONFIG_SPL_COMMON_INIT_DDR
  40 #endif
  41 #endif
  42
  43 #ifdef CONFIG_SPIFLASH
  44 #ifdef CONFIG_SECURE_BOOT
  45 #define CONFIG_RAMBOOT_SPIFLASH
  46 #define CONFIG_SYS_TEXT_BASE            0x11000000
  47 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  48 #else
  49 #define CONFIG_SPL_SERIAL_SUPPORT
  50 #define CONFIG_SPL_SPI_SUPPORT
  51 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  52 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  53 #define CONFIG_SPL_FLUSH_IMAGE
  54 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  55 #define CONFIG_FSL_LAW         /* Use common FSL init code */
  56 #define CONFIG_SYS_TEXT_BASE                    0x11001000
  57 #define CONFIG_SPL_TEXT_BASE                    0xD0001000
  58 #define CONFIG_SPL_PAD_TO                       0x18000
  59 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  65 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  66 #define CONFIG_SPL_SPI_BOOT
  67 #ifdef CONFIG_SPL_BUILD
  68 #define CONFIG_SPL_COMMON_INIT_DDR
  69 #endif
  70 #endif
  71 #endif
  72
  73 #ifdef CONFIG_NAND
  74 #ifdef CONFIG_SECURE_BOOT
  75 #define CONFIG_SPL_INIT_MINIMAL
  76 #define CONFIG_SPL_SERIAL_SUPPORT
  77 #define CONFIG_SPL_NAND_SUPPORT
  78 #define CONFIG_SPL_NAND_BOOT
  79 #define CONFIG_SPL_FLUSH_IMAGE
  80 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  81
  82 #define CONFIG_SYS_TEXT_BASE            0x00201000
  83 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
  84 #define CONFIG_SPL_MAX_SIZE             8192
  85 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  86 #define CONFIG_SPL_RELOC_STACK          0x00100000
  87 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  88 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  89 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  90 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  91 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  92 #else
  93 #ifdef CONFIG_TPL_BUILD
  94 #define CONFIG_SPL_NAND_BOOT
  95 #define CONFIG_SPL_FLUSH_IMAGE
  96 #define CONFIG_SPL_NAND_INIT
  97 #define CONFIG_TPL_SERIAL_SUPPORT
  98 #define CONFIG_TPL_NAND_SUPPORT
  99 #define CONFIG_SPL_COMMON_INIT_DDR
 100 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
 101 #define CONFIG_SPL_TEXT_BASE            0xD0001000
 102 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 103 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
 104 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
 105 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 106 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 107 #elif defined(CONFIG_SPL_BUILD)
 108 #define CONFIG_SPL_INIT_MINIMAL
 109 #define CONFIG_SPL_SERIAL_SUPPORT
 110 #define CONFIG_SPL_NAND_SUPPORT
 111 #define CONFIG_SPL_NAND_MINIMAL
 112 #define CONFIG_SPL_FLUSH_IMAGE
 113 #define CONFIG_SPL_TEXT_BASE            0xff800000
 114 #define CONFIG_SPL_MAX_SIZE             8192
 115 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 116 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
 117 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
 118 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 119 #endif
 120 #define CONFIG_SPL_PAD_TO       0x20000
 121 #define CONFIG_TPL_PAD_TO       0x20000
 122 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
 123 #define CONFIG_SYS_TEXT_BASE    0x11001000
 124 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 125 #endif
 126 #endif
 127
 128 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
 129 #define CONFIG_RAMBOOT_NAND
 130 #define CONFIG_SYS_TEXT_BASE            0x11000000
 131 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
 132 #endif
 133
 134 #ifndef CONFIG_SYS_TEXT_BASE
 135 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 136 #endif
 137
 138 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 139 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 140 #endif
 141
 142 #ifdef CONFIG_SPL_BUILD
 143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 144 #else
 145 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 146 #endif
 147
 148 /* High Level Configuration Options */
 149 #define CONFIG_BOOKE                    /* BOOKE */
 150 #define CONFIG_E500                     /* BOOKE e500 family */
 151 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 152 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 153 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 154
 155 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 156 #if defined(CONFIG_PCI)
 157 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 158 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 159 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 160 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 161 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 162 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 163
 164 #define CONFIG_CMD_PCI
 165
 166 /*
 167  * PCI Windows
 168  * Memory space is mapped 1-1, but I/O space must start from 0.
 169  */
 170 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 171 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
 172 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 173 #ifdef CONFIG_PHYS_64BIT
 174 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 175 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 176 #else
 177 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 178 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 179 #endif
 180 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 181 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 182 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 183 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 184 #ifdef CONFIG_PHYS_64BIT
 185 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 186 #else
 187 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 188 #endif
 189
 190 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 191 #if defined(CONFIG_P1010RDB_PA)
 192 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
 193 #elif defined(CONFIG_P1010RDB_PB)
 194 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
 195 #endif
 196 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 197 #ifdef CONFIG_PHYS_64BIT
 198 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 199 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 200 #else
 201 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 202 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 203 #endif
 204 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 205 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 206 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 207 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 208 #ifdef CONFIG_PHYS_64BIT
 209 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 210 #else
 211 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 212 #endif
 213
 214 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 215
 216 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 217 #define CONFIG_DOS_PARTITION
 218 #endif
 219
 220 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 221 #define CONFIG_TSEC_ENET
 222 #define CONFIG_ENV_OVERWRITE
 223
 224 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 225 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 226
 227 #define CONFIG_MISC_INIT_R
 228 #define CONFIG_HWCONFIG
 229 /*
 230  * These can be toggled for performance analysis, otherwise use default.
 231  */
 232 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 233 #define CONFIG_BTB                      /* toggle branch predition */
 234
 235 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 236
 237 #define CONFIG_ENABLE_36BIT_PHYS
 238
 239 #ifdef CONFIG_PHYS_64BIT
 240 #define CONFIG_ADDR_MAP                 1
 241 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 242 #endif
 243
 244 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 245 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 246 #define CONFIG_PANIC_HANG               /* do not reset board on panic */
 247
 248 /* DDR Setup */
 249 #define CONFIG_SYS_FSL_DDR3
 250 #define CONFIG_SYS_DDR_RAW_TIMING
 251 #define CONFIG_DDR_SPD
 252 #define CONFIG_SYS_SPD_BUS_NUM          1
 253 #define SPD_EEPROM_ADDRESS              0x52
 254
 255 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 256
 257 #ifndef __ASSEMBLY__
 258 extern unsigned long get_sdram_size(void);
 259 #endif
 260 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 261 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 262 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 263
 264 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 265 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 266
 267 /* DDR3 Controller Settings */
 268 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 269 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 270 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 271 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 272 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 273 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 274 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 275 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 276 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 277 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 278 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 279 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 280 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 281 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 282 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 283
 284 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 285 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 286 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 287 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 288 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 289 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 290 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 291 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 292 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 293
 294 /* settings for DDR3 at 667MT/s */
 295 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 296 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 297 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 298 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 299 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 300 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 301 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 302 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 303 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 304
 305 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 306 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 307
 308 /* Don't relocate CCSRBAR while in NAND_SPL */
 309 #ifdef CONFIG_SPL_BUILD
 310 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 311 #endif
 312
 313 /*
 314  * Memory map
 315  *
 316  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 317  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 318  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 319  *
 320  * Localbus non-cacheable
 321  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 322  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 323  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 324  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 325  */
 326
 327 /*
 328  * IFC Definitions
 329  */
 330 /* NOR Flash on IFC */
 331 #ifdef CONFIG_SPL_BUILD
 332 #define CONFIG_SYS_NO_FLASH
 333 #endif
 334
 335 #define CONFIG_SYS_FLASH_BASE           0xee000000
 336 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 337
 338 #ifdef CONFIG_PHYS_64BIT
 339 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 340 #else
 341 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 342 #endif
 343
 344 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 345                                 CSPR_PORT_SIZE_16 | \
 346                                 CSPR_MSEL_NOR | \
 347                                 CSPR_V)
 348 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 349 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 350 /* NOR Flash Timing Params */
 351 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 352                                 FTIM0_NOR_TEADC(0x5) | \
 353                                 FTIM0_NOR_TEAHC(0x5)
 354 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 355                                 FTIM1_NOR_TRAD_NOR(0x0f)
 356 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 357                                 FTIM2_NOR_TCH(0x4) | \
 358                                 FTIM2_NOR_TWP(0x1c)
 359 #define CONFIG_SYS_NOR_FTIM3    0x0
 360
 361 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 362 #define CONFIG_SYS_FLASH_QUIET_TEST
 363 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 364 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 365
 366 #undef CONFIG_SYS_FLASH_CHECKSUM
 367 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 368 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 369
 370 /* CFI for NOR Flash */
 371 #define CONFIG_FLASH_CFI_DRIVER
 372 #define CONFIG_SYS_FLASH_CFI
 373 #define CONFIG_SYS_FLASH_EMPTY_INFO
 374 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 375
 376 /* NAND Flash on IFC */
 377 #define CONFIG_SYS_NAND_BASE            0xff800000
 378 #ifdef CONFIG_PHYS_64BIT
 379 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 380 #else
 381 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 382 #endif
 383
 384 #define CONFIG_MTD_DEVICE
 385 #define CONFIG_MTD_PARTITION
 386 #define CONFIG_CMD_MTDPARTS
 387 #define MTDIDS_DEFAULT                  "nand0=ff800000.flash"
 388 #define MTDPARTS_DEFAULT                \
 389         "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
 390
 391 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 392                                 | CSPR_PORT_SIZE_8      \
 393                                 | CSPR_MSEL_NAND        \
 394                                 | CSPR_V)
 395 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 396
 397 #if defined(CONFIG_P1010RDB_PA)
 398 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 399                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 400                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 401                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 402                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 403                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 404                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 405 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 406
 407 #elif defined(CONFIG_P1010RDB_PB)
 408 #define CONFIG_SYS_NAND_ONFI_DETECTION
 409 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 410                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 411                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 412                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 413                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 414                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 415                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 416 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 417 #endif
 418
 419 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 420 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 421 #define CONFIG_CMD_NAND
 422
 423 #if defined(CONFIG_P1010RDB_PA)
 424 /* NAND Flash Timing Params */
 425 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 426                                         FTIM0_NAND_TWP(0x0C)   | \
 427                                         FTIM0_NAND_TWCHT(0x04) | \
 428                                         FTIM0_NAND_TWH(0x05)
 429 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 430                                         FTIM1_NAND_TWBE(0x1d)  | \
 431                                         FTIM1_NAND_TRR(0x07)   | \
 432                                         FTIM1_NAND_TRP(0x0c)
 433 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 434                                         FTIM2_NAND_TREH(0x05) | \
 435                                         FTIM2_NAND_TWHRE(0x0f)
 436 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 437
 438 #elif defined(CONFIG_P1010RDB_PB)
 439 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 440 /* ONFI NAND Flash mode0 Timing Params */
 441 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 442                                         FTIM0_NAND_TWP(0x18)   | \
 443                                         FTIM0_NAND_TWCHT(0x07) | \
 444                                         FTIM0_NAND_TWH(0x0a))
 445 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 446                                         FTIM1_NAND_TWBE(0x39)  | \
 447                                         FTIM1_NAND_TRR(0x0e)   | \
 448                                         FTIM1_NAND_TRP(0x18))
 449 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 450                                         FTIM2_NAND_TREH(0x0a)  | \
 451                                         FTIM2_NAND_TWHRE(0x1e))
 452 #define CONFIG_SYS_NAND_FTIM3   0x0
 453 #endif
 454
 455 #define CONFIG_SYS_NAND_DDR_LAW         11
 456
 457 /* Set up IFC registers for boot location NOR/NAND */
 458 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 459 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 460 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 461 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 462 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 463 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 464 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 465 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 466 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 467 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 468 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 469 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 470 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 471 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 472 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 473 #else
 474 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 475 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 476 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 477 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 478 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 479 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 480 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 481 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 482 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 483 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 484 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 485 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 486 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 487 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 488 #endif
 489
 490 /* CPLD on IFC */
 491 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 492
 493 #ifdef CONFIG_PHYS_64BIT
 494 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 495 #else
 496 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 497 #endif
 498
 499 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 500                                 | CSPR_PORT_SIZE_8 \
 501                                 | CSPR_MSEL_GPCM \
 502                                 | CSPR_V)
 503 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 504 #define CONFIG_SYS_CSOR3                0x0
 505 /* CPLD Timing parameters for IFC CS3 */
 506 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 507                                         FTIM0_GPCM_TEADC(0x0e) | \
 508                                         FTIM0_GPCM_TEAHC(0x0e))
 509 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 510                                         FTIM1_GPCM_TRAD(0x1f))
 511 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 512                                         FTIM2_GPCM_TCH(0x8) | \
 513                                         FTIM2_GPCM_TWP(0x1f))
 514 #define CONFIG_SYS_CS3_FTIM3            0x0
 515
 516 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 517         defined(CONFIG_RAMBOOT_NAND)
 518 #define CONFIG_SYS_RAMBOOT
 519 #define CONFIG_SYS_EXTRA_ENV_RELOC
 520 #else
 521 #undef CONFIG_SYS_RAMBOOT
 522 #endif
 523
 524 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 525 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 526 #define CONFIG_A003399_NOR_WORKAROUND
 527 #endif
 528 #endif
 529
 530 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 531 #define CONFIG_BOARD_EARLY_INIT_R
 532
 533 #define CONFIG_SYS_INIT_RAM_LOCK
 534 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 535 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 536
 537 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 538                                                 - GENERATED_GBL_DATA_SIZE)
 539 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 540
 541 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 542 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 543
 544 /*
 545  * Config the L2 Cache as L2 SRAM
 546  */
 547 #if defined(CONFIG_SPL_BUILD)
 548 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 549 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 550 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 551 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 552 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 553 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 554 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 555 #define CONFIG_SPL_RELOC_STACK_SIZE     (16 << 10)
 556 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 557 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 558 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 559 #elif defined(CONFIG_NAND)
 560 #ifdef CONFIG_TPL_BUILD
 561 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 562 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 563 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 564 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 565 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 566 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 567 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 568 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 569 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 570 #else
 571 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 572 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 573 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 574 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 575 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 576 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 577 #endif
 578 #endif
 579 #endif
 580
 581 /* Serial Port */
 582 #define CONFIG_CONS_INDEX       1
 583 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 584 #define CONFIG_SYS_NS16550_SERIAL
 585 #define CONFIG_SYS_NS16550_REG_SIZE     1
 586 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 587 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 588 #define CONFIG_NS16550_MIN_FUNCTIONS
 589 #endif
 590
 591 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 592
 593 #define CONFIG_SYS_BAUDRATE_TABLE       \
 594         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 595
 596 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 597 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 598
 599 /* I2C */
 600 #define CONFIG_SYS_I2C
 601 #define CONFIG_SYS_I2C_FSL
 602 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 603 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 604 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 605 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 606 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 607 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 608 #define I2C_PCA9557_ADDR1               0x18
 609 #define I2C_PCA9557_ADDR2               0x19
 610 #define I2C_PCA9557_BUS_NUM             0
 611
 612 /* I2C EEPROM */
 613 #if defined(CONFIG_P1010RDB_PB)
 614 #define CONFIG_ID_EEPROM
 615 #ifdef CONFIG_ID_EEPROM
 616 #define CONFIG_SYS_I2C_EEPROM_NXID
 617 #endif
 618 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 619 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 620 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 621 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 622 #endif
 623 /* enable read and write access to EEPROM */
 624 #define CONFIG_CMD_EEPROM
 625 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 626 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 627 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 628
 629 /* RTC */
 630 #define CONFIG_RTC_PT7C4338
 631 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 632
 633 /*
 634  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 635  * used for SLIC
 636  */
 637 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 638 /* eSPI - Enhanced SPI */
 639 #define CONFIG_SF_DEFAULT_SPEED         10000000
 640 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 641 #endif
 642
 643 #if defined(CONFIG_TSEC_ENET)
 644 #define CONFIG_MII                      /* MII PHY management */
 645 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 646 #define CONFIG_TSEC1    1
 647 #define CONFIG_TSEC1_NAME       "eTSEC1"
 648 #define CONFIG_TSEC2    1
 649 #define CONFIG_TSEC2_NAME       "eTSEC2"
 650 #define CONFIG_TSEC3    1
 651 #define CONFIG_TSEC3_NAME       "eTSEC3"
 652
 653 #define TSEC1_PHY_ADDR          1
 654 #define TSEC2_PHY_ADDR          0
 655 #define TSEC3_PHY_ADDR          2
 656
 657 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 658 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 659 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 660
 661 #define TSEC1_PHYIDX            0
 662 #define TSEC2_PHYIDX            0
 663 #define TSEC3_PHYIDX            0
 664
 665 #define CONFIG_ETHPRIME         "eTSEC1"
 666
 667 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 668
 669 /* TBI PHY configuration for SGMII mode */
 670 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 671                 TBICR_PHY_RESET \
 672                 | TBICR_ANEG_ENABLE \
 673                 | TBICR_FULL_DUPLEX \
 674                 | TBICR_SPEED1_SET \
 675                 )
 676
 677 #endif  /* CONFIG_TSEC_ENET */
 678
 679 /* SATA */
 680 #define CONFIG_FSL_SATA
 681 #define CONFIG_FSL_SATA_V2
 682 #define CONFIG_LIBATA
 683
 684 #ifdef CONFIG_FSL_SATA
 685 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 686 #define CONFIG_SATA1
 687 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 688 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 689 #define CONFIG_SATA2
 690 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 691 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 692
 693 #define CONFIG_CMD_SATA
 694 #define CONFIG_LBA48
 695 #endif /* #ifdef CONFIG_FSL_SATA  */
 696
 697 #define CONFIG_MMC
 698 #ifdef CONFIG_MMC
 699 #define CONFIG_DOS_PARTITION
 700 #define CONFIG_FSL_ESDHC
 701 #define CONFIG_GENERIC_MMC
 702 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 703 #endif
 704
 705 #define CONFIG_HAS_FSL_DR_USB
 706
 707 #if defined(CONFIG_HAS_FSL_DR_USB)
 708 #define CONFIG_USB_EHCI
 709
 710 #ifdef CONFIG_USB_EHCI
 711 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 712 #define CONFIG_USB_EHCI_FSL
 713 #endif
 714 #endif
 715
 716 /*
 717  * Environment
 718  */
 719 #if defined(CONFIG_SDCARD)
 720 #define CONFIG_ENV_IS_IN_MMC
 721 #define CONFIG_FSL_FIXED_MMC_LOCATION
 722 #define CONFIG_SYS_MMC_ENV_DEV          0
 723 #define CONFIG_ENV_SIZE                 0x2000
 724 #elif defined(CONFIG_SPIFLASH)
 725 #define CONFIG_ENV_IS_IN_SPI_FLASH
 726 #define CONFIG_ENV_SPI_BUS      0
 727 #define CONFIG_ENV_SPI_CS       0
 728 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 729 #define CONFIG_ENV_SPI_MODE     0
 730 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 731 #define CONFIG_ENV_SECT_SIZE    0x10000
 732 #define CONFIG_ENV_SIZE         0x2000
 733 #elif defined(CONFIG_NAND)
 734 #define CONFIG_ENV_IS_IN_NAND
 735 #ifdef CONFIG_TPL_BUILD
 736 #define CONFIG_ENV_SIZE         0x2000
 737 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 738 #else
 739 #if defined(CONFIG_P1010RDB_PA)
 740 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 741 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 742 #elif defined(CONFIG_P1010RDB_PB)
 743 #define CONFIG_ENV_SIZE         (16 * 1024)
 744 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 745 #endif
 746 #endif
 747 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 748 #elif defined(CONFIG_SYS_RAMBOOT)
 749 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
 750 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 751 #define CONFIG_ENV_SIZE                 0x2000
 752 #else
 753 #define CONFIG_ENV_IS_IN_FLASH
 754 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 755 #define CONFIG_ENV_SIZE         0x2000
 756 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 757 #endif
 758
 759 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 760 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 761
 762 /*
 763  * Command line configuration.
 764  */
 765 #define CONFIG_CMD_DATE
 766 #define CONFIG_CMD_ERRATA
 767 #define CONFIG_CMD_IRQ
 768 #define CONFIG_CMD_REGINFO
 769
 770 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 771
 772 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 773                  || defined(CONFIG_FSL_SATA)
 774 #define CONFIG_DOS_PARTITION
 775 #endif
 776
 777 /* Hash command with SHA acceleration supported in hardware */
 778 #ifdef CONFIG_FSL_CAAM
 779 #define CONFIG_CMD_HASH
 780 #define CONFIG_SHA_HW_ACCEL
 781 #endif
 782
 783 /*
 784  * Miscellaneous configurable options
 785  */
 786 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 787 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 788 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 789 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 790
 791 #if defined(CONFIG_CMD_KGDB)
 792 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 793 #else
 794 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 795 #endif
 796 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 797                                                 /* Print Buffer Size */
 798 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 799 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 800
 801 /*
 802  * For booting Linux, the board info and command line data
 803  * have to be in the first 64 MB of memory, since this is
 804  * the maximum mapped by the Linux kernel during initialization.
 805  */
 806 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 807 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 808
 809 #if defined(CONFIG_CMD_KGDB)
 810 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 811 #endif
 812
 813 /*
 814  * Environment Configuration
 815  */
 816
 817 #if defined(CONFIG_TSEC_ENET)
 818 #define CONFIG_HAS_ETH0
 819 #define CONFIG_HAS_ETH1
 820 #define CONFIG_HAS_ETH2
 821 #endif
 822
 823 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 824 #define CONFIG_BOOTFILE         "uImage"
 825 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 826
 827 /* default location for tftp and bootm */
 828 #define CONFIG_LOADADDR         1000000
 829
 830 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 831
 832 #define CONFIG_BAUDRATE         115200
 833
 834 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 835         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 836         "netdev=eth0\0"                                         \
 837         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 838         "loadaddr=1000000\0"                    \
 839         "consoledev=ttyS0\0"                            \
 840         "ramdiskaddr=2000000\0"                 \
 841         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 842         "fdtaddr=1e00000\0"                             \
 843         "fdtfile=p1010rdb.dtb\0"                \
 844         "bdev=sda1\0"   \
 845         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 846         "othbootargs=ramdisk_size=600000\0" \
 847         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 848         "console=$consoledev,$baudrate $othbootargs; "  \
 849         "usb start;"                    \
 850         "fatload usb 0:2 $loadaddr $bootfile;"          \
 851         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 852         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 853         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 854         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 855         "console=$consoledev,$baudrate $othbootargs; "  \
 856         "usb start;"                    \
 857         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 858         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 859         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 860         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 861         CONFIG_BOOTMODE
 862
 863 #if defined(CONFIG_P1010RDB_PA)
 864 #define CONFIG_BOOTMODE \
 865         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 866         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 867         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 868         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 869         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 870         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 871
 872 #elif defined(CONFIG_P1010RDB_PB)
 873 #define CONFIG_BOOTMODE \
 874         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 875         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 876         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 877         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 878         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 879         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 880         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 881         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 882         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 883         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 884 #endif
 885
 886 #define CONFIG_RAMBOOTCOMMAND           \
 887         "setenv bootargs root=/dev/ram rw "     \
 888         "console=$consoledev,$baudrate $othbootargs; "  \
 889         "tftp $ramdiskaddr $ramdiskfile;"       \
 890         "tftp $loadaddr $bootfile;"             \
 891         "tftp $fdtaddr $fdtfile;"               \
 892         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 893
 894 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 895
 896 #include <asm/fsl_secure_boot.h>
 897
 898 #endif  /* __CONFIG_H */