Convert CONFIG_USE_BOOTCOMMAND et al to Kconfig
[platform/kernel/u-boot.git] / include / configs / P1010RDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
4  * Copyright 2020 NXP
5  */
6
7 /*
8  * P010 RDB board configuration file
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #include <linux/stringify.h>
15
16 #include <asm/config_mpc85xx.h>
17
18 #ifdef CONFIG_SDCARD
19 #define CONFIG_SPL_FLUSH_IMAGE
20 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
21 #define CONFIG_SPL_PAD_TO               0x18000
22 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
23 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
24 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
25 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
26 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
28 #ifdef CONFIG_SPL_BUILD
29 #define CONFIG_SPL_COMMON_INIT_DDR
30 #endif
31 #endif
32
33 #ifdef CONFIG_SPIFLASH
34 #ifdef CONFIG_NXP_ESBC
35 #define CONFIG_RAMBOOT_SPIFLASH
36 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
37 #else
38 #define CONFIG_SPL_SPI_FLASH_MINIMAL
39 #define CONFIG_SPL_FLUSH_IMAGE
40 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
41 #define CONFIG_SPL_PAD_TO                       0x18000
42 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SPL_COMMON_INIT_DDR
50 #endif
51 #endif
52 #endif
53
54 #ifdef CONFIG_MTD_RAW_NAND
55 #ifdef CONFIG_NXP_ESBC
56 #define CONFIG_SPL_INIT_MINIMAL
57 #define CONFIG_SPL_FLUSH_IMAGE
58 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
59
60 #define CONFIG_SPL_MAX_SIZE             8192
61 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
62 #define CONFIG_SPL_RELOC_STACK          0x00100000
63 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
64 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
65 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
66 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
67 #else
68 #ifdef CONFIG_TPL_BUILD
69 #define CONFIG_SPL_FLUSH_IMAGE
70 #define CONFIG_SPL_NAND_INIT
71 #define CONFIG_SPL_COMMON_INIT_DDR
72 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
73 #define CONFIG_TPL_TEXT_BASE            0xD0001000
74 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
75 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
76 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
77 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
78 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
79 #elif defined(CONFIG_SPL_BUILD)
80 #define CONFIG_SPL_INIT_MINIMAL
81 #define CONFIG_SPL_NAND_MINIMAL
82 #define CONFIG_SPL_FLUSH_IMAGE
83 #define CONFIG_SPL_MAX_SIZE             8192
84 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
85 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
86 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
87 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
88 #endif
89 #define CONFIG_SPL_PAD_TO       0x20000
90 #define CONFIG_TPL_PAD_TO       0x20000
91 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
92 #endif
93 #endif
94
95 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
96 #define CONFIG_RAMBOOT_NAND
97 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
98 #endif
99
100 #ifndef CONFIG_RESET_VECTOR_ADDRESS
101 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
102 #endif
103
104 #ifdef CONFIG_TPL_BUILD
105 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
106 #elif defined(CONFIG_SPL_BUILD)
107 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
108 #else
109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
110 #endif
111
112 /* High Level Configuration Options */
113 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
114
115 #if defined(CONFIG_PCI)
116 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
117 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
118 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
119
120 /*
121  * PCI Windows
122  * Memory space is mapped 1-1, but I/O space must start from 0.
123  */
124 /* controller 1, Slot 1, tgtid 1, Base address a000 */
125 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
126 #ifdef CONFIG_PHYS_64BIT
127 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
128 #else
129 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
130 #endif
131 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
132 #ifdef CONFIG_PHYS_64BIT
133 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
134 #else
135 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
136 #endif
137
138 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
139 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
140 #ifdef CONFIG_PHYS_64BIT
141 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
142 #else
143 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
144 #endif
145 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
146 #ifdef CONFIG_PHYS_64BIT
147 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
148 #else
149 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
150 #endif
151
152 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
153 #endif
154
155 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
156
157 #define CONFIG_HWCONFIG
158 /*
159  * These can be toggled for performance analysis, otherwise use default.
160  */
161 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
162 #define CONFIG_BTB                      /* toggle branch predition */
163
164
165 #define CONFIG_ENABLE_36BIT_PHYS
166
167 /* DDR Setup */
168 #define CONFIG_SYS_DDR_RAW_TIMING
169 #define CONFIG_SYS_SPD_BUS_NUM          1
170 #define SPD_EEPROM_ADDRESS              0x52
171
172 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
173
174 #ifndef __ASSEMBLY__
175 extern unsigned long get_sdram_size(void);
176 #endif
177 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
178 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
179 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
180
181 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
182 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
183
184 /* DDR3 Controller Settings */
185 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
186 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
187 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
188 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
189 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
190 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
191 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
192 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
193 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
194 #define CONFIG_SYS_DDR_RCW_1            0x00000000
195 #define CONFIG_SYS_DDR_RCW_2            0x00000000
196 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
197 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
198 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
199 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
200
201 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
202 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
203 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
204 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
205 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
206 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
207 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
208 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
209 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
210
211 /* settings for DDR3 at 667MT/s */
212 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
213 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
214 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
215 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
216 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
217 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
218 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
219 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
220 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
221
222 #define CONFIG_SYS_CCSRBAR                      0xffe00000
223 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
224
225 /* Don't relocate CCSRBAR while in NAND_SPL */
226 #ifdef CONFIG_SPL_BUILD
227 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
228 #endif
229
230 /*
231  * Memory map
232  *
233  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
234  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
235  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
236  *
237  * Localbus non-cacheable
238  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
239  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
240  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
241  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
242  */
243
244 /*
245  * IFC Definitions
246  */
247 /* NOR Flash on IFC */
248
249 #define CONFIG_SYS_FLASH_BASE           0xee000000
250 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
251
252 #ifdef CONFIG_PHYS_64BIT
253 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
254 #else
255 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
256 #endif
257
258 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
259                                 CSPR_PORT_SIZE_16 | \
260                                 CSPR_MSEL_NOR | \
261                                 CSPR_V)
262 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
263 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
264 /* NOR Flash Timing Params */
265 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
266                                 FTIM0_NOR_TEADC(0x5) | \
267                                 FTIM0_NOR_TEAHC(0x5)
268 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
269                                 FTIM1_NOR_TRAD_NOR(0x0f)
270 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
271                                 FTIM2_NOR_TCH(0x4) | \
272                                 FTIM2_NOR_TWP(0x1c)
273 #define CONFIG_SYS_NOR_FTIM3    0x0
274
275 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
276 #define CONFIG_SYS_FLASH_QUIET_TEST
277 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
278 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
279
280 #undef CONFIG_SYS_FLASH_CHECKSUM
281 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
282 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
283
284 /* CFI for NOR Flash */
285 #define CONFIG_SYS_FLASH_EMPTY_INFO
286
287 /* NAND Flash on IFC */
288 #define CONFIG_SYS_NAND_BASE            0xff800000
289 #ifdef CONFIG_PHYS_64BIT
290 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
291 #else
292 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
293 #endif
294
295 #define CONFIG_MTD_PARTITION
296
297 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
298                                 | CSPR_PORT_SIZE_8      \
299                                 | CSPR_MSEL_NAND        \
300                                 | CSPR_V)
301 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
302
303 #if defined(CONFIG_TARGET_P1010RDB_PA)
304 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
305                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
306                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
307                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
308                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
309                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
310                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
311
312 #elif defined(CONFIG_TARGET_P1010RDB_PB)
313 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
314                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
315                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
316                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
317                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
318                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
319                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
320 #endif
321
322 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
323 #define CONFIG_SYS_MAX_NAND_DEVICE      1
324
325 #if defined(CONFIG_TARGET_P1010RDB_PA)
326 /* NAND Flash Timing Params */
327 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
328                                         FTIM0_NAND_TWP(0x0C)   | \
329                                         FTIM0_NAND_TWCHT(0x04) | \
330                                         FTIM0_NAND_TWH(0x05)
331 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
332                                         FTIM1_NAND_TWBE(0x1d)  | \
333                                         FTIM1_NAND_TRR(0x07)   | \
334                                         FTIM1_NAND_TRP(0x0c)
335 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
336                                         FTIM2_NAND_TREH(0x05) | \
337                                         FTIM2_NAND_TWHRE(0x0f)
338 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
339
340 #elif defined(CONFIG_TARGET_P1010RDB_PB)
341 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
342 /* ONFI NAND Flash mode0 Timing Params */
343 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
344                                         FTIM0_NAND_TWP(0x18)   | \
345                                         FTIM0_NAND_TWCHT(0x07) | \
346                                         FTIM0_NAND_TWH(0x0a))
347 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
348                                         FTIM1_NAND_TWBE(0x39)  | \
349                                         FTIM1_NAND_TRR(0x0e)   | \
350                                         FTIM1_NAND_TRP(0x18))
351 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
352                                         FTIM2_NAND_TREH(0x0a)  | \
353                                         FTIM2_NAND_TWHRE(0x1e))
354 #define CONFIG_SYS_NAND_FTIM3   0x0
355 #endif
356
357 #define CONFIG_SYS_NAND_DDR_LAW         11
358
359 /* Set up IFC registers for boot location NOR/NAND */
360 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
361 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
362 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
363 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
364 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
365 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
366 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
367 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
368 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
369 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
370 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
371 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
372 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
373 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
374 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
375 #else
376 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
377 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
378 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
379 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
380 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
381 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
382 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
383 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
384 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
385 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
386 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
387 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
388 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
389 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
390 #endif
391
392 /* CPLD on IFC */
393 #define CONFIG_SYS_CPLD_BASE            0xffb00000
394
395 #ifdef CONFIG_PHYS_64BIT
396 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
397 #else
398 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
399 #endif
400
401 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
402                                 | CSPR_PORT_SIZE_8 \
403                                 | CSPR_MSEL_GPCM \
404                                 | CSPR_V)
405 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
406 #define CONFIG_SYS_CSOR3                0x0
407 /* CPLD Timing parameters for IFC CS3 */
408 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
409                                         FTIM0_GPCM_TEADC(0x0e) | \
410                                         FTIM0_GPCM_TEAHC(0x0e))
411 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
412                                         FTIM1_GPCM_TRAD(0x1f))
413 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
414                                         FTIM2_GPCM_TCH(0x8) | \
415                                         FTIM2_GPCM_TWP(0x1f))
416 #define CONFIG_SYS_CS3_FTIM3            0x0
417
418 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
419         defined(CONFIG_RAMBOOT_NAND)
420 #define CONFIG_SYS_RAMBOOT
421 #else
422 #undef CONFIG_SYS_RAMBOOT
423 #endif
424
425 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
426 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
427 #define CONFIG_A003399_NOR_WORKAROUND
428 #endif
429 #endif
430
431 #define CONFIG_SYS_INIT_RAM_LOCK
432 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
433 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
434
435 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
436                                                 - GENERATED_GBL_DATA_SIZE)
437 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
438
439 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
440
441 /*
442  * Config the L2 Cache as L2 SRAM
443  */
444 #if defined(CONFIG_SPL_BUILD)
445 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
446 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
447 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
448 #define CONFIG_SYS_L2_SIZE              (256 << 10)
449 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
450 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
451 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
452 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
453 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
454 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
455 #elif defined(CONFIG_MTD_RAW_NAND)
456 #ifdef CONFIG_TPL_BUILD
457 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
458 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
459 #define CONFIG_SYS_L2_SIZE              (256 << 10)
460 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
461 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
462 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
463 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
464 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
465 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
466 #else
467 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
468 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
469 #define CONFIG_SYS_L2_SIZE              (256 << 10)
470 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
471 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
472 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
473 #endif
474 #endif
475 #endif
476
477 /* Serial Port */
478 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
479 #define CONFIG_SYS_NS16550_SERIAL
480 #define CONFIG_SYS_NS16550_REG_SIZE     1
481 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
482 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
483 #define CONFIG_NS16550_MIN_FUNCTIONS
484 #endif
485
486 #define CONFIG_SYS_BAUDRATE_TABLE       \
487         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
488
489 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
490 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
491
492 /* I2C */
493 #define I2C_PCA9557_ADDR1               0x18
494 #define I2C_PCA9557_ADDR2               0x19
495 #define I2C_PCA9557_BUS_NUM             0
496
497 /* I2C EEPROM */
498 #if defined(CONFIG_TARGET_P1010RDB_PB)
499 #ifdef CONFIG_ID_EEPROM
500 #define CONFIG_SYS_I2C_EEPROM_NXID
501 #endif
502 #define CONFIG_SYS_EEPROM_BUS_NUM       0
503 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
504 #endif
505 /* enable read and write access to EEPROM */
506
507 /* RTC */
508 #define CONFIG_RTC_PT7C4338
509 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
510
511 /*
512  * SPI interface will not be available in case of NAND boot SPI CS0 will be
513  * used for SLIC
514  */
515 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
516 /* eSPI - Enhanced SPI */
517 #endif
518
519 #if defined(CONFIG_TSEC_ENET)
520 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
521 #define CONFIG_TSEC1    1
522 #define CONFIG_TSEC1_NAME       "eTSEC1"
523 #define CONFIG_TSEC2    1
524 #define CONFIG_TSEC2_NAME       "eTSEC2"
525 #define CONFIG_TSEC3    1
526 #define CONFIG_TSEC3_NAME       "eTSEC3"
527
528 #define TSEC1_PHY_ADDR          1
529 #define TSEC2_PHY_ADDR          0
530 #define TSEC3_PHY_ADDR          2
531
532 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
533 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
534 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
535
536 #define TSEC1_PHYIDX            0
537 #define TSEC2_PHYIDX            0
538 #define TSEC3_PHYIDX            0
539
540 #define CONFIG_ETHPRIME         "eTSEC1"
541
542 /* TBI PHY configuration for SGMII mode */
543 #define CONFIG_TSEC_TBICR_SETTINGS ( \
544                 TBICR_PHY_RESET \
545                 | TBICR_ANEG_ENABLE \
546                 | TBICR_FULL_DUPLEX \
547                 | TBICR_SPEED1_SET \
548                 )
549
550 #endif  /* CONFIG_TSEC_ENET */
551
552 /* SATA */
553 #define CONFIG_FSL_SATA_V2
554
555 #ifdef CONFIG_FSL_SATA
556 #define CONFIG_SYS_SATA_MAX_DEVICE      2
557 #define CONFIG_SATA1
558 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
559 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
560 #define CONFIG_SATA2
561 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
562 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
563
564 #define CONFIG_LBA48
565 #endif /* #ifdef CONFIG_FSL_SATA  */
566
567 #ifdef CONFIG_MMC
568 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
569 #endif
570
571 #define CONFIG_HAS_FSL_DR_USB
572
573 #if defined(CONFIG_HAS_FSL_DR_USB)
574 #ifdef CONFIG_USB_EHCI_HCD
575 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
576 #define CONFIG_USB_EHCI_FSL
577 #endif
578 #endif
579
580 /*
581  * Environment
582  */
583 #if defined(CONFIG_SDCARD)
584 #define CONFIG_FSL_FIXED_MMC_LOCATION
585 #elif defined(CONFIG_MTD_RAW_NAND)
586 #ifdef CONFIG_TPL_BUILD
587 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
588 #else
589 #if defined(CONFIG_TARGET_P1010RDB_PA)
590 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
591 #elif defined(CONFIG_TARGET_P1010RDB_PB)
592 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
593 #endif
594 #endif
595 #endif
596
597 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
598 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
599
600 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
601
602 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
603                  || defined(CONFIG_FSL_SATA)
604 #endif
605
606 /*
607  * Miscellaneous configurable options
608  */
609
610 /*
611  * For booting Linux, the board info and command line data
612  * have to be in the first 64 MB of memory, since this is
613  * the maximum mapped by the Linux kernel during initialization.
614  */
615 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
616 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
617
618 /*
619  * Environment Configuration
620  */
621
622 #if defined(CONFIG_TSEC_ENET)
623 #define CONFIG_HAS_ETH0
624 #define CONFIG_HAS_ETH1
625 #define CONFIG_HAS_ETH2
626 #endif
627
628 #define CONFIG_ROOTPATH         "/opt/nfsroot"
629 #define CONFIG_BOOTFILE         "uImage"
630 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
631
632 #define CONFIG_EXTRA_ENV_SETTINGS                               \
633         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
634         "netdev=eth0\0"                                         \
635         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
636         "loadaddr=1000000\0"                    \
637         "consoledev=ttyS0\0"                            \
638         "ramdiskaddr=2000000\0"                 \
639         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
640         "fdtaddr=1e00000\0"                             \
641         "fdtfile=p1010rdb.dtb\0"                \
642         "bdev=sda1\0"   \
643         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
644         "othbootargs=ramdisk_size=600000\0" \
645         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
646         "console=$consoledev,$baudrate $othbootargs; "  \
647         "usb start;"                    \
648         "fatload usb 0:2 $loadaddr $bootfile;"          \
649         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
650         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
651         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
652         "usbext2boot=setenv bootargs root=/dev/ram rw " \
653         "console=$consoledev,$baudrate $othbootargs; "  \
654         "usb start;"                    \
655         "ext2load usb 0:4 $loadaddr $bootfile;"         \
656         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
657         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
658         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
659         CONFIG_BOOTMODE
660
661 #if defined(CONFIG_TARGET_P1010RDB_PA)
662 #define CONFIG_BOOTMODE \
663         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
664         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
665         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
666         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
667         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
668         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
669
670 #elif defined(CONFIG_TARGET_P1010RDB_PB)
671 #define CONFIG_BOOTMODE \
672         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
673         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
674         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
675         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
676         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
677         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
678         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
679         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
680         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
681         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
682 #endif
683
684 #include <asm/fsl_secure_boot.h>
685
686 #endif  /* __CONFIG_H */