1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
20 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
21 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
23 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
24 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
27 #ifdef CONFIG_SPIFLASH
28 #ifdef CONFIG_NXP_ESBC
29 #define CONFIG_RAMBOOT_SPIFLASH
30 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
32 #define CONFIG_SPL_SPI_FLASH_MINIMAL
33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
42 #ifdef CONFIG_MTD_RAW_NAND
43 #ifdef CONFIG_NXP_ESBC
44 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
47 #define CONFIG_SPL_RELOC_STACK 0x00100000
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
49 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
50 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
52 #ifdef CONFIG_TPL_BUILD
53 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
54 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
55 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
56 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
57 #elif defined(CONFIG_SPL_BUILD)
58 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
59 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
60 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
62 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
66 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
70 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
71 #define CONFIG_RAMBOOT_NAND
72 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
75 #ifndef CONFIG_RESET_VECTOR_ADDRESS
76 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
79 /* High Level Configuration Options */
81 #if defined(CONFIG_PCI)
82 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
83 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
87 * Memory space is mapped 1-1, but I/O space must start from 0.
89 /* controller 1, Slot 1, tgtid 1, Base address a000 */
90 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
91 #ifdef CONFIG_PHYS_64BIT
92 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
94 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
96 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
97 #ifdef CONFIG_PHYS_64BIT
98 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
100 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
103 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
104 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
105 #ifdef CONFIG_PHYS_64BIT
106 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
108 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
110 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
111 #ifdef CONFIG_PHYS_64BIT
112 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
114 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
117 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
120 #define CONFIG_HWCONFIG
122 * These can be toggled for performance analysis, otherwise use default.
124 #define CONFIG_L2_CACHE /* toggle L2 cache */
127 #define CONFIG_ENABLE_36BIT_PHYS
130 #define CONFIG_SYS_DDR_RAW_TIMING
131 #define CONFIG_SYS_SPD_BUS_NUM 1
132 #define SPD_EEPROM_ADDRESS 0x52
134 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
137 extern unsigned long get_sdram_size(void);
139 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
141 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
143 /* DDR3 Controller Settings */
144 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
145 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
146 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
147 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
148 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
149 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
150 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
151 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
152 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
153 #define CONFIG_SYS_DDR_RCW_1 0x00000000
154 #define CONFIG_SYS_DDR_RCW_2 0x00000000
155 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
156 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
157 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
158 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
160 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
161 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
162 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
163 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
164 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
165 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
166 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
167 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
168 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
170 /* settings for DDR3 at 667MT/s */
171 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
172 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
173 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
174 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
175 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
176 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
177 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
178 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
179 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
181 #define CONFIG_SYS_CCSRBAR 0xffe00000
182 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
187 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
188 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
189 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
191 * Localbus non-cacheable
192 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
193 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
194 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
195 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
201 /* NOR Flash on IFC */
203 #define CONFIG_SYS_FLASH_BASE 0xee000000
204 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
206 #ifdef CONFIG_PHYS_64BIT
207 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
209 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
212 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
213 CSPR_PORT_SIZE_16 | \
216 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
217 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
218 /* NOR Flash Timing Params */
219 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
220 FTIM0_NOR_TEADC(0x5) | \
222 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
223 FTIM1_NOR_TRAD_NOR(0x0f)
224 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
225 FTIM2_NOR_TCH(0x4) | \
227 #define CONFIG_SYS_NOR_FTIM3 0x0
229 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
230 #define CONFIG_SYS_FLASH_QUIET_TEST
231 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
233 #undef CONFIG_SYS_FLASH_CHECKSUM
234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
237 /* CFI for NOR Flash */
238 #define CONFIG_SYS_FLASH_EMPTY_INFO
240 /* NAND Flash on IFC */
241 #define CONFIG_SYS_NAND_BASE 0xff800000
242 #ifdef CONFIG_PHYS_64BIT
243 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
245 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
248 #define CONFIG_MTD_PARTITION
250 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
254 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
256 #if defined(CONFIG_TARGET_P1010RDB_PA)
257 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
258 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
259 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
260 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
261 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
262 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
263 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
265 #elif defined(CONFIG_TARGET_P1010RDB_PB)
266 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
267 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
268 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
269 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
270 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
271 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
272 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
275 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
276 #define CONFIG_SYS_MAX_NAND_DEVICE 1
278 #if defined(CONFIG_TARGET_P1010RDB_PA)
279 /* NAND Flash Timing Params */
280 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
281 FTIM0_NAND_TWP(0x0C) | \
282 FTIM0_NAND_TWCHT(0x04) | \
284 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
285 FTIM1_NAND_TWBE(0x1d) | \
286 FTIM1_NAND_TRR(0x07) | \
288 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
289 FTIM2_NAND_TREH(0x05) | \
290 FTIM2_NAND_TWHRE(0x0f)
291 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
293 #elif defined(CONFIG_TARGET_P1010RDB_PB)
294 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
295 /* ONFI NAND Flash mode0 Timing Params */
296 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
297 FTIM0_NAND_TWP(0x18) | \
298 FTIM0_NAND_TWCHT(0x07) | \
299 FTIM0_NAND_TWH(0x0a))
300 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
301 FTIM1_NAND_TWBE(0x39) | \
302 FTIM1_NAND_TRR(0x0e) | \
303 FTIM1_NAND_TRP(0x18))
304 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
305 FTIM2_NAND_TREH(0x0a) | \
306 FTIM2_NAND_TWHRE(0x1e))
307 #define CONFIG_SYS_NAND_FTIM3 0x0
310 #define CONFIG_SYS_NAND_DDR_LAW 11
312 /* Set up IFC registers for boot location NOR/NAND */
313 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
314 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
315 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
316 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
317 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
318 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
319 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
320 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
321 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
322 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
323 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
324 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
325 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
326 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
327 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
329 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
330 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
331 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
332 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
333 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
334 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
335 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
336 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
337 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
338 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
339 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
340 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
341 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
342 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
346 #define CONFIG_SYS_CPLD_BASE 0xffb00000
348 #ifdef CONFIG_PHYS_64BIT
349 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
351 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
354 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
358 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
359 #define CONFIG_SYS_CSOR3 0x0
360 /* CPLD Timing parameters for IFC CS3 */
361 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
362 FTIM0_GPCM_TEADC(0x0e) | \
363 FTIM0_GPCM_TEAHC(0x0e))
364 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
365 FTIM1_GPCM_TRAD(0x1f))
366 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
367 FTIM2_GPCM_TCH(0x8) | \
368 FTIM2_GPCM_TWP(0x1f))
369 #define CONFIG_SYS_CS3_FTIM3 0x0
371 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
372 defined(CONFIG_RAMBOOT_NAND)
373 #define CONFIG_SYS_RAMBOOT
375 #undef CONFIG_SYS_RAMBOOT
378 #define CONFIG_SYS_INIT_RAM_LOCK
379 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
380 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
382 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
384 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
387 * Config the L2 Cache as L2 SRAM
389 #if defined(CONFIG_SPL_BUILD)
390 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
391 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
392 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
393 #define CONFIG_SYS_L2_SIZE (256 << 10)
394 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
395 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
396 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
397 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
398 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
399 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
400 #elif defined(CONFIG_MTD_RAW_NAND)
401 #ifdef CONFIG_TPL_BUILD
402 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
403 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
404 #define CONFIG_SYS_L2_SIZE (256 << 10)
405 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
406 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
407 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
408 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
409 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
410 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
412 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
413 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
414 #define CONFIG_SYS_L2_SIZE (256 << 10)
415 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
416 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
417 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
423 #undef CONFIG_SERIAL_SOFTWARE_FIFO
424 #define CONFIG_SYS_NS16550_SERIAL
425 #define CONFIG_SYS_NS16550_REG_SIZE 1
426 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
427 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
428 #define CONFIG_NS16550_MIN_FUNCTIONS
431 #define CONFIG_SYS_BAUDRATE_TABLE \
432 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
434 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
435 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
438 #define I2C_PCA9557_ADDR1 0x18
439 #define I2C_PCA9557_ADDR2 0x19
440 #define I2C_PCA9557_BUS_NUM 0
443 #if defined(CONFIG_TARGET_P1010RDB_PB)
444 #ifdef CONFIG_ID_EEPROM
445 #define CONFIG_SYS_I2C_EEPROM_NXID
447 #define CONFIG_SYS_EEPROM_BUS_NUM 0
448 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
450 /* enable read and write access to EEPROM */
453 #define CONFIG_RTC_PT7C4338
454 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
457 * SPI interface will not be available in case of NAND boot SPI CS0 will be
460 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
461 /* eSPI - Enhanced SPI */
464 #if defined(CONFIG_TSEC_ENET)
465 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
466 #define CONFIG_TSEC1 1
467 #define CONFIG_TSEC1_NAME "eTSEC1"
468 #define CONFIG_TSEC2 1
469 #define CONFIG_TSEC2_NAME "eTSEC2"
470 #define CONFIG_TSEC3 1
471 #define CONFIG_TSEC3_NAME "eTSEC3"
473 #define TSEC1_PHY_ADDR 1
474 #define TSEC2_PHY_ADDR 0
475 #define TSEC3_PHY_ADDR 2
477 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
478 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
479 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
481 #define TSEC1_PHYIDX 0
482 #define TSEC2_PHYIDX 0
483 #define TSEC3_PHYIDX 0
485 /* TBI PHY configuration for SGMII mode */
486 #define CONFIG_TSEC_TBICR_SETTINGS ( \
488 | TBICR_ANEG_ENABLE \
489 | TBICR_FULL_DUPLEX \
493 #endif /* CONFIG_TSEC_ENET */
496 #define CONFIG_FSL_SATA_V2
498 #ifdef CONFIG_FSL_SATA
500 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
501 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
503 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
504 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
507 #endif /* #ifdef CONFIG_FSL_SATA */
510 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
513 #define CONFIG_HAS_FSL_DR_USB
515 #if defined(CONFIG_HAS_FSL_DR_USB)
516 #ifdef CONFIG_USB_EHCI_HCD
517 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
524 #if defined(CONFIG_SDCARD)
525 #define CONFIG_FSL_FIXED_MMC_LOCATION
526 #elif defined(CONFIG_MTD_RAW_NAND)
527 #ifdef CONFIG_TPL_BUILD
528 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
530 #if defined(CONFIG_TARGET_P1010RDB_PA)
531 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
532 #elif defined(CONFIG_TARGET_P1010RDB_PB)
533 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
538 #define CONFIG_LOADS_ECHO /* echo on for serial download */
539 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
541 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
542 || defined(CONFIG_FSL_SATA)
546 * Miscellaneous configurable options
550 * For booting Linux, the board info and command line data
551 * have to be in the first 64 MB of memory, since this is
552 * the maximum mapped by the Linux kernel during initialization.
554 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
555 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
558 * Environment Configuration
561 #define CONFIG_ROOTPATH "/opt/nfsroot"
562 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
564 #define CONFIG_EXTRA_ENV_SETTINGS \
565 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
567 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
568 "loadaddr=1000000\0" \
569 "consoledev=ttyS0\0" \
570 "ramdiskaddr=2000000\0" \
571 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
572 "fdtaddr=1e00000\0" \
573 "fdtfile=p1010rdb.dtb\0" \
575 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
576 "othbootargs=ramdisk_size=600000\0" \
577 "usbfatboot=setenv bootargs root=/dev/ram rw " \
578 "console=$consoledev,$baudrate $othbootargs; " \
580 "fatload usb 0:2 $loadaddr $bootfile;" \
581 "fatload usb 0:2 $fdtaddr $fdtfile;" \
582 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
583 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
584 "usbext2boot=setenv bootargs root=/dev/ram rw " \
585 "console=$consoledev,$baudrate $othbootargs; " \
587 "ext2load usb 0:4 $loadaddr $bootfile;" \
588 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
589 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
590 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
593 #if defined(CONFIG_TARGET_P1010RDB_PA)
595 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
596 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
597 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
598 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
599 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
600 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
602 #elif defined(CONFIG_TARGET_P1010RDB_PB)
604 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
605 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
606 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
607 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
608 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
609 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
610 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
611 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
612 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
613 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
616 #include <asm/fsl_secure_boot.h>
618 #endif /* __CONFIG_H */