1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
20 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
21 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
23 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
24 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
25 #ifdef CONFIG_SPL_BUILD
26 #define CONFIG_SPL_COMMON_INIT_DDR
30 #ifdef CONFIG_SPIFLASH
31 #ifdef CONFIG_NXP_ESBC
32 #define CONFIG_RAMBOOT_SPIFLASH
33 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
35 #define CONFIG_SPL_SPI_FLASH_MINIMAL
36 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SPL_COMMON_INIT_DDR
48 #ifdef CONFIG_MTD_RAW_NAND
49 #ifdef CONFIG_NXP_ESBC
50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
52 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
53 #define CONFIG_SPL_RELOC_STACK 0x00100000
54 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
55 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
56 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
58 #ifdef CONFIG_TPL_BUILD
59 #define CONFIG_SPL_NAND_INIT
60 #define CONFIG_SPL_COMMON_INIT_DDR
61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
62 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
63 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
64 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
65 #elif defined(CONFIG_SPL_BUILD)
66 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
67 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
68 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
70 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
74 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
78 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
79 #define CONFIG_RAMBOOT_NAND
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
83 #ifndef CONFIG_RESET_VECTOR_ADDRESS
84 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
87 /* High Level Configuration Options */
89 #if defined(CONFIG_PCI)
90 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
91 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
95 * Memory space is mapped 1-1, but I/O space must start from 0.
97 /* controller 1, Slot 1, tgtid 1, Base address a000 */
98 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
99 #ifdef CONFIG_PHYS_64BIT
100 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
102 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
104 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
105 #ifdef CONFIG_PHYS_64BIT
106 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
108 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
111 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
112 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
113 #ifdef CONFIG_PHYS_64BIT
114 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
116 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
118 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
119 #ifdef CONFIG_PHYS_64BIT
120 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
122 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
125 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
128 #define CONFIG_HWCONFIG
130 * These can be toggled for performance analysis, otherwise use default.
132 #define CONFIG_L2_CACHE /* toggle L2 cache */
135 #define CONFIG_ENABLE_36BIT_PHYS
138 #define CONFIG_SYS_DDR_RAW_TIMING
139 #define CONFIG_SYS_SPD_BUS_NUM 1
140 #define SPD_EEPROM_ADDRESS 0x52
142 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
145 extern unsigned long get_sdram_size(void);
147 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
148 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
149 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
151 /* DDR3 Controller Settings */
152 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
153 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
154 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
155 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
156 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
157 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
158 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
159 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
160 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
161 #define CONFIG_SYS_DDR_RCW_1 0x00000000
162 #define CONFIG_SYS_DDR_RCW_2 0x00000000
163 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
164 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
165 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
166 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
168 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
169 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
170 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
171 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
172 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
173 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
174 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
175 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
176 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
178 /* settings for DDR3 at 667MT/s */
179 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
180 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
181 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
182 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
183 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
184 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
185 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
186 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
187 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
189 #define CONFIG_SYS_CCSRBAR 0xffe00000
190 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
195 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
196 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
197 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
199 * Localbus non-cacheable
200 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
201 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
202 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
203 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
209 /* NOR Flash on IFC */
211 #define CONFIG_SYS_FLASH_BASE 0xee000000
212 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
214 #ifdef CONFIG_PHYS_64BIT
215 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
217 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
220 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
221 CSPR_PORT_SIZE_16 | \
224 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
225 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
226 /* NOR Flash Timing Params */
227 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
228 FTIM0_NOR_TEADC(0x5) | \
230 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
231 FTIM1_NOR_TRAD_NOR(0x0f)
232 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
233 FTIM2_NOR_TCH(0x4) | \
235 #define CONFIG_SYS_NOR_FTIM3 0x0
237 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
238 #define CONFIG_SYS_FLASH_QUIET_TEST
239 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
241 #undef CONFIG_SYS_FLASH_CHECKSUM
242 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
243 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
245 /* CFI for NOR Flash */
246 #define CONFIG_SYS_FLASH_EMPTY_INFO
248 /* NAND Flash on IFC */
249 #define CONFIG_SYS_NAND_BASE 0xff800000
250 #ifdef CONFIG_PHYS_64BIT
251 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
253 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
256 #define CONFIG_MTD_PARTITION
258 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
262 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
264 #if defined(CONFIG_TARGET_P1010RDB_PA)
265 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
266 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
267 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
268 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
269 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
270 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
271 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
273 #elif defined(CONFIG_TARGET_P1010RDB_PB)
274 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
275 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
276 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
277 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
278 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
279 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
280 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
283 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
284 #define CONFIG_SYS_MAX_NAND_DEVICE 1
286 #if defined(CONFIG_TARGET_P1010RDB_PA)
287 /* NAND Flash Timing Params */
288 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
289 FTIM0_NAND_TWP(0x0C) | \
290 FTIM0_NAND_TWCHT(0x04) | \
292 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
293 FTIM1_NAND_TWBE(0x1d) | \
294 FTIM1_NAND_TRR(0x07) | \
296 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
297 FTIM2_NAND_TREH(0x05) | \
298 FTIM2_NAND_TWHRE(0x0f)
299 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
301 #elif defined(CONFIG_TARGET_P1010RDB_PB)
302 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
303 /* ONFI NAND Flash mode0 Timing Params */
304 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
305 FTIM0_NAND_TWP(0x18) | \
306 FTIM0_NAND_TWCHT(0x07) | \
307 FTIM0_NAND_TWH(0x0a))
308 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
309 FTIM1_NAND_TWBE(0x39) | \
310 FTIM1_NAND_TRR(0x0e) | \
311 FTIM1_NAND_TRP(0x18))
312 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
313 FTIM2_NAND_TREH(0x0a) | \
314 FTIM2_NAND_TWHRE(0x1e))
315 #define CONFIG_SYS_NAND_FTIM3 0x0
318 #define CONFIG_SYS_NAND_DDR_LAW 11
320 /* Set up IFC registers for boot location NOR/NAND */
321 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
322 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
323 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
324 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
325 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
326 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
327 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
328 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
329 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
330 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
331 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
332 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
333 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
334 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
335 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
337 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
338 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
339 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
340 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
341 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
342 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
343 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
344 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
345 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
346 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
347 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
348 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
349 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
350 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
354 #define CONFIG_SYS_CPLD_BASE 0xffb00000
356 #ifdef CONFIG_PHYS_64BIT
357 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
359 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
362 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
366 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
367 #define CONFIG_SYS_CSOR3 0x0
368 /* CPLD Timing parameters for IFC CS3 */
369 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
370 FTIM0_GPCM_TEADC(0x0e) | \
371 FTIM0_GPCM_TEAHC(0x0e))
372 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
373 FTIM1_GPCM_TRAD(0x1f))
374 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
375 FTIM2_GPCM_TCH(0x8) | \
376 FTIM2_GPCM_TWP(0x1f))
377 #define CONFIG_SYS_CS3_FTIM3 0x0
379 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
380 defined(CONFIG_RAMBOOT_NAND)
381 #define CONFIG_SYS_RAMBOOT
383 #undef CONFIG_SYS_RAMBOOT
386 #define CONFIG_SYS_INIT_RAM_LOCK
387 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
388 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
390 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
391 - GENERATED_GBL_DATA_SIZE)
392 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
394 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
397 * Config the L2 Cache as L2 SRAM
399 #if defined(CONFIG_SPL_BUILD)
400 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
401 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
402 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
403 #define CONFIG_SYS_L2_SIZE (256 << 10)
404 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
405 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
406 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
407 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
408 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
409 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
410 #elif defined(CONFIG_MTD_RAW_NAND)
411 #ifdef CONFIG_TPL_BUILD
412 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
413 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
414 #define CONFIG_SYS_L2_SIZE (256 << 10)
415 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
416 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
417 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
418 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
419 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
420 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
422 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
423 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
424 #define CONFIG_SYS_L2_SIZE (256 << 10)
425 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
426 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
427 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
433 #undef CONFIG_SERIAL_SOFTWARE_FIFO
434 #define CONFIG_SYS_NS16550_SERIAL
435 #define CONFIG_SYS_NS16550_REG_SIZE 1
436 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
437 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
438 #define CONFIG_NS16550_MIN_FUNCTIONS
441 #define CONFIG_SYS_BAUDRATE_TABLE \
442 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
444 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
445 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
448 #define I2C_PCA9557_ADDR1 0x18
449 #define I2C_PCA9557_ADDR2 0x19
450 #define I2C_PCA9557_BUS_NUM 0
453 #if defined(CONFIG_TARGET_P1010RDB_PB)
454 #ifdef CONFIG_ID_EEPROM
455 #define CONFIG_SYS_I2C_EEPROM_NXID
457 #define CONFIG_SYS_EEPROM_BUS_NUM 0
458 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
460 /* enable read and write access to EEPROM */
463 #define CONFIG_RTC_PT7C4338
464 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
467 * SPI interface will not be available in case of NAND boot SPI CS0 will be
470 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
471 /* eSPI - Enhanced SPI */
474 #if defined(CONFIG_TSEC_ENET)
475 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
476 #define CONFIG_TSEC1 1
477 #define CONFIG_TSEC1_NAME "eTSEC1"
478 #define CONFIG_TSEC2 1
479 #define CONFIG_TSEC2_NAME "eTSEC2"
480 #define CONFIG_TSEC3 1
481 #define CONFIG_TSEC3_NAME "eTSEC3"
483 #define TSEC1_PHY_ADDR 1
484 #define TSEC2_PHY_ADDR 0
485 #define TSEC3_PHY_ADDR 2
487 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
488 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
489 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
491 #define TSEC1_PHYIDX 0
492 #define TSEC2_PHYIDX 0
493 #define TSEC3_PHYIDX 0
495 /* TBI PHY configuration for SGMII mode */
496 #define CONFIG_TSEC_TBICR_SETTINGS ( \
498 | TBICR_ANEG_ENABLE \
499 | TBICR_FULL_DUPLEX \
503 #endif /* CONFIG_TSEC_ENET */
506 #define CONFIG_FSL_SATA_V2
508 #ifdef CONFIG_FSL_SATA
510 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
511 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
513 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
514 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
517 #endif /* #ifdef CONFIG_FSL_SATA */
520 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
523 #define CONFIG_HAS_FSL_DR_USB
525 #if defined(CONFIG_HAS_FSL_DR_USB)
526 #ifdef CONFIG_USB_EHCI_HCD
527 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
534 #if defined(CONFIG_SDCARD)
535 #define CONFIG_FSL_FIXED_MMC_LOCATION
536 #elif defined(CONFIG_MTD_RAW_NAND)
537 #ifdef CONFIG_TPL_BUILD
538 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
540 #if defined(CONFIG_TARGET_P1010RDB_PA)
541 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
542 #elif defined(CONFIG_TARGET_P1010RDB_PB)
543 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
548 #define CONFIG_LOADS_ECHO /* echo on for serial download */
549 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
551 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
552 || defined(CONFIG_FSL_SATA)
556 * Miscellaneous configurable options
560 * For booting Linux, the board info and command line data
561 * have to be in the first 64 MB of memory, since this is
562 * the maximum mapped by the Linux kernel during initialization.
564 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
565 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
568 * Environment Configuration
571 #define CONFIG_ROOTPATH "/opt/nfsroot"
572 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
574 #define CONFIG_EXTRA_ENV_SETTINGS \
575 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
577 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
578 "loadaddr=1000000\0" \
579 "consoledev=ttyS0\0" \
580 "ramdiskaddr=2000000\0" \
581 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
582 "fdtaddr=1e00000\0" \
583 "fdtfile=p1010rdb.dtb\0" \
585 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
586 "othbootargs=ramdisk_size=600000\0" \
587 "usbfatboot=setenv bootargs root=/dev/ram rw " \
588 "console=$consoledev,$baudrate $othbootargs; " \
590 "fatload usb 0:2 $loadaddr $bootfile;" \
591 "fatload usb 0:2 $fdtaddr $fdtfile;" \
592 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
593 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
594 "usbext2boot=setenv bootargs root=/dev/ram rw " \
595 "console=$consoledev,$baudrate $othbootargs; " \
597 "ext2load usb 0:4 $loadaddr $bootfile;" \
598 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
599 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
600 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
603 #if defined(CONFIG_TARGET_P1010RDB_PA)
605 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
606 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
607 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
608 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
609 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
610 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
612 #elif defined(CONFIG_TARGET_P1010RDB_PB)
614 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
615 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
616 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
617 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
618 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
619 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
620 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
621 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
622 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
623 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
626 #include <asm/fsl_secure_boot.h>
628 #endif /* __CONFIG_H */