include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  20 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  21 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  22 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  23 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  24 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  25 #endif
  26
  27 #ifdef CONFIG_SPIFLASH
  28 #ifdef CONFIG_NXP_ESBC
  29 #define CONFIG_RAMBOOT_SPIFLASH
  30 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  31 #else
  32 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  33 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  39 #endif
  40 #endif
  41
  42 #ifdef CONFIG_MTD_RAW_NAND
  43 #ifdef CONFIG_NXP_ESBC
  44 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  45
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  47 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  48 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  49 #else
  50 #ifdef CONFIG_TPL_BUILD
  51 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  52 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  53 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  54 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  55 #elif defined(CONFIG_SPL_BUILD)
  56 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  57 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  58 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  59 #else
  60 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  62 #endif
  63 #endif
  64 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  65 #endif
  66 #endif
  67
  68 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  69 #define CONFIG_RAMBOOT_NAND
  70 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  71 #endif
  72
  73 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  74 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  75 #endif
  76
  77 /* High Level Configuration Options */
  78
  79 #if defined(CONFIG_PCI)
  80 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  81 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
  82
  83 /*
  84  * PCI Windows
  85  * Memory space is mapped 1-1, but I/O space must start from 0.
  86  */
  87 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  88 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
  89 #ifdef CONFIG_PHYS_64BIT
  90 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
  91 #else
  92 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
  93 #endif
  94 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
  95 #ifdef CONFIG_PHYS_64BIT
  96 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
  97 #else
  98 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
  99 #endif
 100
 101 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 102 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 103 #ifdef CONFIG_PHYS_64BIT
 104 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 105 #else
 106 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 107 #endif
 108 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 109 #ifdef CONFIG_PHYS_64BIT
 110 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 111 #else
 112 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 113 #endif
 114
 115 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 116 #endif
 117
 118 #define CONFIG_HWCONFIG
 119 /*
 120  * These can be toggled for performance analysis, otherwise use default.
 121  */
 122 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 123
 124
 125 #define CONFIG_ENABLE_36BIT_PHYS
 126
 127 /* DDR Setup */
 128 #define CONFIG_SYS_DDR_RAW_TIMING
 129 #define CONFIG_SYS_SPD_BUS_NUM          1
 130 #define SPD_EEPROM_ADDRESS              0x52
 131
 132 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 133
 134 #ifndef __ASSEMBLY__
 135 extern unsigned long get_sdram_size(void);
 136 #endif
 137 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 138 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 139 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 140
 141 /* DDR3 Controller Settings */
 142 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 143 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 144 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 145 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 146 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 147 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 148 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 149 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 150 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 151 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 152 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 153 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 154 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 155 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 156 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 157
 158 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 159 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 160 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 161 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 162 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 163 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 164 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 165 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 166 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 167
 168 /* settings for DDR3 at 667MT/s */
 169 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 170 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 171 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 172 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 173 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 174 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 175 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 176 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 177 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 178
 179 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 180 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 181
 182 /*
 183  * Memory map
 184  *
 185  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 186  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 187  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 188  *
 189  * Localbus non-cacheable
 190  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 191  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 192  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 193  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 194  */
 195
 196 /*
 197  * IFC Definitions
 198  */
 199 /* NOR Flash on IFC */
 200
 201 #define CONFIG_SYS_FLASH_BASE           0xee000000
 202 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 203
 204 #ifdef CONFIG_PHYS_64BIT
 205 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 206 #else
 207 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 208 #endif
 209
 210 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 211                                 CSPR_PORT_SIZE_16 | \
 212                                 CSPR_MSEL_NOR | \
 213                                 CSPR_V)
 214 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 215 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 216 /* NOR Flash Timing Params */
 217 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 218                                 FTIM0_NOR_TEADC(0x5) | \
 219                                 FTIM0_NOR_TEAHC(0x5)
 220 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 221                                 FTIM1_NOR_TRAD_NOR(0x0f)
 222 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 223                                 FTIM2_NOR_TCH(0x4) | \
 224                                 FTIM2_NOR_TWP(0x1c)
 225 #define CONFIG_SYS_NOR_FTIM3    0x0
 226
 227 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 228 #define CONFIG_SYS_FLASH_QUIET_TEST
 229 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 230
 231 #undef CONFIG_SYS_FLASH_CHECKSUM
 232 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 233 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 234
 235 /* CFI for NOR Flash */
 236 #define CONFIG_SYS_FLASH_EMPTY_INFO
 237
 238 /* NAND Flash on IFC */
 239 #define CONFIG_SYS_NAND_BASE            0xff800000
 240 #ifdef CONFIG_PHYS_64BIT
 241 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 242 #else
 243 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 244 #endif
 245
 246 #define CONFIG_MTD_PARTITION
 247
 248 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 249                                 | CSPR_PORT_SIZE_8      \
 250                                 | CSPR_MSEL_NAND        \
 251                                 | CSPR_V)
 252 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 253
 254 #if defined(CONFIG_TARGET_P1010RDB_PA)
 255 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 256                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 257                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 258                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 259                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 260                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 261                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 262
 263 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 264 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 265                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 266                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 267                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 268                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 269                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 270                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 271 #endif
 272
 273 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 274 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 275
 276 #if defined(CONFIG_TARGET_P1010RDB_PA)
 277 /* NAND Flash Timing Params */
 278 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 279                                         FTIM0_NAND_TWP(0x0C)   | \
 280                                         FTIM0_NAND_TWCHT(0x04) | \
 281                                         FTIM0_NAND_TWH(0x05)
 282 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 283                                         FTIM1_NAND_TWBE(0x1d)  | \
 284                                         FTIM1_NAND_TRR(0x07)   | \
 285                                         FTIM1_NAND_TRP(0x0c)
 286 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 287                                         FTIM2_NAND_TREH(0x05) | \
 288                                         FTIM2_NAND_TWHRE(0x0f)
 289 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 290
 291 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 292 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 293 /* ONFI NAND Flash mode0 Timing Params */
 294 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 295                                         FTIM0_NAND_TWP(0x18)   | \
 296                                         FTIM0_NAND_TWCHT(0x07) | \
 297                                         FTIM0_NAND_TWH(0x0a))
 298 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 299                                         FTIM1_NAND_TWBE(0x39)  | \
 300                                         FTIM1_NAND_TRR(0x0e)   | \
 301                                         FTIM1_NAND_TRP(0x18))
 302 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 303                                         FTIM2_NAND_TREH(0x0a)  | \
 304                                         FTIM2_NAND_TWHRE(0x1e))
 305 #define CONFIG_SYS_NAND_FTIM3   0x0
 306 #endif
 307
 308 #define CONFIG_SYS_NAND_DDR_LAW         11
 309
 310 /* Set up IFC registers for boot location NOR/NAND */
 311 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 312 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 313 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 314 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 315 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 316 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 317 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 318 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 319 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 320 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 321 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 322 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 323 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 324 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 325 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 326 #else
 327 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 328 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 329 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 330 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 331 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 332 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 333 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 334 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 335 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 336 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 337 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 338 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 339 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 340 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 341 #endif
 342
 343 /* CPLD on IFC */
 344 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 345
 346 #ifdef CONFIG_PHYS_64BIT
 347 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 348 #else
 349 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 350 #endif
 351
 352 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 353                                 | CSPR_PORT_SIZE_8 \
 354                                 | CSPR_MSEL_GPCM \
 355                                 | CSPR_V)
 356 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 357 #define CONFIG_SYS_CSOR3                0x0
 358 /* CPLD Timing parameters for IFC CS3 */
 359 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 360                                         FTIM0_GPCM_TEADC(0x0e) | \
 361                                         FTIM0_GPCM_TEAHC(0x0e))
 362 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 363                                         FTIM1_GPCM_TRAD(0x1f))
 364 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 365                                         FTIM2_GPCM_TCH(0x8) | \
 366                                         FTIM2_GPCM_TWP(0x1f))
 367 #define CONFIG_SYS_CS3_FTIM3            0x0
 368
 369 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 370         defined(CONFIG_RAMBOOT_NAND)
 371 #define CONFIG_SYS_RAMBOOT
 372 #else
 373 #undef CONFIG_SYS_RAMBOOT
 374 #endif
 375
 376 #define CONFIG_SYS_INIT_RAM_LOCK
 377 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 378 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 379
 380 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 381
 382 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 383
 384 /*
 385  * Config the L2 Cache as L2 SRAM
 386  */
 387 #if defined(CONFIG_SPL_BUILD)
 388 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 389 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 390 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 391 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 392 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 393 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 394 #elif defined(CONFIG_MTD_RAW_NAND)
 395 #ifdef CONFIG_TPL_BUILD
 396 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 397 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 398 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 399 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 400 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 401 #else
 402 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 403 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 404 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 405 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 406 #endif
 407 #endif
 408 #endif
 409
 410 /* Serial Port */
 411 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 412 #define CONFIG_SYS_NS16550_SERIAL
 413 #define CONFIG_SYS_NS16550_REG_SIZE     1
 414 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 415 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
 416 #define CONFIG_NS16550_MIN_FUNCTIONS
 417 #endif
 418
 419 #define CONFIG_SYS_BAUDRATE_TABLE       \
 420         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 421
 422 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 423 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 424
 425 /* I2C */
 426 #define I2C_PCA9557_ADDR1               0x18
 427 #define I2C_PCA9557_ADDR2               0x19
 428 #define I2C_PCA9557_BUS_NUM             0
 429
 430 /* I2C EEPROM */
 431 #if defined(CONFIG_TARGET_P1010RDB_PB)
 432 #ifdef CONFIG_ID_EEPROM
 433 #define CONFIG_SYS_I2C_EEPROM_NXID
 434 #endif
 435 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 436 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 437 #endif
 438 /* enable read and write access to EEPROM */
 439
 440 /* RTC */
 441 #define CONFIG_RTC_PT7C4338
 442 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 443
 444 /*
 445  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 446  * used for SLIC
 447  */
 448 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 449 /* eSPI - Enhanced SPI */
 450 #endif
 451
 452 #if defined(CONFIG_TSEC_ENET)
 453 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 454 #define CONFIG_TSEC1    1
 455 #define CONFIG_TSEC1_NAME       "eTSEC1"
 456 #define CONFIG_TSEC2    1
 457 #define CONFIG_TSEC2_NAME       "eTSEC2"
 458 #define CONFIG_TSEC3    1
 459 #define CONFIG_TSEC3_NAME       "eTSEC3"
 460
 461 #define TSEC1_PHY_ADDR          1
 462 #define TSEC2_PHY_ADDR          0
 463 #define TSEC3_PHY_ADDR          2
 464
 465 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 466 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 467 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 468
 469 #define TSEC1_PHYIDX            0
 470 #define TSEC2_PHYIDX            0
 471 #define TSEC3_PHYIDX            0
 472
 473 /* TBI PHY configuration for SGMII mode */
 474 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 475                 TBICR_PHY_RESET \
 476                 | TBICR_ANEG_ENABLE \
 477                 | TBICR_FULL_DUPLEX \
 478                 | TBICR_SPEED1_SET \
 479                 )
 480
 481 #endif  /* CONFIG_TSEC_ENET */
 482
 483 /* SATA */
 484 #define CONFIG_FSL_SATA_V2
 485
 486 #ifdef CONFIG_FSL_SATA
 487 #define CONFIG_SATA1
 488 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 489 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 490 #define CONFIG_SATA2
 491 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 492 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 493
 494 #define CONFIG_LBA48
 495 #endif /* #ifdef CONFIG_FSL_SATA  */
 496
 497 #ifdef CONFIG_MMC
 498 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 499 #endif
 500
 501 #define CONFIG_HAS_FSL_DR_USB
 502
 503 #if defined(CONFIG_HAS_FSL_DR_USB)
 504 #ifdef CONFIG_USB_EHCI_HCD
 505 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 506 #endif
 507 #endif
 508
 509 /*
 510  * Environment
 511  */
 512 #if defined(CONFIG_SDCARD)
 513 #define CONFIG_FSL_FIXED_MMC_LOCATION
 514 #elif defined(CONFIG_MTD_RAW_NAND)
 515 #ifdef CONFIG_TPL_BUILD
 516 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 517 #else
 518 #if defined(CONFIG_TARGET_P1010RDB_PA)
 519 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 520 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 521 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 522 #endif
 523 #endif
 524 #endif
 525
 526 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 527 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 528
 529 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 530                  || defined(CONFIG_FSL_SATA)
 531 #endif
 532
 533 /*
 534  * Miscellaneous configurable options
 535  */
 536
 537 /*
 538  * For booting Linux, the board info and command line data
 539  * have to be in the first 64 MB of memory, since this is
 540  * the maximum mapped by the Linux kernel during initialization.
 541  */
 542 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 543 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 544
 545 /*
 546  * Environment Configuration
 547  */
 548
 549 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 550 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 551
 552 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 553         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 554         "netdev=eth0\0"                                         \
 555         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 556         "loadaddr=1000000\0"                    \
 557         "consoledev=ttyS0\0"                            \
 558         "ramdiskaddr=2000000\0"                 \
 559         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 560         "fdtaddr=1e00000\0"                             \
 561         "fdtfile=p1010rdb.dtb\0"                \
 562         "bdev=sda1\0"   \
 563         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 564         "othbootargs=ramdisk_size=600000\0" \
 565         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 566         "console=$consoledev,$baudrate $othbootargs; "  \
 567         "usb start;"                    \
 568         "fatload usb 0:2 $loadaddr $bootfile;"          \
 569         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 570         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 571         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 572         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 573         "console=$consoledev,$baudrate $othbootargs; "  \
 574         "usb start;"                    \
 575         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 576         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 577         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 578         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 579         BOOTMODE
 580
 581 #if defined(CONFIG_TARGET_P1010RDB_PA)
 582 #define BOOTMODE \
 583         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 584         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 585         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 586         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 587         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 588         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 589
 590 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 591 #define BOOTMODE \
 592         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 593         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 594         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 595         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 596         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 597         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 598         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 599         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 600         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 601         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 602 #endif
 603
 604 #include <asm/fsl_secure_boot.h>
 605
 606 #endif  /* __CONFIG_H */