include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_SPL_FLUSH_IMAGE
  20 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  21 #define CONFIG_SPL_PAD_TO               0x18000
  22 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  23 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  24 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  25 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  26 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  28 #ifdef CONFIG_SPL_BUILD
  29 #define CONFIG_SPL_COMMON_INIT_DDR
  30 #endif
  31 #endif
  32
  33 #ifdef CONFIG_SPIFLASH
  34 #ifdef CONFIG_NXP_ESBC
  35 #define CONFIG_RAMBOOT_SPIFLASH
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  37 #else
  38 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  39 #define CONFIG_SPL_FLUSH_IMAGE
  40 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  41 #define CONFIG_SPL_PAD_TO                       0x18000
  42 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  48 #ifdef CONFIG_SPL_BUILD
  49 #define CONFIG_SPL_COMMON_INIT_DDR
  50 #endif
  51 #endif
  52 #endif
  53
  54 #ifdef CONFIG_MTD_RAW_NAND
  55 #ifdef CONFIG_NXP_ESBC
  56 #define CONFIG_SPL_INIT_MINIMAL
  57 #define CONFIG_SPL_FLUSH_IMAGE
  58 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  59
  60 #define CONFIG_SPL_MAX_SIZE             8192
  61 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  62 #define CONFIG_SPL_RELOC_STACK          0x00100000
  63 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  64 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  65 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  66 #else
  67 #ifdef CONFIG_TPL_BUILD
  68 #define CONFIG_SPL_FLUSH_IMAGE
  69 #define CONFIG_SPL_NAND_INIT
  70 #define CONFIG_SPL_COMMON_INIT_DDR
  71 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  73 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  74 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  75 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  76 #elif defined(CONFIG_SPL_BUILD)
  77 #define CONFIG_SPL_INIT_MINIMAL
  78 #define CONFIG_SPL_NAND_MINIMAL
  79 #define CONFIG_SPL_FLUSH_IMAGE
  80 #define CONFIG_SPL_MAX_SIZE             8192
  81 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  82 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  83 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  84 #endif
  85 #define CONFIG_SPL_PAD_TO       0x20000
  86 #define CONFIG_TPL_PAD_TO       0x20000
  87 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  88 #endif
  89 #endif
  90
  91 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  92 #define CONFIG_RAMBOOT_NAND
  93 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  94 #endif
  95
  96 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  97 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  98 #endif
  99
 100 /* High Level Configuration Options */
 101
 102 #if defined(CONFIG_PCI)
 103 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 104 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 105
 106 /*
 107  * PCI Windows
 108  * Memory space is mapped 1-1, but I/O space must start from 0.
 109  */
 110 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 111 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 112 #ifdef CONFIG_PHYS_64BIT
 113 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 114 #else
 115 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 116 #endif
 117 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 118 #ifdef CONFIG_PHYS_64BIT
 119 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 120 #else
 121 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 122 #endif
 123
 124 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 125 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 126 #ifdef CONFIG_PHYS_64BIT
 127 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 128 #else
 129 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 130 #endif
 131 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 134 #else
 135 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 136 #endif
 137
 138 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 139 #endif
 140
 141 #define CONFIG_HWCONFIG
 142 /*
 143  * These can be toggled for performance analysis, otherwise use default.
 144  */
 145 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 146
 147
 148 #define CONFIG_ENABLE_36BIT_PHYS
 149
 150 /* DDR Setup */
 151 #define CONFIG_SYS_DDR_RAW_TIMING
 152 #define CONFIG_SYS_SPD_BUS_NUM          1
 153 #define SPD_EEPROM_ADDRESS              0x52
 154
 155 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 156
 157 #ifndef __ASSEMBLY__
 158 extern unsigned long get_sdram_size(void);
 159 #endif
 160 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 161 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 162 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 163
 164 /* DDR3 Controller Settings */
 165 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 166 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 167 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 168 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 169 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 170 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 171 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 172 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 173 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 174 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 175 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 176 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 177 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 178 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 179 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 180
 181 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 182 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 183 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 184 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 185 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 186 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 187 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 188 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 189 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 190
 191 /* settings for DDR3 at 667MT/s */
 192 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 193 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 194 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 195 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 196 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 197 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 198 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 199 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 200 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 201
 202 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 203 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 204
 205 /* Don't relocate CCSRBAR while in NAND_SPL */
 206 #ifdef CONFIG_SPL_BUILD
 207 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 208 #endif
 209
 210 /*
 211  * Memory map
 212  *
 213  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 214  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 215  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 216  *
 217  * Localbus non-cacheable
 218  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 219  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 220  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 221  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 222  */
 223
 224 /*
 225  * IFC Definitions
 226  */
 227 /* NOR Flash on IFC */
 228
 229 #define CONFIG_SYS_FLASH_BASE           0xee000000
 230 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 231
 232 #ifdef CONFIG_PHYS_64BIT
 233 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 234 #else
 235 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 236 #endif
 237
 238 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 239                                 CSPR_PORT_SIZE_16 | \
 240                                 CSPR_MSEL_NOR | \
 241                                 CSPR_V)
 242 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 243 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 244 /* NOR Flash Timing Params */
 245 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 246                                 FTIM0_NOR_TEADC(0x5) | \
 247                                 FTIM0_NOR_TEAHC(0x5)
 248 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 249                                 FTIM1_NOR_TRAD_NOR(0x0f)
 250 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 251                                 FTIM2_NOR_TCH(0x4) | \
 252                                 FTIM2_NOR_TWP(0x1c)
 253 #define CONFIG_SYS_NOR_FTIM3    0x0
 254
 255 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 256 #define CONFIG_SYS_FLASH_QUIET_TEST
 257 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 258
 259 #undef CONFIG_SYS_FLASH_CHECKSUM
 260 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 261 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 262
 263 /* CFI for NOR Flash */
 264 #define CONFIG_SYS_FLASH_EMPTY_INFO
 265
 266 /* NAND Flash on IFC */
 267 #define CONFIG_SYS_NAND_BASE            0xff800000
 268 #ifdef CONFIG_PHYS_64BIT
 269 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 270 #else
 271 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 272 #endif
 273
 274 #define CONFIG_MTD_PARTITION
 275
 276 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 277                                 | CSPR_PORT_SIZE_8      \
 278                                 | CSPR_MSEL_NAND        \
 279                                 | CSPR_V)
 280 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 281
 282 #if defined(CONFIG_TARGET_P1010RDB_PA)
 283 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 284                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 285                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 286                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 287                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 288                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 289                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 290
 291 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 292 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 293                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 294                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 295                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 296                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 297                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 298                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 299 #endif
 300
 301 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 302 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 303
 304 #if defined(CONFIG_TARGET_P1010RDB_PA)
 305 /* NAND Flash Timing Params */
 306 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 307                                         FTIM0_NAND_TWP(0x0C)   | \
 308                                         FTIM0_NAND_TWCHT(0x04) | \
 309                                         FTIM0_NAND_TWH(0x05)
 310 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 311                                         FTIM1_NAND_TWBE(0x1d)  | \
 312                                         FTIM1_NAND_TRR(0x07)   | \
 313                                         FTIM1_NAND_TRP(0x0c)
 314 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 315                                         FTIM2_NAND_TREH(0x05) | \
 316                                         FTIM2_NAND_TWHRE(0x0f)
 317 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 318
 319 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 320 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 321 /* ONFI NAND Flash mode0 Timing Params */
 322 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 323                                         FTIM0_NAND_TWP(0x18)   | \
 324                                         FTIM0_NAND_TWCHT(0x07) | \
 325                                         FTIM0_NAND_TWH(0x0a))
 326 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 327                                         FTIM1_NAND_TWBE(0x39)  | \
 328                                         FTIM1_NAND_TRR(0x0e)   | \
 329                                         FTIM1_NAND_TRP(0x18))
 330 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 331                                         FTIM2_NAND_TREH(0x0a)  | \
 332                                         FTIM2_NAND_TWHRE(0x1e))
 333 #define CONFIG_SYS_NAND_FTIM3   0x0
 334 #endif
 335
 336 #define CONFIG_SYS_NAND_DDR_LAW         11
 337
 338 /* Set up IFC registers for boot location NOR/NAND */
 339 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 340 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 341 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 342 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 343 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 344 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 345 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 346 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 347 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 348 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 349 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 350 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 351 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 352 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 353 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 354 #else
 355 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 356 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 357 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 358 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 359 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 360 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 361 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 362 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 363 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 364 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 365 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 366 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 367 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 368 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 369 #endif
 370
 371 /* CPLD on IFC */
 372 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 373
 374 #ifdef CONFIG_PHYS_64BIT
 375 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 376 #else
 377 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 378 #endif
 379
 380 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 381                                 | CSPR_PORT_SIZE_8 \
 382                                 | CSPR_MSEL_GPCM \
 383                                 | CSPR_V)
 384 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 385 #define CONFIG_SYS_CSOR3                0x0
 386 /* CPLD Timing parameters for IFC CS3 */
 387 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 388                                         FTIM0_GPCM_TEADC(0x0e) | \
 389                                         FTIM0_GPCM_TEAHC(0x0e))
 390 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 391                                         FTIM1_GPCM_TRAD(0x1f))
 392 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 393                                         FTIM2_GPCM_TCH(0x8) | \
 394                                         FTIM2_GPCM_TWP(0x1f))
 395 #define CONFIG_SYS_CS3_FTIM3            0x0
 396
 397 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 398         defined(CONFIG_RAMBOOT_NAND)
 399 #define CONFIG_SYS_RAMBOOT
 400 #else
 401 #undef CONFIG_SYS_RAMBOOT
 402 #endif
 403
 404 #define CONFIG_SYS_INIT_RAM_LOCK
 405 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 406 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 407
 408 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 409                                                 - GENERATED_GBL_DATA_SIZE)
 410 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 411
 412 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 413
 414 /*
 415  * Config the L2 Cache as L2 SRAM
 416  */
 417 #if defined(CONFIG_SPL_BUILD)
 418 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 419 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 420 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 421 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 422 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 423 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 424 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 425 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 426 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 427 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 428 #elif defined(CONFIG_MTD_RAW_NAND)
 429 #ifdef CONFIG_TPL_BUILD
 430 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 431 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 432 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 433 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 434 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 435 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 436 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 437 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 438 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 439 #else
 440 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 441 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 442 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 443 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 444 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 445 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 446 #endif
 447 #endif
 448 #endif
 449
 450 /* Serial Port */
 451 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 452 #define CONFIG_SYS_NS16550_SERIAL
 453 #define CONFIG_SYS_NS16550_REG_SIZE     1
 454 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 455 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 456 #define CONFIG_NS16550_MIN_FUNCTIONS
 457 #endif
 458
 459 #define CONFIG_SYS_BAUDRATE_TABLE       \
 460         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 461
 462 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 463 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 464
 465 /* I2C */
 466 #define I2C_PCA9557_ADDR1               0x18
 467 #define I2C_PCA9557_ADDR2               0x19
 468 #define I2C_PCA9557_BUS_NUM             0
 469
 470 /* I2C EEPROM */
 471 #if defined(CONFIG_TARGET_P1010RDB_PB)
 472 #ifdef CONFIG_ID_EEPROM
 473 #define CONFIG_SYS_I2C_EEPROM_NXID
 474 #endif
 475 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 476 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 477 #endif
 478 /* enable read and write access to EEPROM */
 479
 480 /* RTC */
 481 #define CONFIG_RTC_PT7C4338
 482 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 483
 484 /*
 485  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 486  * used for SLIC
 487  */
 488 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 489 /* eSPI - Enhanced SPI */
 490 #endif
 491
 492 #if defined(CONFIG_TSEC_ENET)
 493 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 494 #define CONFIG_TSEC1    1
 495 #define CONFIG_TSEC1_NAME       "eTSEC1"
 496 #define CONFIG_TSEC2    1
 497 #define CONFIG_TSEC2_NAME       "eTSEC2"
 498 #define CONFIG_TSEC3    1
 499 #define CONFIG_TSEC3_NAME       "eTSEC3"
 500
 501 #define TSEC1_PHY_ADDR          1
 502 #define TSEC2_PHY_ADDR          0
 503 #define TSEC3_PHY_ADDR          2
 504
 505 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 506 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 507 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 508
 509 #define TSEC1_PHYIDX            0
 510 #define TSEC2_PHYIDX            0
 511 #define TSEC3_PHYIDX            0
 512
 513 /* TBI PHY configuration for SGMII mode */
 514 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 515                 TBICR_PHY_RESET \
 516                 | TBICR_ANEG_ENABLE \
 517                 | TBICR_FULL_DUPLEX \
 518                 | TBICR_SPEED1_SET \
 519                 )
 520
 521 #endif  /* CONFIG_TSEC_ENET */
 522
 523 /* SATA */
 524 #define CONFIG_FSL_SATA_V2
 525
 526 #ifdef CONFIG_FSL_SATA
 527 #define CONFIG_SATA1
 528 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 529 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 530 #define CONFIG_SATA2
 531 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 532 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 533
 534 #define CONFIG_LBA48
 535 #endif /* #ifdef CONFIG_FSL_SATA  */
 536
 537 #ifdef CONFIG_MMC
 538 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 539 #endif
 540
 541 #define CONFIG_HAS_FSL_DR_USB
 542
 543 #if defined(CONFIG_HAS_FSL_DR_USB)
 544 #ifdef CONFIG_USB_EHCI_HCD
 545 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 546 #endif
 547 #endif
 548
 549 /*
 550  * Environment
 551  */
 552 #if defined(CONFIG_SDCARD)
 553 #define CONFIG_FSL_FIXED_MMC_LOCATION
 554 #elif defined(CONFIG_MTD_RAW_NAND)
 555 #ifdef CONFIG_TPL_BUILD
 556 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 557 #else
 558 #if defined(CONFIG_TARGET_P1010RDB_PA)
 559 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 560 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 561 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 562 #endif
 563 #endif
 564 #endif
 565
 566 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 567 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 568
 569 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 570                  || defined(CONFIG_FSL_SATA)
 571 #endif
 572
 573 /*
 574  * Miscellaneous configurable options
 575  */
 576
 577 /*
 578  * For booting Linux, the board info and command line data
 579  * have to be in the first 64 MB of memory, since this is
 580  * the maximum mapped by the Linux kernel during initialization.
 581  */
 582 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 583 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 584
 585 /*
 586  * Environment Configuration
 587  */
 588
 589 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 590 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 591
 592 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 593         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 594         "netdev=eth0\0"                                         \
 595         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 596         "loadaddr=1000000\0"                    \
 597         "consoledev=ttyS0\0"                            \
 598         "ramdiskaddr=2000000\0"                 \
 599         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 600         "fdtaddr=1e00000\0"                             \
 601         "fdtfile=p1010rdb.dtb\0"                \
 602         "bdev=sda1\0"   \
 603         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 604         "othbootargs=ramdisk_size=600000\0" \
 605         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 606         "console=$consoledev,$baudrate $othbootargs; "  \
 607         "usb start;"                    \
 608         "fatload usb 0:2 $loadaddr $bootfile;"          \
 609         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 610         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 611         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 612         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 613         "console=$consoledev,$baudrate $othbootargs; "  \
 614         "usb start;"                    \
 615         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 616         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 617         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 618         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 619         BOOTMODE
 620
 621 #if defined(CONFIG_TARGET_P1010RDB_PA)
 622 #define BOOTMODE \
 623         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 624         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 625         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 626         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 627         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 628         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 629
 630 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 631 #define BOOTMODE \
 632         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 633         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 634         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 635         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 636         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 637         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 638         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 639         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 640         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 641         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 642 #endif
 643
 644 #include <asm/fsl_secure_boot.h>
 645
 646 #endif  /* __CONFIG_H */