include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_SPL_FLUSH_IMAGE
  20 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  21 #define CONFIG_SPL_PAD_TO               0x18000
  22 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  23 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  24 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  25 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  26 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  28 #ifdef CONFIG_SPL_BUILD
  29 #define CONFIG_SPL_COMMON_INIT_DDR
  30 #endif
  31 #endif
  32
  33 #ifdef CONFIG_SPIFLASH
  34 #ifdef CONFIG_NXP_ESBC
  35 #define CONFIG_RAMBOOT_SPIFLASH
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  37 #else
  38 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  39 #define CONFIG_SPL_FLUSH_IMAGE
  40 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  41 #define CONFIG_SPL_PAD_TO                       0x18000
  42 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  48 #ifdef CONFIG_SPL_BUILD
  49 #define CONFIG_SPL_COMMON_INIT_DDR
  50 #endif
  51 #endif
  52 #endif
  53
  54 #ifdef CONFIG_MTD_RAW_NAND
  55 #ifdef CONFIG_NXP_ESBC
  56 #define CONFIG_SPL_INIT_MINIMAL
  57 #define CONFIG_SPL_FLUSH_IMAGE
  58 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  59
  60 #define CONFIG_SPL_MAX_SIZE             8192
  61 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  62 #define CONFIG_SPL_RELOC_STACK          0x00100000
  63 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  64 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  65 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  66 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  67 #else
  68 #ifdef CONFIG_TPL_BUILD
  69 #define CONFIG_SPL_FLUSH_IMAGE
  70 #define CONFIG_SPL_NAND_INIT
  71 #define CONFIG_SPL_COMMON_INIT_DDR
  72 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  73 #define CONFIG_TPL_TEXT_BASE            0xD0001000
  74 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  75 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  76 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  77 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  78 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  79 #elif defined(CONFIG_SPL_BUILD)
  80 #define CONFIG_SPL_INIT_MINIMAL
  81 #define CONFIG_SPL_NAND_MINIMAL
  82 #define CONFIG_SPL_FLUSH_IMAGE
  83 #define CONFIG_SPL_MAX_SIZE             8192
  84 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  85 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  86 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  87 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  88 #endif
  89 #define CONFIG_SPL_PAD_TO       0x20000
  90 #define CONFIG_TPL_PAD_TO       0x20000
  91 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  92 #endif
  93 #endif
  94
  95 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  96 #define CONFIG_RAMBOOT_NAND
  97 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  98 #endif
  99
 100 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 101 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 102 #endif
 103
 104 #ifdef CONFIG_TPL_BUILD
 105 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
 106 #elif defined(CONFIG_SPL_BUILD)
 107 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 108 #else
 109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 110 #endif
 111
 112 /* High Level Configuration Options */
 113
 114 #if defined(CONFIG_PCI)
 115 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 116 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 117 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 118
 119 /*
 120  * PCI Windows
 121  * Memory space is mapped 1-1, but I/O space must start from 0.
 122  */
 123 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 124 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 125 #ifdef CONFIG_PHYS_64BIT
 126 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 127 #else
 128 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 129 #endif
 130 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 131 #ifdef CONFIG_PHYS_64BIT
 132 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 133 #else
 134 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 135 #endif
 136
 137 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 138 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 139 #ifdef CONFIG_PHYS_64BIT
 140 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 141 #else
 142 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 143 #endif
 144 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 145 #ifdef CONFIG_PHYS_64BIT
 146 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 147 #else
 148 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 149 #endif
 150
 151 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 152 #endif
 153
 154 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 155
 156 #define CONFIG_HWCONFIG
 157 /*
 158  * These can be toggled for performance analysis, otherwise use default.
 159  */
 160 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 161 #define CONFIG_BTB                      /* toggle branch predition */
 162
 163
 164 #define CONFIG_ENABLE_36BIT_PHYS
 165
 166 /* DDR Setup */
 167 #define CONFIG_SYS_DDR_RAW_TIMING
 168 #define CONFIG_SYS_SPD_BUS_NUM          1
 169 #define SPD_EEPROM_ADDRESS              0x52
 170
 171 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 172
 173 #ifndef __ASSEMBLY__
 174 extern unsigned long get_sdram_size(void);
 175 #endif
 176 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 177 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 178 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 179
 180 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 181 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 182
 183 /* DDR3 Controller Settings */
 184 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 185 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 186 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 187 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 188 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 189 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 190 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 191 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 192 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 193 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 194 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 195 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 196 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 197 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 198 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 199
 200 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 201 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 202 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 203 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 204 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 205 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 206 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 207 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 208 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 209
 210 /* settings for DDR3 at 667MT/s */
 211 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 212 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 213 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 214 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 215 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 216 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 217 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 218 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 219 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 220
 221 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 222 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 223
 224 /* Don't relocate CCSRBAR while in NAND_SPL */
 225 #ifdef CONFIG_SPL_BUILD
 226 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 227 #endif
 228
 229 /*
 230  * Memory map
 231  *
 232  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 233  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 234  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 235  *
 236  * Localbus non-cacheable
 237  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 238  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 239  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 240  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 241  */
 242
 243 /*
 244  * IFC Definitions
 245  */
 246 /* NOR Flash on IFC */
 247
 248 #define CONFIG_SYS_FLASH_BASE           0xee000000
 249 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 250
 251 #ifdef CONFIG_PHYS_64BIT
 252 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 253 #else
 254 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 255 #endif
 256
 257 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 258                                 CSPR_PORT_SIZE_16 | \
 259                                 CSPR_MSEL_NOR | \
 260                                 CSPR_V)
 261 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 262 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 263 /* NOR Flash Timing Params */
 264 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 265                                 FTIM0_NOR_TEADC(0x5) | \
 266                                 FTIM0_NOR_TEAHC(0x5)
 267 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 268                                 FTIM1_NOR_TRAD_NOR(0x0f)
 269 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 270                                 FTIM2_NOR_TCH(0x4) | \
 271                                 FTIM2_NOR_TWP(0x1c)
 272 #define CONFIG_SYS_NOR_FTIM3    0x0
 273
 274 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 275 #define CONFIG_SYS_FLASH_QUIET_TEST
 276 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 277 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 278
 279 #undef CONFIG_SYS_FLASH_CHECKSUM
 280 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 281 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 282
 283 /* CFI for NOR Flash */
 284 #define CONFIG_SYS_FLASH_EMPTY_INFO
 285
 286 /* NAND Flash on IFC */
 287 #define CONFIG_SYS_NAND_BASE            0xff800000
 288 #ifdef CONFIG_PHYS_64BIT
 289 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 290 #else
 291 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 292 #endif
 293
 294 #define CONFIG_MTD_PARTITION
 295
 296 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 297                                 | CSPR_PORT_SIZE_8      \
 298                                 | CSPR_MSEL_NAND        \
 299                                 | CSPR_V)
 300 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 301
 302 #if defined(CONFIG_TARGET_P1010RDB_PA)
 303 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 304                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 305                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 306                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 307                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 308                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 309                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 310
 311 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 312 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 313                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 314                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 315                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 316                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 317                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 318                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 319 #endif
 320
 321 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 322 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 323
 324 #if defined(CONFIG_TARGET_P1010RDB_PA)
 325 /* NAND Flash Timing Params */
 326 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 327                                         FTIM0_NAND_TWP(0x0C)   | \
 328                                         FTIM0_NAND_TWCHT(0x04) | \
 329                                         FTIM0_NAND_TWH(0x05)
 330 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 331                                         FTIM1_NAND_TWBE(0x1d)  | \
 332                                         FTIM1_NAND_TRR(0x07)   | \
 333                                         FTIM1_NAND_TRP(0x0c)
 334 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 335                                         FTIM2_NAND_TREH(0x05) | \
 336                                         FTIM2_NAND_TWHRE(0x0f)
 337 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 338
 339 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 340 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 341 /* ONFI NAND Flash mode0 Timing Params */
 342 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 343                                         FTIM0_NAND_TWP(0x18)   | \
 344                                         FTIM0_NAND_TWCHT(0x07) | \
 345                                         FTIM0_NAND_TWH(0x0a))
 346 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 347                                         FTIM1_NAND_TWBE(0x39)  | \
 348                                         FTIM1_NAND_TRR(0x0e)   | \
 349                                         FTIM1_NAND_TRP(0x18))
 350 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 351                                         FTIM2_NAND_TREH(0x0a)  | \
 352                                         FTIM2_NAND_TWHRE(0x1e))
 353 #define CONFIG_SYS_NAND_FTIM3   0x0
 354 #endif
 355
 356 #define CONFIG_SYS_NAND_DDR_LAW         11
 357
 358 /* Set up IFC registers for boot location NOR/NAND */
 359 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 360 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 361 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 362 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 363 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 364 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 365 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 366 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 367 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 368 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 369 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 370 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 371 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 372 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 373 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 374 #else
 375 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 376 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 377 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 378 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 379 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 380 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 381 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 382 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 383 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 384 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 385 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 386 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 387 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 388 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 389 #endif
 390
 391 /* CPLD on IFC */
 392 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 393
 394 #ifdef CONFIG_PHYS_64BIT
 395 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 396 #else
 397 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 398 #endif
 399
 400 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 401                                 | CSPR_PORT_SIZE_8 \
 402                                 | CSPR_MSEL_GPCM \
 403                                 | CSPR_V)
 404 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 405 #define CONFIG_SYS_CSOR3                0x0
 406 /* CPLD Timing parameters for IFC CS3 */
 407 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 408                                         FTIM0_GPCM_TEADC(0x0e) | \
 409                                         FTIM0_GPCM_TEAHC(0x0e))
 410 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 411                                         FTIM1_GPCM_TRAD(0x1f))
 412 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 413                                         FTIM2_GPCM_TCH(0x8) | \
 414                                         FTIM2_GPCM_TWP(0x1f))
 415 #define CONFIG_SYS_CS3_FTIM3            0x0
 416
 417 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 418         defined(CONFIG_RAMBOOT_NAND)
 419 #define CONFIG_SYS_RAMBOOT
 420 #else
 421 #undef CONFIG_SYS_RAMBOOT
 422 #endif
 423
 424 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 425 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 426 #define CONFIG_A003399_NOR_WORKAROUND
 427 #endif
 428 #endif
 429
 430 #define CONFIG_SYS_INIT_RAM_LOCK
 431 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 432 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 433
 434 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 435                                                 - GENERATED_GBL_DATA_SIZE)
 436 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 437
 438 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 439
 440 /*
 441  * Config the L2 Cache as L2 SRAM
 442  */
 443 #if defined(CONFIG_SPL_BUILD)
 444 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 445 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 446 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 447 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 448 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 449 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 450 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 451 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 452 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 453 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 454 #elif defined(CONFIG_MTD_RAW_NAND)
 455 #ifdef CONFIG_TPL_BUILD
 456 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 457 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 458 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 459 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 460 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 461 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 462 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 463 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 464 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 465 #else
 466 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 467 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 468 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 469 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 470 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 471 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 472 #endif
 473 #endif
 474 #endif
 475
 476 /* Serial Port */
 477 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 478 #define CONFIG_SYS_NS16550_SERIAL
 479 #define CONFIG_SYS_NS16550_REG_SIZE     1
 480 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 481 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 482 #define CONFIG_NS16550_MIN_FUNCTIONS
 483 #endif
 484
 485 #define CONFIG_SYS_BAUDRATE_TABLE       \
 486         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 487
 488 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 489 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 490
 491 /* I2C */
 492 #define I2C_PCA9557_ADDR1               0x18
 493 #define I2C_PCA9557_ADDR2               0x19
 494 #define I2C_PCA9557_BUS_NUM             0
 495
 496 /* I2C EEPROM */
 497 #if defined(CONFIG_TARGET_P1010RDB_PB)
 498 #ifdef CONFIG_ID_EEPROM
 499 #define CONFIG_SYS_I2C_EEPROM_NXID
 500 #endif
 501 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 502 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 503 #endif
 504 /* enable read and write access to EEPROM */
 505
 506 /* RTC */
 507 #define CONFIG_RTC_PT7C4338
 508 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 509
 510 /*
 511  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 512  * used for SLIC
 513  */
 514 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 515 /* eSPI - Enhanced SPI */
 516 #endif
 517
 518 #if defined(CONFIG_TSEC_ENET)
 519 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 520 #define CONFIG_TSEC1    1
 521 #define CONFIG_TSEC1_NAME       "eTSEC1"
 522 #define CONFIG_TSEC2    1
 523 #define CONFIG_TSEC2_NAME       "eTSEC2"
 524 #define CONFIG_TSEC3    1
 525 #define CONFIG_TSEC3_NAME       "eTSEC3"
 526
 527 #define TSEC1_PHY_ADDR          1
 528 #define TSEC2_PHY_ADDR          0
 529 #define TSEC3_PHY_ADDR          2
 530
 531 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 532 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 533 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 534
 535 #define TSEC1_PHYIDX            0
 536 #define TSEC2_PHYIDX            0
 537 #define TSEC3_PHYIDX            0
 538
 539 #define CONFIG_ETHPRIME         "eTSEC1"
 540
 541 /* TBI PHY configuration for SGMII mode */
 542 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 543                 TBICR_PHY_RESET \
 544                 | TBICR_ANEG_ENABLE \
 545                 | TBICR_FULL_DUPLEX \
 546                 | TBICR_SPEED1_SET \
 547                 )
 548
 549 #endif  /* CONFIG_TSEC_ENET */
 550
 551 /* SATA */
 552 #define CONFIG_FSL_SATA_V2
 553
 554 #ifdef CONFIG_FSL_SATA
 555 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 556 #define CONFIG_SATA1
 557 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 558 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 559 #define CONFIG_SATA2
 560 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 561 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 562
 563 #define CONFIG_LBA48
 564 #endif /* #ifdef CONFIG_FSL_SATA  */
 565
 566 #ifdef CONFIG_MMC
 567 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 568 #endif
 569
 570 #define CONFIG_HAS_FSL_DR_USB
 571
 572 #if defined(CONFIG_HAS_FSL_DR_USB)
 573 #ifdef CONFIG_USB_EHCI_HCD
 574 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 575 #endif
 576 #endif
 577
 578 /*
 579  * Environment
 580  */
 581 #if defined(CONFIG_SDCARD)
 582 #define CONFIG_FSL_FIXED_MMC_LOCATION
 583 #elif defined(CONFIG_MTD_RAW_NAND)
 584 #ifdef CONFIG_TPL_BUILD
 585 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 586 #else
 587 #if defined(CONFIG_TARGET_P1010RDB_PA)
 588 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 589 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 590 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 591 #endif
 592 #endif
 593 #endif
 594
 595 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 596 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 597
 598 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 599                  || defined(CONFIG_FSL_SATA)
 600 #endif
 601
 602 /*
 603  * Miscellaneous configurable options
 604  */
 605
 606 /*
 607  * For booting Linux, the board info and command line data
 608  * have to be in the first 64 MB of memory, since this is
 609  * the maximum mapped by the Linux kernel during initialization.
 610  */
 611 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 612 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 613
 614 /*
 615  * Environment Configuration
 616  */
 617
 618 #if defined(CONFIG_TSEC_ENET)
 619 #define CONFIG_HAS_ETH0
 620 #define CONFIG_HAS_ETH1
 621 #define CONFIG_HAS_ETH2
 622 #endif
 623
 624 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 625 #define CONFIG_BOOTFILE         "uImage"
 626 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 627
 628 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 629         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 630         "netdev=eth0\0"                                         \
 631         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 632         "loadaddr=1000000\0"                    \
 633         "consoledev=ttyS0\0"                            \
 634         "ramdiskaddr=2000000\0"                 \
 635         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 636         "fdtaddr=1e00000\0"                             \
 637         "fdtfile=p1010rdb.dtb\0"                \
 638         "bdev=sda1\0"   \
 639         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 640         "othbootargs=ramdisk_size=600000\0" \
 641         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 642         "console=$consoledev,$baudrate $othbootargs; "  \
 643         "usb start;"                    \
 644         "fatload usb 0:2 $loadaddr $bootfile;"          \
 645         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 646         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 647         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 648         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 649         "console=$consoledev,$baudrate $othbootargs; "  \
 650         "usb start;"                    \
 651         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 652         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 653         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 654         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 655         CONFIG_BOOTMODE
 656
 657 #if defined(CONFIG_TARGET_P1010RDB_PA)
 658 #define CONFIG_BOOTMODE \
 659         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 660         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 661         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 662         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 663         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 664         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 665
 666 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 667 #define CONFIG_BOOTMODE \
 668         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 669         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 670         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 671         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 672         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 673         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 674         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 675         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 676         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 677         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 678 #endif
 679
 680 #include <asm/fsl_secure_boot.h>
 681
 682 #endif  /* __CONFIG_H */