include/configs/P1010RDB.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #define CONFIG_P1010
  17 #define CONFIG_E500                     /* BOOKE e500 family */
  18 #include <asm/config_mpc85xx.h>
  19 #define CONFIG_NAND_FSL_IFC
  20
  21 #ifdef CONFIG_SDCARD
  22 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  23 #define CONFIG_SPL_SERIAL_SUPPORT
  24 #define CONFIG_SPL_MMC_MINIMAL
  25 #define CONFIG_SPL_FLUSH_IMAGE
  26 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  27 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  28 #define CONFIG_SYS_TEXT_BASE            0x11001000
  29 #define CONFIG_SPL_TEXT_BASE            0xD0001000
  30 #define CONFIG_SPL_PAD_TO               0x18000
  31 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  32 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  33 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  34 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  35 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  37 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  38 #define CONFIG_SPL_MMC_BOOT
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SPL_COMMON_INIT_DDR
  41 #endif
  42 #endif
  43
  44 #ifdef CONFIG_SPIFLASH
  45 #ifdef CONFIG_SECURE_BOOT
  46 #define CONFIG_RAMBOOT_SPIFLASH
  47 #define CONFIG_SYS_TEXT_BASE            0x11000000
  48 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  49 #else
  50 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  51 #define CONFIG_SPL_SERIAL_SUPPORT
  52 #define CONFIG_SPL_SPI_SUPPORT
  53 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  54 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  55 #define CONFIG_SPL_FLUSH_IMAGE
  56 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  57 #define CONFIG_FSL_LAW         /* Use common FSL init code */
  58 #define CONFIG_SYS_TEXT_BASE                    0x11001000
  59 #define CONFIG_SPL_TEXT_BASE                    0xD0001000
  60 #define CONFIG_SPL_PAD_TO                       0x18000
  61 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  67 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  68 #define CONFIG_SPL_SPI_BOOT
  69 #ifdef CONFIG_SPL_BUILD
  70 #define CONFIG_SPL_COMMON_INIT_DDR
  71 #endif
  72 #endif
  73 #endif
  74
  75 #ifdef CONFIG_NAND
  76 #ifdef CONFIG_SECURE_BOOT
  77 #define CONFIG_SPL_INIT_MINIMAL
  78 #define CONFIG_SPL_SERIAL_SUPPORT
  79 #define CONFIG_SPL_NAND_SUPPORT
  80 #define CONFIG_SPL_NAND_BOOT
  81 #define CONFIG_SPL_FLUSH_IMAGE
  82 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  83
  84 #define CONFIG_SYS_TEXT_BASE            0x00201000
  85 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
  86 #define CONFIG_SPL_MAX_SIZE             8192
  87 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  88 #define CONFIG_SPL_RELOC_STACK          0x00100000
  89 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  90 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  91 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  92 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  93 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  94 #else
  95 #ifdef CONFIG_TPL_BUILD
  96 #define CONFIG_SPL_NAND_BOOT
  97 #define CONFIG_SPL_FLUSH_IMAGE
  98 #define CONFIG_SPL_NAND_INIT
  99 #define CONFIG_TPL_SERIAL_SUPPORT
 100 #define CONFIG_TPL_NAND_SUPPORT
 101 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT
 102 #define CONFIG_SPL_COMMON_INIT_DDR
 103 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
 104 #define CONFIG_SPL_TEXT_BASE            0xD0001000
 105 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 106 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
 107 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
 108 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 109 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 110 #elif defined(CONFIG_SPL_BUILD)
 111 #define CONFIG_SPL_INIT_MINIMAL
 112 #define CONFIG_SPL_SERIAL_SUPPORT
 113 #define CONFIG_SPL_NAND_SUPPORT
 114 #define CONFIG_SPL_NAND_MINIMAL
 115 #define CONFIG_SPL_FLUSH_IMAGE
 116 #define CONFIG_SPL_TEXT_BASE            0xff800000
 117 #define CONFIG_SPL_MAX_SIZE             8192
 118 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 119 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
 120 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
 121 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 122 #endif
 123 #define CONFIG_SPL_PAD_TO       0x20000
 124 #define CONFIG_TPL_PAD_TO       0x20000
 125 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
 126 #define CONFIG_SYS_TEXT_BASE    0x11001000
 127 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 128 #endif
 129 #endif
 130
 131 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
 132 #define CONFIG_RAMBOOT_NAND
 133 #define CONFIG_SYS_TEXT_BASE            0x11000000
 134 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
 135 #endif
 136
 137 #ifndef CONFIG_SYS_TEXT_BASE
 138 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 139 #endif
 140
 141 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 142 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 143 #endif
 144
 145 #ifdef CONFIG_SPL_BUILD
 146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 147 #else
 148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 149 #endif
 150
 151 /* High Level Configuration Options */
 152 #define CONFIG_BOOKE                    /* BOOKE */
 153 #define CONFIG_E500                     /* BOOKE e500 family */
 154 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 155 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 156 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 157
 158 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 159 #if defined(CONFIG_PCI)
 160 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 161 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 162 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 163 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 164 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 165 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 166
 167 #define CONFIG_CMD_PCI
 168
 169 /*
 170  * PCI Windows
 171  * Memory space is mapped 1-1, but I/O space must start from 0.
 172  */
 173 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 174 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
 175 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 176 #ifdef CONFIG_PHYS_64BIT
 177 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 178 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 179 #else
 180 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 181 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 182 #endif
 183 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 184 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 185 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 186 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 187 #ifdef CONFIG_PHYS_64BIT
 188 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 189 #else
 190 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 191 #endif
 192
 193 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 194 #if defined(CONFIG_P1010RDB_PA)
 195 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
 196 #elif defined(CONFIG_P1010RDB_PB)
 197 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
 198 #endif
 199 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 200 #ifdef CONFIG_PHYS_64BIT
 201 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 202 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 203 #else
 204 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 205 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 206 #endif
 207 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 208 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 209 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 210 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 211 #ifdef CONFIG_PHYS_64BIT
 212 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 213 #else
 214 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 215 #endif
 216
 217 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 218
 219 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 220 #define CONFIG_DOS_PARTITION
 221 #endif
 222
 223 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 224 #define CONFIG_TSEC_ENET
 225 #define CONFIG_ENV_OVERWRITE
 226
 227 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 228 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 229
 230 #define CONFIG_MISC_INIT_R
 231 #define CONFIG_HWCONFIG
 232 /*
 233  * These can be toggled for performance analysis, otherwise use default.
 234  */
 235 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 236 #define CONFIG_BTB                      /* toggle branch predition */
 237
 238 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 239
 240 #define CONFIG_ENABLE_36BIT_PHYS
 241
 242 #ifdef CONFIG_PHYS_64BIT
 243 #define CONFIG_ADDR_MAP                 1
 244 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 245 #endif
 246
 247 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 248 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 249 #define CONFIG_PANIC_HANG               /* do not reset board on panic */
 250
 251 /* DDR Setup */
 252 #define CONFIG_SYS_FSL_DDR3
 253 #define CONFIG_SYS_DDR_RAW_TIMING
 254 #define CONFIG_DDR_SPD
 255 #define CONFIG_SYS_SPD_BUS_NUM          1
 256 #define SPD_EEPROM_ADDRESS              0x52
 257
 258 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 259
 260 #ifndef __ASSEMBLY__
 261 extern unsigned long get_sdram_size(void);
 262 #endif
 263 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 264 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 265 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 266
 267 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 268 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 269
 270 /* DDR3 Controller Settings */
 271 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 272 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 273 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 274 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 275 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 276 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 277 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 278 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 279 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 280 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 281 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 282 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 283 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 284 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 285 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 286
 287 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 288 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 289 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 290 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 291 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 292 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 293 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 294 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 295 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 296
 297 /* settings for DDR3 at 667MT/s */
 298 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 299 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 300 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 301 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 302 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 303 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 304 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 305 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 306 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 307
 308 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 309 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 310
 311 /* Don't relocate CCSRBAR while in NAND_SPL */
 312 #ifdef CONFIG_SPL_BUILD
 313 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 314 #endif
 315
 316 /*
 317  * Memory map
 318  *
 319  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 320  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 321  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 322  *
 323  * Localbus non-cacheable
 324  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 325  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 326  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 327  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 328  */
 329
 330 /*
 331  * IFC Definitions
 332  */
 333 /* NOR Flash on IFC */
 334 #ifdef CONFIG_SPL_BUILD
 335 #define CONFIG_SYS_NO_FLASH
 336 #endif
 337
 338 #define CONFIG_SYS_FLASH_BASE           0xee000000
 339 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 340
 341 #ifdef CONFIG_PHYS_64BIT
 342 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 343 #else
 344 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 345 #endif
 346
 347 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 348                                 CSPR_PORT_SIZE_16 | \
 349                                 CSPR_MSEL_NOR | \
 350                                 CSPR_V)
 351 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 352 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 353 /* NOR Flash Timing Params */
 354 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 355                                 FTIM0_NOR_TEADC(0x5) | \
 356                                 FTIM0_NOR_TEAHC(0x5)
 357 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 358                                 FTIM1_NOR_TRAD_NOR(0x0f)
 359 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 360                                 FTIM2_NOR_TCH(0x4) | \
 361                                 FTIM2_NOR_TWP(0x1c)
 362 #define CONFIG_SYS_NOR_FTIM3    0x0
 363
 364 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 365 #define CONFIG_SYS_FLASH_QUIET_TEST
 366 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 367 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 368
 369 #undef CONFIG_SYS_FLASH_CHECKSUM
 370 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 371 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 372
 373 /* CFI for NOR Flash */
 374 #define CONFIG_FLASH_CFI_DRIVER
 375 #define CONFIG_SYS_FLASH_CFI
 376 #define CONFIG_SYS_FLASH_EMPTY_INFO
 377 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 378
 379 /* NAND Flash on IFC */
 380 #define CONFIG_SYS_NAND_BASE            0xff800000
 381 #ifdef CONFIG_PHYS_64BIT
 382 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 383 #else
 384 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 385 #endif
 386
 387 #define CONFIG_MTD_DEVICE
 388 #define CONFIG_MTD_PARTITION
 389 #define CONFIG_CMD_MTDPARTS
 390 #define MTDIDS_DEFAULT                  "nand0=ff800000.flash"
 391 #define MTDPARTS_DEFAULT                \
 392         "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
 393
 394 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 395                                 | CSPR_PORT_SIZE_8      \
 396                                 | CSPR_MSEL_NAND        \
 397                                 | CSPR_V)
 398 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 399
 400 #if defined(CONFIG_P1010RDB_PA)
 401 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 402                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 403                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 404                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 405                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 406                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 407                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 408 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 409
 410 #elif defined(CONFIG_P1010RDB_PB)
 411 #define CONFIG_SYS_NAND_ONFI_DETECTION
 412 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 413                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 414                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 415                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 416                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 417                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 418                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 419 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 420 #endif
 421
 422 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 423 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 424 #define CONFIG_CMD_NAND
 425
 426 #if defined(CONFIG_P1010RDB_PA)
 427 /* NAND Flash Timing Params */
 428 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 429                                         FTIM0_NAND_TWP(0x0C)   | \
 430                                         FTIM0_NAND_TWCHT(0x04) | \
 431                                         FTIM0_NAND_TWH(0x05)
 432 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 433                                         FTIM1_NAND_TWBE(0x1d)  | \
 434                                         FTIM1_NAND_TRR(0x07)   | \
 435                                         FTIM1_NAND_TRP(0x0c)
 436 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 437                                         FTIM2_NAND_TREH(0x05) | \
 438                                         FTIM2_NAND_TWHRE(0x0f)
 439 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 440
 441 #elif defined(CONFIG_P1010RDB_PB)
 442 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 443 /* ONFI NAND Flash mode0 Timing Params */
 444 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 445                                         FTIM0_NAND_TWP(0x18)   | \
 446                                         FTIM0_NAND_TWCHT(0x07) | \
 447                                         FTIM0_NAND_TWH(0x0a))
 448 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 449                                         FTIM1_NAND_TWBE(0x39)  | \
 450                                         FTIM1_NAND_TRR(0x0e)   | \
 451                                         FTIM1_NAND_TRP(0x18))
 452 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 453                                         FTIM2_NAND_TREH(0x0a)  | \
 454                                         FTIM2_NAND_TWHRE(0x1e))
 455 #define CONFIG_SYS_NAND_FTIM3   0x0
 456 #endif
 457
 458 #define CONFIG_SYS_NAND_DDR_LAW         11
 459
 460 /* Set up IFC registers for boot location NOR/NAND */
 461 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 462 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 463 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 464 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 465 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 466 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 467 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 468 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 469 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 470 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 471 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 472 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 473 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 474 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 475 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 476 #else
 477 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 478 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 479 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 480 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 481 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 482 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 483 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 484 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 485 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 486 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 487 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 488 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 489 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 490 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 491 #endif
 492
 493 /* CPLD on IFC */
 494 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 495
 496 #ifdef CONFIG_PHYS_64BIT
 497 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 498 #else
 499 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 500 #endif
 501
 502 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 503                                 | CSPR_PORT_SIZE_8 \
 504                                 | CSPR_MSEL_GPCM \
 505                                 | CSPR_V)
 506 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 507 #define CONFIG_SYS_CSOR3                0x0
 508 /* CPLD Timing parameters for IFC CS3 */
 509 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 510                                         FTIM0_GPCM_TEADC(0x0e) | \
 511                                         FTIM0_GPCM_TEAHC(0x0e))
 512 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 513                                         FTIM1_GPCM_TRAD(0x1f))
 514 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 515                                         FTIM2_GPCM_TCH(0x8) | \
 516                                         FTIM2_GPCM_TWP(0x1f))
 517 #define CONFIG_SYS_CS3_FTIM3            0x0
 518
 519 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 520         defined(CONFIG_RAMBOOT_NAND)
 521 #define CONFIG_SYS_RAMBOOT
 522 #define CONFIG_SYS_EXTRA_ENV_RELOC
 523 #else
 524 #undef CONFIG_SYS_RAMBOOT
 525 #endif
 526
 527 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 528 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 529 #define CONFIG_A003399_NOR_WORKAROUND
 530 #endif
 531 #endif
 532
 533 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 534 #define CONFIG_BOARD_EARLY_INIT_R
 535
 536 #define CONFIG_SYS_INIT_RAM_LOCK
 537 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 538 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 539
 540 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 541                                                 - GENERATED_GBL_DATA_SIZE)
 542 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 543
 544 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 545 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 546
 547 /*
 548  * Config the L2 Cache as L2 SRAM
 549  */
 550 #if defined(CONFIG_SPL_BUILD)
 551 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 552 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 553 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 554 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 555 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 556 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 557 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 558 #define CONFIG_SPL_RELOC_STACK_SIZE     (16 << 10)
 559 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 560 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 561 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 562 #elif defined(CONFIG_NAND)
 563 #ifdef CONFIG_TPL_BUILD
 564 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 565 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 566 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 567 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 568 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 569 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 570 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 571 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 572 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 573 #else
 574 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 575 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 576 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 577 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 578 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 579 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 580 #endif
 581 #endif
 582 #endif
 583
 584 /* Serial Port */
 585 #define CONFIG_CONS_INDEX       1
 586 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 587 #define CONFIG_SYS_NS16550_SERIAL
 588 #define CONFIG_SYS_NS16550_REG_SIZE     1
 589 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 590 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 591 #define CONFIG_NS16550_MIN_FUNCTIONS
 592 #endif
 593
 594 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 595
 596 #define CONFIG_SYS_BAUDRATE_TABLE       \
 597         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 598
 599 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 600 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 601
 602 /* I2C */
 603 #define CONFIG_SYS_I2C
 604 #define CONFIG_SYS_I2C_FSL
 605 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 606 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 607 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 608 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 609 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 610 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 611 #define I2C_PCA9557_ADDR1               0x18
 612 #define I2C_PCA9557_ADDR2               0x19
 613 #define I2C_PCA9557_BUS_NUM             0
 614
 615 /* I2C EEPROM */
 616 #if defined(CONFIG_P1010RDB_PB)
 617 #define CONFIG_ID_EEPROM
 618 #ifdef CONFIG_ID_EEPROM
 619 #define CONFIG_SYS_I2C_EEPROM_NXID
 620 #endif
 621 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 622 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 623 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 624 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 625 #endif
 626 /* enable read and write access to EEPROM */
 627 #define CONFIG_CMD_EEPROM
 628 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 629 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 630 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 631
 632 /* RTC */
 633 #define CONFIG_RTC_PT7C4338
 634 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 635
 636 /*
 637  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 638  * used for SLIC
 639  */
 640 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 641 /* eSPI - Enhanced SPI */
 642 #define CONFIG_SF_DEFAULT_SPEED         10000000
 643 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 644 #endif
 645
 646 #if defined(CONFIG_TSEC_ENET)
 647 #define CONFIG_MII                      /* MII PHY management */
 648 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 649 #define CONFIG_TSEC1    1
 650 #define CONFIG_TSEC1_NAME       "eTSEC1"
 651 #define CONFIG_TSEC2    1
 652 #define CONFIG_TSEC2_NAME       "eTSEC2"
 653 #define CONFIG_TSEC3    1
 654 #define CONFIG_TSEC3_NAME       "eTSEC3"
 655
 656 #define TSEC1_PHY_ADDR          1
 657 #define TSEC2_PHY_ADDR          0
 658 #define TSEC3_PHY_ADDR          2
 659
 660 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 661 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 662 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 663
 664 #define TSEC1_PHYIDX            0
 665 #define TSEC2_PHYIDX            0
 666 #define TSEC3_PHYIDX            0
 667
 668 #define CONFIG_ETHPRIME         "eTSEC1"
 669
 670 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 671
 672 /* TBI PHY configuration for SGMII mode */
 673 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 674                 TBICR_PHY_RESET \
 675                 | TBICR_ANEG_ENABLE \
 676                 | TBICR_FULL_DUPLEX \
 677                 | TBICR_SPEED1_SET \
 678                 )
 679
 680 #endif  /* CONFIG_TSEC_ENET */
 681
 682 /* SATA */
 683 #define CONFIG_FSL_SATA
 684 #define CONFIG_FSL_SATA_V2
 685 #define CONFIG_LIBATA
 686
 687 #ifdef CONFIG_FSL_SATA
 688 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 689 #define CONFIG_SATA1
 690 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 691 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 692 #define CONFIG_SATA2
 693 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 694 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 695
 696 #define CONFIG_CMD_SATA
 697 #define CONFIG_LBA48
 698 #endif /* #ifdef CONFIG_FSL_SATA  */
 699
 700 #define CONFIG_MMC
 701 #ifdef CONFIG_MMC
 702 #define CONFIG_DOS_PARTITION
 703 #define CONFIG_FSL_ESDHC
 704 #define CONFIG_GENERIC_MMC
 705 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 706 #endif
 707
 708 #define CONFIG_HAS_FSL_DR_USB
 709
 710 #if defined(CONFIG_HAS_FSL_DR_USB)
 711 #define CONFIG_USB_EHCI
 712
 713 #ifdef CONFIG_USB_EHCI
 714 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 715 #define CONFIG_USB_EHCI_FSL
 716 #endif
 717 #endif
 718
 719 /*
 720  * Environment
 721  */
 722 #if defined(CONFIG_SDCARD)
 723 #define CONFIG_ENV_IS_IN_MMC
 724 #define CONFIG_FSL_FIXED_MMC_LOCATION
 725 #define CONFIG_SYS_MMC_ENV_DEV          0
 726 #define CONFIG_ENV_SIZE                 0x2000
 727 #elif defined(CONFIG_SPIFLASH)
 728 #define CONFIG_ENV_IS_IN_SPI_FLASH
 729 #define CONFIG_ENV_SPI_BUS      0
 730 #define CONFIG_ENV_SPI_CS       0
 731 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 732 #define CONFIG_ENV_SPI_MODE     0
 733 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 734 #define CONFIG_ENV_SECT_SIZE    0x10000
 735 #define CONFIG_ENV_SIZE         0x2000
 736 #elif defined(CONFIG_NAND)
 737 #define CONFIG_ENV_IS_IN_NAND
 738 #ifdef CONFIG_TPL_BUILD
 739 #define CONFIG_ENV_SIZE         0x2000
 740 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 741 #else
 742 #if defined(CONFIG_P1010RDB_PA)
 743 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 744 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 745 #elif defined(CONFIG_P1010RDB_PB)
 746 #define CONFIG_ENV_SIZE         (16 * 1024)
 747 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 748 #endif
 749 #endif
 750 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 751 #elif defined(CONFIG_SYS_RAMBOOT)
 752 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
 753 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 754 #define CONFIG_ENV_SIZE                 0x2000
 755 #else
 756 #define CONFIG_ENV_IS_IN_FLASH
 757 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 758 #define CONFIG_ENV_SIZE         0x2000
 759 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 760 #endif
 761
 762 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 763 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 764
 765 /*
 766  * Command line configuration.
 767  */
 768 #define CONFIG_CMD_DATE
 769 #define CONFIG_CMD_ERRATA
 770 #define CONFIG_CMD_IRQ
 771 #define CONFIG_CMD_REGINFO
 772
 773 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 774
 775 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 776                  || defined(CONFIG_FSL_SATA)
 777 #define CONFIG_DOS_PARTITION
 778 #endif
 779
 780 /* Hash command with SHA acceleration supported in hardware */
 781 #ifdef CONFIG_FSL_CAAM
 782 #define CONFIG_CMD_HASH
 783 #define CONFIG_SHA_HW_ACCEL
 784 #endif
 785
 786 /*
 787  * Miscellaneous configurable options
 788  */
 789 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 790 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 791 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 792 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 793
 794 #if defined(CONFIG_CMD_KGDB)
 795 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 796 #else
 797 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 798 #endif
 799 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 800                                                 /* Print Buffer Size */
 801 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 802 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 803
 804 /*
 805  * For booting Linux, the board info and command line data
 806  * have to be in the first 64 MB of memory, since this is
 807  * the maximum mapped by the Linux kernel during initialization.
 808  */
 809 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 810 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 811
 812 #if defined(CONFIG_CMD_KGDB)
 813 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 814 #endif
 815
 816 /*
 817  * Environment Configuration
 818  */
 819
 820 #if defined(CONFIG_TSEC_ENET)
 821 #define CONFIG_HAS_ETH0
 822 #define CONFIG_HAS_ETH1
 823 #define CONFIG_HAS_ETH2
 824 #endif
 825
 826 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 827 #define CONFIG_BOOTFILE         "uImage"
 828 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 829
 830 /* default location for tftp and bootm */
 831 #define CONFIG_LOADADDR         1000000
 832
 833 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 834
 835 #define CONFIG_BAUDRATE         115200
 836
 837 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 838         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 839         "netdev=eth0\0"                                         \
 840         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 841         "loadaddr=1000000\0"                    \
 842         "consoledev=ttyS0\0"                            \
 843         "ramdiskaddr=2000000\0"                 \
 844         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 845         "fdtaddr=1e00000\0"                             \
 846         "fdtfile=p1010rdb.dtb\0"                \
 847         "bdev=sda1\0"   \
 848         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 849         "othbootargs=ramdisk_size=600000\0" \
 850         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 851         "console=$consoledev,$baudrate $othbootargs; "  \
 852         "usb start;"                    \
 853         "fatload usb 0:2 $loadaddr $bootfile;"          \
 854         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 855         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 856         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 857         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 858         "console=$consoledev,$baudrate $othbootargs; "  \
 859         "usb start;"                    \
 860         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 861         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 862         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 863         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 864         CONFIG_BOOTMODE
 865
 866 #if defined(CONFIG_P1010RDB_PA)
 867 #define CONFIG_BOOTMODE \
 868         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 869         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 870         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 871         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 872         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 873         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 874
 875 #elif defined(CONFIG_P1010RDB_PB)
 876 #define CONFIG_BOOTMODE \
 877         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 878         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 879         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 880         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 881         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 882         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 883         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 884         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 885         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 886         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 887 #endif
 888
 889 #define CONFIG_RAMBOOTCOMMAND           \
 890         "setenv bootargs root=/dev/ram rw "     \
 891         "console=$consoledev,$baudrate $othbootargs; "  \
 892         "tftp $ramdiskaddr $ramdiskfile;"       \
 893         "tftp $loadaddr $bootfile;"             \
 894         "tftp $fdtaddr $fdtfile;"               \
 895         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 896
 897 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 898
 899 #include <asm/fsl_secure_boot.h>
 900
 901 #endif  /* __CONFIG_H */