1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SPL_FLUSH_IMAGE
20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
21 #define CONFIG_SPL_PAD_TO 0x18000
22 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
23 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
24 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
25 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
26 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
28 #ifdef CONFIG_SPL_BUILD
29 #define CONFIG_SPL_COMMON_INIT_DDR
33 #ifdef CONFIG_SPIFLASH
34 #ifdef CONFIG_NXP_ESBC
35 #define CONFIG_RAMBOOT_SPIFLASH
36 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
38 #define CONFIG_SPL_SPI_FLASH_MINIMAL
39 #define CONFIG_SPL_FLUSH_IMAGE
40 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
41 #define CONFIG_SPL_PAD_TO 0x18000
42 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SPL_COMMON_INIT_DDR
54 #ifdef CONFIG_MTD_RAW_NAND
55 #ifdef CONFIG_NXP_ESBC
56 #define CONFIG_SPL_INIT_MINIMAL
57 #define CONFIG_SPL_FLUSH_IMAGE
58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
60 #define CONFIG_SPL_MAX_SIZE 8192
61 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
62 #define CONFIG_SPL_RELOC_STACK 0x00100000
63 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
64 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
65 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
66 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
68 #ifdef CONFIG_TPL_BUILD
69 #define CONFIG_SPL_FLUSH_IMAGE
70 #define CONFIG_SPL_NAND_INIT
71 #define CONFIG_SPL_COMMON_INIT_DDR
72 #define CONFIG_SPL_MAX_SIZE (128 << 10)
73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
74 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
75 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
76 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
77 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
78 #elif defined(CONFIG_SPL_BUILD)
79 #define CONFIG_SPL_INIT_MINIMAL
80 #define CONFIG_SPL_NAND_MINIMAL
81 #define CONFIG_SPL_FLUSH_IMAGE
82 #define CONFIG_SPL_MAX_SIZE 8192
83 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
84 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
85 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
86 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
88 #define CONFIG_SPL_PAD_TO 0x20000
89 #define CONFIG_TPL_PAD_TO 0x20000
90 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
94 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
95 #define CONFIG_RAMBOOT_NAND
96 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
99 #ifndef CONFIG_RESET_VECTOR_ADDRESS
100 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
103 #ifdef CONFIG_TPL_BUILD
104 #define CONFIG_SYS_MONITOR_BASE 0xD0001000
105 #elif defined(CONFIG_SPL_BUILD)
106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
111 /* High Level Configuration Options */
113 #if defined(CONFIG_PCI)
114 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
115 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
119 * Memory space is mapped 1-1, but I/O space must start from 0.
121 /* controller 1, Slot 1, tgtid 1, Base address a000 */
122 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
123 #ifdef CONFIG_PHYS_64BIT
124 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
126 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
128 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
129 #ifdef CONFIG_PHYS_64BIT
130 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
132 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
135 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
136 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
137 #ifdef CONFIG_PHYS_64BIT
138 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
140 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
142 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
143 #ifdef CONFIG_PHYS_64BIT
144 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
146 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
149 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
152 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
154 #define CONFIG_HWCONFIG
156 * These can be toggled for performance analysis, otherwise use default.
158 #define CONFIG_L2_CACHE /* toggle L2 cache */
159 #define CONFIG_BTB /* toggle branch predition */
162 #define CONFIG_ENABLE_36BIT_PHYS
165 #define CONFIG_SYS_DDR_RAW_TIMING
166 #define CONFIG_SYS_SPD_BUS_NUM 1
167 #define SPD_EEPROM_ADDRESS 0x52
169 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
172 extern unsigned long get_sdram_size(void);
174 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
175 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
176 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
178 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
179 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
181 /* DDR3 Controller Settings */
182 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
183 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
184 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
185 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
186 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
187 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
188 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
189 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
190 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
191 #define CONFIG_SYS_DDR_RCW_1 0x00000000
192 #define CONFIG_SYS_DDR_RCW_2 0x00000000
193 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
194 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
195 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
196 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
198 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
199 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
200 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
201 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
202 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
203 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
204 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
205 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
206 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
208 /* settings for DDR3 at 667MT/s */
209 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
210 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
211 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
212 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
213 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
214 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
215 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
216 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
217 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
219 #define CONFIG_SYS_CCSRBAR 0xffe00000
220 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
222 /* Don't relocate CCSRBAR while in NAND_SPL */
223 #ifdef CONFIG_SPL_BUILD
224 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
230 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
231 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
232 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
234 * Localbus non-cacheable
235 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
236 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
237 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
238 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
244 /* NOR Flash on IFC */
246 #define CONFIG_SYS_FLASH_BASE 0xee000000
247 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
249 #ifdef CONFIG_PHYS_64BIT
250 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
252 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
255 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
256 CSPR_PORT_SIZE_16 | \
259 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
260 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
261 /* NOR Flash Timing Params */
262 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
263 FTIM0_NOR_TEADC(0x5) | \
265 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
266 FTIM1_NOR_TRAD_NOR(0x0f)
267 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
268 FTIM2_NOR_TCH(0x4) | \
270 #define CONFIG_SYS_NOR_FTIM3 0x0
272 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
273 #define CONFIG_SYS_FLASH_QUIET_TEST
274 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
275 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
277 #undef CONFIG_SYS_FLASH_CHECKSUM
278 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
279 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
281 /* CFI for NOR Flash */
282 #define CONFIG_SYS_FLASH_EMPTY_INFO
284 /* NAND Flash on IFC */
285 #define CONFIG_SYS_NAND_BASE 0xff800000
286 #ifdef CONFIG_PHYS_64BIT
287 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
289 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
292 #define CONFIG_MTD_PARTITION
294 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
298 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
300 #if defined(CONFIG_TARGET_P1010RDB_PA)
301 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
302 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
303 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
304 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
305 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
306 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
307 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
309 #elif defined(CONFIG_TARGET_P1010RDB_PB)
310 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
311 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
312 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
313 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
314 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
315 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
316 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
319 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
320 #define CONFIG_SYS_MAX_NAND_DEVICE 1
322 #if defined(CONFIG_TARGET_P1010RDB_PA)
323 /* NAND Flash Timing Params */
324 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
325 FTIM0_NAND_TWP(0x0C) | \
326 FTIM0_NAND_TWCHT(0x04) | \
328 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
329 FTIM1_NAND_TWBE(0x1d) | \
330 FTIM1_NAND_TRR(0x07) | \
332 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
333 FTIM2_NAND_TREH(0x05) | \
334 FTIM2_NAND_TWHRE(0x0f)
335 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
337 #elif defined(CONFIG_TARGET_P1010RDB_PB)
338 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
339 /* ONFI NAND Flash mode0 Timing Params */
340 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
341 FTIM0_NAND_TWP(0x18) | \
342 FTIM0_NAND_TWCHT(0x07) | \
343 FTIM0_NAND_TWH(0x0a))
344 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
345 FTIM1_NAND_TWBE(0x39) | \
346 FTIM1_NAND_TRR(0x0e) | \
347 FTIM1_NAND_TRP(0x18))
348 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
349 FTIM2_NAND_TREH(0x0a) | \
350 FTIM2_NAND_TWHRE(0x1e))
351 #define CONFIG_SYS_NAND_FTIM3 0x0
354 #define CONFIG_SYS_NAND_DDR_LAW 11
356 /* Set up IFC registers for boot location NOR/NAND */
357 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
365 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
366 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
367 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
368 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
369 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
370 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
371 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
373 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
374 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
375 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
376 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
377 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
378 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
379 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
380 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
381 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
382 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
383 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
384 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
385 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
386 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
390 #define CONFIG_SYS_CPLD_BASE 0xffb00000
392 #ifdef CONFIG_PHYS_64BIT
393 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
395 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
398 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
402 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
403 #define CONFIG_SYS_CSOR3 0x0
404 /* CPLD Timing parameters for IFC CS3 */
405 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
406 FTIM0_GPCM_TEADC(0x0e) | \
407 FTIM0_GPCM_TEAHC(0x0e))
408 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
409 FTIM1_GPCM_TRAD(0x1f))
410 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
411 FTIM2_GPCM_TCH(0x8) | \
412 FTIM2_GPCM_TWP(0x1f))
413 #define CONFIG_SYS_CS3_FTIM3 0x0
415 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
416 defined(CONFIG_RAMBOOT_NAND)
417 #define CONFIG_SYS_RAMBOOT
419 #undef CONFIG_SYS_RAMBOOT
422 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
423 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
424 #define CONFIG_A003399_NOR_WORKAROUND
428 #define CONFIG_SYS_INIT_RAM_LOCK
429 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
430 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
432 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
433 - GENERATED_GBL_DATA_SIZE)
434 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
436 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
439 * Config the L2 Cache as L2 SRAM
441 #if defined(CONFIG_SPL_BUILD)
442 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
443 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
444 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
445 #define CONFIG_SYS_L2_SIZE (256 << 10)
446 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
447 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
448 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
449 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
450 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
451 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
452 #elif defined(CONFIG_MTD_RAW_NAND)
453 #ifdef CONFIG_TPL_BUILD
454 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
455 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
456 #define CONFIG_SYS_L2_SIZE (256 << 10)
457 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
458 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
459 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
460 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
461 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
462 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
464 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
465 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
466 #define CONFIG_SYS_L2_SIZE (256 << 10)
467 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
468 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
469 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
475 #undef CONFIG_SERIAL_SOFTWARE_FIFO
476 #define CONFIG_SYS_NS16550_SERIAL
477 #define CONFIG_SYS_NS16550_REG_SIZE 1
478 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
479 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
480 #define CONFIG_NS16550_MIN_FUNCTIONS
483 #define CONFIG_SYS_BAUDRATE_TABLE \
484 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
486 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
487 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
490 #define I2C_PCA9557_ADDR1 0x18
491 #define I2C_PCA9557_ADDR2 0x19
492 #define I2C_PCA9557_BUS_NUM 0
495 #if defined(CONFIG_TARGET_P1010RDB_PB)
496 #ifdef CONFIG_ID_EEPROM
497 #define CONFIG_SYS_I2C_EEPROM_NXID
499 #define CONFIG_SYS_EEPROM_BUS_NUM 0
500 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
502 /* enable read and write access to EEPROM */
505 #define CONFIG_RTC_PT7C4338
506 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
509 * SPI interface will not be available in case of NAND boot SPI CS0 will be
512 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
513 /* eSPI - Enhanced SPI */
516 #if defined(CONFIG_TSEC_ENET)
517 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
518 #define CONFIG_TSEC1 1
519 #define CONFIG_TSEC1_NAME "eTSEC1"
520 #define CONFIG_TSEC2 1
521 #define CONFIG_TSEC2_NAME "eTSEC2"
522 #define CONFIG_TSEC3 1
523 #define CONFIG_TSEC3_NAME "eTSEC3"
525 #define TSEC1_PHY_ADDR 1
526 #define TSEC2_PHY_ADDR 0
527 #define TSEC3_PHY_ADDR 2
529 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
530 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
531 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
533 #define TSEC1_PHYIDX 0
534 #define TSEC2_PHYIDX 0
535 #define TSEC3_PHYIDX 0
537 #define CONFIG_ETHPRIME "eTSEC1"
539 /* TBI PHY configuration for SGMII mode */
540 #define CONFIG_TSEC_TBICR_SETTINGS ( \
542 | TBICR_ANEG_ENABLE \
543 | TBICR_FULL_DUPLEX \
547 #endif /* CONFIG_TSEC_ENET */
550 #define CONFIG_FSL_SATA_V2
552 #ifdef CONFIG_FSL_SATA
553 #define CONFIG_SYS_SATA_MAX_DEVICE 2
555 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
556 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
558 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
559 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
562 #endif /* #ifdef CONFIG_FSL_SATA */
565 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
568 #define CONFIG_HAS_FSL_DR_USB
570 #if defined(CONFIG_HAS_FSL_DR_USB)
571 #ifdef CONFIG_USB_EHCI_HCD
572 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
579 #if defined(CONFIG_SDCARD)
580 #define CONFIG_FSL_FIXED_MMC_LOCATION
581 #elif defined(CONFIG_MTD_RAW_NAND)
582 #ifdef CONFIG_TPL_BUILD
583 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
585 #if defined(CONFIG_TARGET_P1010RDB_PA)
586 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
587 #elif defined(CONFIG_TARGET_P1010RDB_PB)
588 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
593 #define CONFIG_LOADS_ECHO /* echo on for serial download */
594 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
596 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
597 || defined(CONFIG_FSL_SATA)
601 * Miscellaneous configurable options
605 * For booting Linux, the board info and command line data
606 * have to be in the first 64 MB of memory, since this is
607 * the maximum mapped by the Linux kernel during initialization.
609 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
610 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
613 * Environment Configuration
616 #if defined(CONFIG_TSEC_ENET)
617 #define CONFIG_HAS_ETH0
618 #define CONFIG_HAS_ETH1
619 #define CONFIG_HAS_ETH2
622 #define CONFIG_ROOTPATH "/opt/nfsroot"
623 #define CONFIG_BOOTFILE "uImage"
624 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
626 #define CONFIG_EXTRA_ENV_SETTINGS \
627 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
629 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
630 "loadaddr=1000000\0" \
631 "consoledev=ttyS0\0" \
632 "ramdiskaddr=2000000\0" \
633 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
634 "fdtaddr=1e00000\0" \
635 "fdtfile=p1010rdb.dtb\0" \
637 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
638 "othbootargs=ramdisk_size=600000\0" \
639 "usbfatboot=setenv bootargs root=/dev/ram rw " \
640 "console=$consoledev,$baudrate $othbootargs; " \
642 "fatload usb 0:2 $loadaddr $bootfile;" \
643 "fatload usb 0:2 $fdtaddr $fdtfile;" \
644 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
645 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
646 "usbext2boot=setenv bootargs root=/dev/ram rw " \
647 "console=$consoledev,$baudrate $othbootargs; " \
649 "ext2load usb 0:4 $loadaddr $bootfile;" \
650 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
651 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
652 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
655 #if defined(CONFIG_TARGET_P1010RDB_PA)
656 #define CONFIG_BOOTMODE \
657 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
658 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
659 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
660 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
661 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
662 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
664 #elif defined(CONFIG_TARGET_P1010RDB_PB)
665 #define CONFIG_BOOTMODE \
666 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
667 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
668 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
669 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
670 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
671 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
672 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
673 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
674 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
675 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
678 #include <asm/fsl_secure_boot.h>
680 #endif /* __CONFIG_H */