include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <asm/config_mpc85xx.h>
  15 #define CONFIG_NAND_FSL_IFC
  16
  17 #ifdef CONFIG_SDCARD
  18 #define CONFIG_SPL_FLUSH_IMAGE
  19 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  20 #define CONFIG_SPL_PAD_TO               0x18000
  21 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  22 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  23 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  24 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  25 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  27 #ifdef CONFIG_SPL_BUILD
  28 #define CONFIG_SPL_COMMON_INIT_DDR
  29 #endif
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #ifdef CONFIG_NXP_ESBC
  34 #define CONFIG_RAMBOOT_SPIFLASH
  35 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  36 #else
  37 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  38 #define CONFIG_SPL_FLUSH_IMAGE
  39 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  40 #define CONFIG_SPL_PAD_TO                       0x18000
  41 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  47 #ifdef CONFIG_SPL_BUILD
  48 #define CONFIG_SPL_COMMON_INIT_DDR
  49 #endif
  50 #endif
  51 #endif
  52
  53 #ifdef CONFIG_MTD_RAW_NAND
  54 #ifdef CONFIG_NXP_ESBC
  55 #define CONFIG_SPL_INIT_MINIMAL
  56 #define CONFIG_SPL_FLUSH_IMAGE
  57 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  58
  59 #define CONFIG_SPL_MAX_SIZE             8192
  60 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  61 #define CONFIG_SPL_RELOC_STACK          0x00100000
  62 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  63 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  64 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  65 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  66 #else
  67 #ifdef CONFIG_TPL_BUILD
  68 #define CONFIG_SPL_FLUSH_IMAGE
  69 #define CONFIG_SPL_NAND_INIT
  70 #define CONFIG_SPL_COMMON_INIT_DDR
  71 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  72 #define CONFIG_TPL_TEXT_BASE            0xD0001000
  73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  74 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  75 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  76 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  77 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  78 #elif defined(CONFIG_SPL_BUILD)
  79 #define CONFIG_SPL_INIT_MINIMAL
  80 #define CONFIG_SPL_NAND_MINIMAL
  81 #define CONFIG_SPL_FLUSH_IMAGE
  82 #define CONFIG_SPL_MAX_SIZE             8192
  83 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  84 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  85 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  86 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  87 #endif
  88 #define CONFIG_SPL_PAD_TO       0x20000
  89 #define CONFIG_TPL_PAD_TO       0x20000
  90 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  91 #endif
  92 #endif
  93
  94 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  95 #define CONFIG_RAMBOOT_NAND
  96 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  97 #endif
  98
  99 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 100 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 101 #endif
 102
 103 #ifdef CONFIG_TPL_BUILD
 104 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
 105 #elif defined(CONFIG_SPL_BUILD)
 106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 107 #else
 108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 109 #endif
 110
 111 /* High Level Configuration Options */
 112 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 113
 114 #if defined(CONFIG_PCI)
 115 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 116 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 117 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 118
 119 /*
 120  * PCI Windows
 121  * Memory space is mapped 1-1, but I/O space must start from 0.
 122  */
 123 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 124 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 125 #ifdef CONFIG_PHYS_64BIT
 126 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 127 #else
 128 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 129 #endif
 130 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 131 #ifdef CONFIG_PHYS_64BIT
 132 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 133 #else
 134 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 135 #endif
 136
 137 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 138 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 139 #ifdef CONFIG_PHYS_64BIT
 140 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 141 #else
 142 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 143 #endif
 144 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 145 #ifdef CONFIG_PHYS_64BIT
 146 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 147 #else
 148 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 149 #endif
 150
 151 #if !defined(CONFIG_DM_PCI)
 152 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 153 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 154 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
 155 #ifdef CONFIG_PHYS_64BIT
 156 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 157 #else
 158 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 159 #endif
 160 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 161 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 162 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 163
 164 #if defined(CONFIG_TARGET_P1010RDB_PA)
 165 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
 166 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 167 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
 168 #endif
 169 #ifdef CONFIG_PHYS_64BIT
 170 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 171 #else
 172 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 173 #endif
 174 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 175 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 176 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 177 #endif
 178
 179 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 180 #endif
 181
 182 #define CONFIG_ENV_OVERWRITE
 183
 184 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 185 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 186
 187 #define CONFIG_HWCONFIG
 188 /*
 189  * These can be toggled for performance analysis, otherwise use default.
 190  */
 191 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 192 #define CONFIG_BTB                      /* toggle branch predition */
 193
 194
 195 #define CONFIG_ENABLE_36BIT_PHYS
 196
 197 #ifdef CONFIG_PHYS_64BIT
 198 #define CONFIG_ADDR_MAP                 1
 199 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 200 #endif
 201
 202 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 203 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 204
 205 /* DDR Setup */
 206 #define CONFIG_SYS_DDR_RAW_TIMING
 207 #define CONFIG_DDR_SPD
 208 #define CONFIG_SYS_SPD_BUS_NUM          1
 209 #define SPD_EEPROM_ADDRESS              0x52
 210
 211 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 212
 213 #ifndef __ASSEMBLY__
 214 extern unsigned long get_sdram_size(void);
 215 #endif
 216 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 217 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 218 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 219
 220 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 221 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 222
 223 /* DDR3 Controller Settings */
 224 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 225 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 226 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 227 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 228 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 229 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 230 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 231 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 232 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 233 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 234 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 235 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 236 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 237 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 238 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 239
 240 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 241 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 242 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 243 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 244 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 245 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 246 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 247 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 248 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 249
 250 /* settings for DDR3 at 667MT/s */
 251 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 252 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 253 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 254 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 255 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 256 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 257 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 258 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 259 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 260
 261 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 262 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 263
 264 /* Don't relocate CCSRBAR while in NAND_SPL */
 265 #ifdef CONFIG_SPL_BUILD
 266 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 267 #endif
 268
 269 /*
 270  * Memory map
 271  *
 272  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 273  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 274  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 275  *
 276  * Localbus non-cacheable
 277  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 278  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 279  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 280  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 281  */
 282
 283 /*
 284  * IFC Definitions
 285  */
 286 /* NOR Flash on IFC */
 287
 288 #define CONFIG_SYS_FLASH_BASE           0xee000000
 289 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 290
 291 #ifdef CONFIG_PHYS_64BIT
 292 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 293 #else
 294 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 295 #endif
 296
 297 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 298                                 CSPR_PORT_SIZE_16 | \
 299                                 CSPR_MSEL_NOR | \
 300                                 CSPR_V)
 301 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 302 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 303 /* NOR Flash Timing Params */
 304 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 305                                 FTIM0_NOR_TEADC(0x5) | \
 306                                 FTIM0_NOR_TEAHC(0x5)
 307 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 308                                 FTIM1_NOR_TRAD_NOR(0x0f)
 309 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 310                                 FTIM2_NOR_TCH(0x4) | \
 311                                 FTIM2_NOR_TWP(0x1c)
 312 #define CONFIG_SYS_NOR_FTIM3    0x0
 313
 314 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 315 #define CONFIG_SYS_FLASH_QUIET_TEST
 316 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 317 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 318
 319 #undef CONFIG_SYS_FLASH_CHECKSUM
 320 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 321 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 322
 323 /* CFI for NOR Flash */
 324 #define CONFIG_SYS_FLASH_EMPTY_INFO
 325
 326 /* NAND Flash on IFC */
 327 #define CONFIG_SYS_NAND_BASE            0xff800000
 328 #ifdef CONFIG_PHYS_64BIT
 329 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 330 #else
 331 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 332 #endif
 333
 334 #define CONFIG_MTD_PARTITION
 335
 336 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 337                                 | CSPR_PORT_SIZE_8      \
 338                                 | CSPR_MSEL_NAND        \
 339                                 | CSPR_V)
 340 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 341
 342 #if defined(CONFIG_TARGET_P1010RDB_PA)
 343 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 344                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 345                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 346                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 347                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 348                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 349                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 350 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 351
 352 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 353 #define CONFIG_SYS_NAND_ONFI_DETECTION
 354 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 355                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 356                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 357                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 358                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 359                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 360                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 361 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 362 #endif
 363
 364 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 365 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 366
 367 #if defined(CONFIG_TARGET_P1010RDB_PA)
 368 /* NAND Flash Timing Params */
 369 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 370                                         FTIM0_NAND_TWP(0x0C)   | \
 371                                         FTIM0_NAND_TWCHT(0x04) | \
 372                                         FTIM0_NAND_TWH(0x05)
 373 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 374                                         FTIM1_NAND_TWBE(0x1d)  | \
 375                                         FTIM1_NAND_TRR(0x07)   | \
 376                                         FTIM1_NAND_TRP(0x0c)
 377 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 378                                         FTIM2_NAND_TREH(0x05) | \
 379                                         FTIM2_NAND_TWHRE(0x0f)
 380 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 381
 382 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 383 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 384 /* ONFI NAND Flash mode0 Timing Params */
 385 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 386                                         FTIM0_NAND_TWP(0x18)   | \
 387                                         FTIM0_NAND_TWCHT(0x07) | \
 388                                         FTIM0_NAND_TWH(0x0a))
 389 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 390                                         FTIM1_NAND_TWBE(0x39)  | \
 391                                         FTIM1_NAND_TRR(0x0e)   | \
 392                                         FTIM1_NAND_TRP(0x18))
 393 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 394                                         FTIM2_NAND_TREH(0x0a)  | \
 395                                         FTIM2_NAND_TWHRE(0x1e))
 396 #define CONFIG_SYS_NAND_FTIM3   0x0
 397 #endif
 398
 399 #define CONFIG_SYS_NAND_DDR_LAW         11
 400
 401 /* Set up IFC registers for boot location NOR/NAND */
 402 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 403 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 404 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 405 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 406 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 407 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 408 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 409 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 410 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 411 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 412 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 413 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 414 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 415 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 416 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 417 #else
 418 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 419 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 420 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 421 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 422 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 423 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 424 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 425 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 426 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 427 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 428 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 429 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 430 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 431 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 432 #endif
 433
 434 /* CPLD on IFC */
 435 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 436
 437 #ifdef CONFIG_PHYS_64BIT
 438 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 439 #else
 440 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 441 #endif
 442
 443 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 444                                 | CSPR_PORT_SIZE_8 \
 445                                 | CSPR_MSEL_GPCM \
 446                                 | CSPR_V)
 447 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 448 #define CONFIG_SYS_CSOR3                0x0
 449 /* CPLD Timing parameters for IFC CS3 */
 450 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 451                                         FTIM0_GPCM_TEADC(0x0e) | \
 452                                         FTIM0_GPCM_TEAHC(0x0e))
 453 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 454                                         FTIM1_GPCM_TRAD(0x1f))
 455 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 456                                         FTIM2_GPCM_TCH(0x8) | \
 457                                         FTIM2_GPCM_TWP(0x1f))
 458 #define CONFIG_SYS_CS3_FTIM3            0x0
 459
 460 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 461         defined(CONFIG_RAMBOOT_NAND)
 462 #define CONFIG_SYS_RAMBOOT
 463 #else
 464 #undef CONFIG_SYS_RAMBOOT
 465 #endif
 466
 467 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 468 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 469 #define CONFIG_A003399_NOR_WORKAROUND
 470 #endif
 471 #endif
 472
 473 #define CONFIG_SYS_INIT_RAM_LOCK
 474 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 475 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 476
 477 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 478                                                 - GENERATED_GBL_DATA_SIZE)
 479 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 480
 481 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 482 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 483
 484 /*
 485  * Config the L2 Cache as L2 SRAM
 486  */
 487 #if defined(CONFIG_SPL_BUILD)
 488 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 489 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 490 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 491 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 492 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 493 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 494 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 495 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 496 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 497 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 498 #elif defined(CONFIG_MTD_RAW_NAND)
 499 #ifdef CONFIG_TPL_BUILD
 500 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 501 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 502 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 503 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 504 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 505 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 506 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 507 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 508 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 509 #else
 510 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 511 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 512 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 513 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 514 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 515 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 516 #endif
 517 #endif
 518 #endif
 519
 520 /* Serial Port */
 521 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 522 #define CONFIG_SYS_NS16550_SERIAL
 523 #define CONFIG_SYS_NS16550_REG_SIZE     1
 524 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 525 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 526 #define CONFIG_NS16550_MIN_FUNCTIONS
 527 #endif
 528
 529 #define CONFIG_SYS_BAUDRATE_TABLE       \
 530         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 531
 532 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 533 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 534
 535 /* I2C */
 536 #ifndef CONFIG_DM_I2C
 537 #define CONFIG_SYS_I2C
 538 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 539 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 540 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 541 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 542 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 543 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 544 #else
 545 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 546 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 547 #endif
 548 #define I2C_PCA9557_ADDR1               0x18
 549 #define I2C_PCA9557_ADDR2               0x19
 550 #define I2C_PCA9557_BUS_NUM             0
 551 #define CONFIG_SYS_I2C_FSL
 552
 553 /* I2C EEPROM */
 554 #if defined(CONFIG_TARGET_P1010RDB_PB)
 555 #define CONFIG_ID_EEPROM
 556 #ifdef CONFIG_ID_EEPROM
 557 #define CONFIG_SYS_I2C_EEPROM_NXID
 558 #endif
 559 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 560 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 561 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 562 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 563 #endif
 564 /* enable read and write access to EEPROM */
 565 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 566 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 567 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 568
 569 /* RTC */
 570 #define CONFIG_RTC_PT7C4338
 571 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 572
 573 /*
 574  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 575  * used for SLIC
 576  */
 577 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 578 /* eSPI - Enhanced SPI */
 579 #endif
 580
 581 #if defined(CONFIG_TSEC_ENET)
 582 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 583 #define CONFIG_TSEC1    1
 584 #define CONFIG_TSEC1_NAME       "eTSEC1"
 585 #define CONFIG_TSEC2    1
 586 #define CONFIG_TSEC2_NAME       "eTSEC2"
 587 #define CONFIG_TSEC3    1
 588 #define CONFIG_TSEC3_NAME       "eTSEC3"
 589
 590 #define TSEC1_PHY_ADDR          1
 591 #define TSEC2_PHY_ADDR          0
 592 #define TSEC3_PHY_ADDR          2
 593
 594 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 595 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 596 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 597
 598 #define TSEC1_PHYIDX            0
 599 #define TSEC2_PHYIDX            0
 600 #define TSEC3_PHYIDX            0
 601
 602 #define CONFIG_ETHPRIME         "eTSEC1"
 603
 604 /* TBI PHY configuration for SGMII mode */
 605 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 606                 TBICR_PHY_RESET \
 607                 | TBICR_ANEG_ENABLE \
 608                 | TBICR_FULL_DUPLEX \
 609                 | TBICR_SPEED1_SET \
 610                 )
 611
 612 #endif  /* CONFIG_TSEC_ENET */
 613
 614 /* SATA */
 615 #define CONFIG_FSL_SATA_V2
 616
 617 #ifdef CONFIG_FSL_SATA
 618 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 619 #define CONFIG_SATA1
 620 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 621 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 622 #define CONFIG_SATA2
 623 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 624 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 625
 626 #define CONFIG_LBA48
 627 #endif /* #ifdef CONFIG_FSL_SATA  */
 628
 629 #ifdef CONFIG_MMC
 630 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 631 #endif
 632
 633 #define CONFIG_HAS_FSL_DR_USB
 634
 635 #if defined(CONFIG_HAS_FSL_DR_USB)
 636 #ifdef CONFIG_USB_EHCI_HCD
 637 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 638 #define CONFIG_USB_EHCI_FSL
 639 #endif
 640 #endif
 641
 642 /*
 643  * Environment
 644  */
 645 #if defined(CONFIG_SDCARD)
 646 #define CONFIG_FSL_FIXED_MMC_LOCATION
 647 #define CONFIG_SYS_MMC_ENV_DEV          0
 648 #elif defined(CONFIG_MTD_RAW_NAND)
 649 #ifdef CONFIG_TPL_BUILD
 650 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 651 #else
 652 #if defined(CONFIG_TARGET_P1010RDB_PA)
 653 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 654 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 655 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 656 #endif
 657 #endif
 658 #endif
 659
 660 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 661 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 662
 663 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 664
 665 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 666                  || defined(CONFIG_FSL_SATA)
 667 #endif
 668
 669 /*
 670  * Miscellaneous configurable options
 671  */
 672 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 673
 674 /*
 675  * For booting Linux, the board info and command line data
 676  * have to be in the first 64 MB of memory, since this is
 677  * the maximum mapped by the Linux kernel during initialization.
 678  */
 679 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 680 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 681
 682 #if defined(CONFIG_CMD_KGDB)
 683 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 684 #endif
 685
 686 /*
 687  * Environment Configuration
 688  */
 689
 690 #if defined(CONFIG_TSEC_ENET)
 691 #define CONFIG_HAS_ETH0
 692 #define CONFIG_HAS_ETH1
 693 #define CONFIG_HAS_ETH2
 694 #endif
 695
 696 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 697 #define CONFIG_BOOTFILE         "uImage"
 698 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 699
 700 /* default location for tftp and bootm */
 701 #define CONFIG_LOADADDR         1000000
 702
 703 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 704         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 705         "netdev=eth0\0"                                         \
 706         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 707         "loadaddr=1000000\0"                    \
 708         "consoledev=ttyS0\0"                            \
 709         "ramdiskaddr=2000000\0"                 \
 710         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 711         "fdtaddr=1e00000\0"                             \
 712         "fdtfile=p1010rdb.dtb\0"                \
 713         "bdev=sda1\0"   \
 714         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 715         "othbootargs=ramdisk_size=600000\0" \
 716         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 717         "console=$consoledev,$baudrate $othbootargs; "  \
 718         "usb start;"                    \
 719         "fatload usb 0:2 $loadaddr $bootfile;"          \
 720         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 721         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 722         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 723         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 724         "console=$consoledev,$baudrate $othbootargs; "  \
 725         "usb start;"                    \
 726         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 727         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 728         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 729         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 730         CONFIG_BOOTMODE
 731
 732 #if defined(CONFIG_TARGET_P1010RDB_PA)
 733 #define CONFIG_BOOTMODE \
 734         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 735         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 736         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 737         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 738         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 739         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 740
 741 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 742 #define CONFIG_BOOTMODE \
 743         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 744         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 745         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 746         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 747         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 748         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 749         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 750         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 751         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 752         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 753 #endif
 754
 755 #define CONFIG_RAMBOOTCOMMAND           \
 756         "setenv bootargs root=/dev/ram rw "     \
 757         "console=$consoledev,$baudrate $othbootargs; "  \
 758         "tftp $ramdiskaddr $ramdiskfile;"       \
 759         "tftp $loadaddr $bootfile;"             \
 760         "tftp $fdtaddr $fdtfile;"               \
 761         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 762
 763 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 764
 765 #include <asm/fsl_secure_boot.h>
 766
 767 #endif  /* __CONFIG_H */