1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
20 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
21 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
23 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
24 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
27 #ifdef CONFIG_SPIFLASH
28 #ifdef CONFIG_NXP_ESBC
29 #define CONFIG_RAMBOOT_SPIFLASH
30 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
41 #ifdef CONFIG_MTD_RAW_NAND
42 #ifdef CONFIG_NXP_ESBC
43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
46 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
49 #ifdef CONFIG_TPL_BUILD
50 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
52 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
53 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
54 #elif defined(CONFIG_SPL_BUILD)
55 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
56 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
57 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
59 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
60 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
67 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
68 #define CONFIG_RAMBOOT_NAND
69 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
72 #ifndef CONFIG_RESET_VECTOR_ADDRESS
73 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
76 /* High Level Configuration Options */
78 #if defined(CONFIG_PCI)
79 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
80 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
84 * Memory space is mapped 1-1, but I/O space must start from 0.
86 /* controller 1, Slot 1, tgtid 1, Base address a000 */
87 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
88 #ifdef CONFIG_PHYS_64BIT
89 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
91 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
93 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
94 #ifdef CONFIG_PHYS_64BIT
95 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
97 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
100 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
101 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
102 #ifdef CONFIG_PHYS_64BIT
103 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
105 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
107 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
108 #ifdef CONFIG_PHYS_64BIT
109 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
111 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
114 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
117 #define CONFIG_HWCONFIG
119 * These can be toggled for performance analysis, otherwise use default.
121 #define CONFIG_L2_CACHE /* toggle L2 cache */
124 #define CONFIG_ENABLE_36BIT_PHYS
127 #define CONFIG_SYS_DDR_RAW_TIMING
128 #define CONFIG_SYS_SPD_BUS_NUM 1
129 #define SPD_EEPROM_ADDRESS 0x52
131 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
134 extern unsigned long get_sdram_size(void);
136 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
137 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
138 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
140 /* DDR3 Controller Settings */
141 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
142 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
143 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
144 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
145 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
146 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
147 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
148 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
149 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
150 #define CONFIG_SYS_DDR_RCW_1 0x00000000
151 #define CONFIG_SYS_DDR_RCW_2 0x00000000
152 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
153 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
154 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
155 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
157 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
158 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
159 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
160 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
161 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
162 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
163 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
164 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
165 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
167 /* settings for DDR3 at 667MT/s */
168 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
169 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
170 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
171 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
172 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
173 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
174 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
175 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
176 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
178 #define CONFIG_SYS_CCSRBAR 0xffe00000
179 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
184 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
185 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
186 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
188 * Localbus non-cacheable
189 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
190 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
191 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
192 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
198 /* NOR Flash on IFC */
200 #define CONFIG_SYS_FLASH_BASE 0xee000000
201 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
203 #ifdef CONFIG_PHYS_64BIT
204 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
206 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
209 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
210 CSPR_PORT_SIZE_16 | \
213 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
214 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
215 /* NOR Flash Timing Params */
216 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
217 FTIM0_NOR_TEADC(0x5) | \
219 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
220 FTIM1_NOR_TRAD_NOR(0x0f)
221 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
222 FTIM2_NOR_TCH(0x4) | \
224 #define CONFIG_SYS_NOR_FTIM3 0x0
226 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
227 #define CONFIG_SYS_FLASH_QUIET_TEST
228 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
230 #undef CONFIG_SYS_FLASH_CHECKSUM
231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
234 /* CFI for NOR Flash */
235 #define CONFIG_SYS_FLASH_EMPTY_INFO
237 /* NAND Flash on IFC */
238 #define CONFIG_SYS_NAND_BASE 0xff800000
239 #ifdef CONFIG_PHYS_64BIT
240 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
242 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
245 #define CONFIG_MTD_PARTITION
247 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
251 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
253 #if defined(CONFIG_TARGET_P1010RDB_PA)
254 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
255 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
256 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
257 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
258 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
259 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
260 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
262 #elif defined(CONFIG_TARGET_P1010RDB_PB)
263 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
264 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
265 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
266 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
267 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
268 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
269 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
272 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
273 #define CONFIG_SYS_MAX_NAND_DEVICE 1
275 #if defined(CONFIG_TARGET_P1010RDB_PA)
276 /* NAND Flash Timing Params */
277 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
278 FTIM0_NAND_TWP(0x0C) | \
279 FTIM0_NAND_TWCHT(0x04) | \
281 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
282 FTIM1_NAND_TWBE(0x1d) | \
283 FTIM1_NAND_TRR(0x07) | \
285 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
286 FTIM2_NAND_TREH(0x05) | \
287 FTIM2_NAND_TWHRE(0x0f)
288 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
290 #elif defined(CONFIG_TARGET_P1010RDB_PB)
291 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
292 /* ONFI NAND Flash mode0 Timing Params */
293 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
294 FTIM0_NAND_TWP(0x18) | \
295 FTIM0_NAND_TWCHT(0x07) | \
296 FTIM0_NAND_TWH(0x0a))
297 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
298 FTIM1_NAND_TWBE(0x39) | \
299 FTIM1_NAND_TRR(0x0e) | \
300 FTIM1_NAND_TRP(0x18))
301 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
302 FTIM2_NAND_TREH(0x0a) | \
303 FTIM2_NAND_TWHRE(0x1e))
304 #define CONFIG_SYS_NAND_FTIM3 0x0
307 #define CONFIG_SYS_NAND_DDR_LAW 11
309 /* Set up IFC registers for boot location NOR/NAND */
310 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
311 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
312 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
313 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
314 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
315 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
316 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
317 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
318 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
319 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
320 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
321 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
322 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
323 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
324 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
326 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
327 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
328 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
329 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
330 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
331 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
332 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
343 #define CONFIG_SYS_CPLD_BASE 0xffb00000
345 #ifdef CONFIG_PHYS_64BIT
346 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
348 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
351 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
355 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
356 #define CONFIG_SYS_CSOR3 0x0
357 /* CPLD Timing parameters for IFC CS3 */
358 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
359 FTIM0_GPCM_TEADC(0x0e) | \
360 FTIM0_GPCM_TEAHC(0x0e))
361 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
362 FTIM1_GPCM_TRAD(0x1f))
363 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
364 FTIM2_GPCM_TCH(0x8) | \
365 FTIM2_GPCM_TWP(0x1f))
366 #define CONFIG_SYS_CS3_FTIM3 0x0
368 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
369 defined(CONFIG_RAMBOOT_NAND)
370 #define CONFIG_SYS_RAMBOOT
372 #undef CONFIG_SYS_RAMBOOT
375 #define CONFIG_SYS_INIT_RAM_LOCK
376 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
377 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
379 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
381 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
384 * Config the L2 Cache as L2 SRAM
386 #if defined(CONFIG_SPL_BUILD)
387 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
388 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
389 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
390 #define CONFIG_SYS_L2_SIZE (256 << 10)
391 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
392 #elif defined(CONFIG_MTD_RAW_NAND)
393 #ifdef CONFIG_TPL_BUILD
394 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
395 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
396 #define CONFIG_SYS_L2_SIZE (256 << 10)
397 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
399 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
400 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
401 #define CONFIG_SYS_L2_SIZE (256 << 10)
402 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
408 #undef CONFIG_SERIAL_SOFTWARE_FIFO
409 #define CONFIG_SYS_NS16550_SERIAL
410 #define CONFIG_SYS_NS16550_REG_SIZE 1
411 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
412 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
413 #define CONFIG_NS16550_MIN_FUNCTIONS
416 #define CONFIG_SYS_BAUDRATE_TABLE \
417 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
419 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
420 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
423 #define I2C_PCA9557_ADDR1 0x18
424 #define I2C_PCA9557_ADDR2 0x19
425 #define I2C_PCA9557_BUS_NUM 0
428 #if defined(CONFIG_TARGET_P1010RDB_PB)
429 #ifdef CONFIG_ID_EEPROM
430 #define CONFIG_SYS_I2C_EEPROM_NXID
432 #define CONFIG_SYS_EEPROM_BUS_NUM 0
433 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
435 /* enable read and write access to EEPROM */
438 #define CONFIG_RTC_PT7C4338
439 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
442 * SPI interface will not be available in case of NAND boot SPI CS0 will be
445 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
446 /* eSPI - Enhanced SPI */
449 #if defined(CONFIG_TSEC_ENET)
450 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
451 #define CONFIG_TSEC1 1
452 #define CONFIG_TSEC1_NAME "eTSEC1"
453 #define CONFIG_TSEC2 1
454 #define CONFIG_TSEC2_NAME "eTSEC2"
455 #define CONFIG_TSEC3 1
456 #define CONFIG_TSEC3_NAME "eTSEC3"
458 #define TSEC1_PHY_ADDR 1
459 #define TSEC2_PHY_ADDR 0
460 #define TSEC3_PHY_ADDR 2
462 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
463 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
464 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
466 #define TSEC1_PHYIDX 0
467 #define TSEC2_PHYIDX 0
468 #define TSEC3_PHYIDX 0
470 /* TBI PHY configuration for SGMII mode */
471 #define CONFIG_TSEC_TBICR_SETTINGS ( \
473 | TBICR_ANEG_ENABLE \
474 | TBICR_FULL_DUPLEX \
478 #endif /* CONFIG_TSEC_ENET */
481 #define CONFIG_FSL_SATA_V2
483 #ifdef CONFIG_FSL_SATA
485 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
486 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
488 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
489 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
492 #endif /* #ifdef CONFIG_FSL_SATA */
495 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
498 #define CONFIG_HAS_FSL_DR_USB
500 #if defined(CONFIG_HAS_FSL_DR_USB)
501 #ifdef CONFIG_USB_EHCI_HCD
502 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
509 #if defined(CONFIG_SDCARD)
510 #define CONFIG_FSL_FIXED_MMC_LOCATION
511 #elif defined(CONFIG_MTD_RAW_NAND)
512 #ifdef CONFIG_TPL_BUILD
513 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
515 #if defined(CONFIG_TARGET_P1010RDB_PA)
516 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
517 #elif defined(CONFIG_TARGET_P1010RDB_PB)
518 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
523 #define CONFIG_LOADS_ECHO /* echo on for serial download */
524 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
526 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
527 || defined(CONFIG_FSL_SATA)
531 * Miscellaneous configurable options
535 * For booting Linux, the board info and command line data
536 * have to be in the first 64 MB of memory, since this is
537 * the maximum mapped by the Linux kernel during initialization.
539 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
540 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
543 * Environment Configuration
546 #define CONFIG_ROOTPATH "/opt/nfsroot"
547 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
549 #define CONFIG_EXTRA_ENV_SETTINGS \
550 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
552 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
553 "loadaddr=1000000\0" \
554 "consoledev=ttyS0\0" \
555 "ramdiskaddr=2000000\0" \
556 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
557 "fdtaddr=1e00000\0" \
558 "fdtfile=p1010rdb.dtb\0" \
560 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
561 "othbootargs=ramdisk_size=600000\0" \
562 "usbfatboot=setenv bootargs root=/dev/ram rw " \
563 "console=$consoledev,$baudrate $othbootargs; " \
565 "fatload usb 0:2 $loadaddr $bootfile;" \
566 "fatload usb 0:2 $fdtaddr $fdtfile;" \
567 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
568 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
569 "usbext2boot=setenv bootargs root=/dev/ram rw " \
570 "console=$consoledev,$baudrate $othbootargs; " \
572 "ext2load usb 0:4 $loadaddr $bootfile;" \
573 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
574 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
575 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
578 #if defined(CONFIG_TARGET_P1010RDB_PA)
580 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
581 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
582 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
583 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
584 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
585 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
587 #elif defined(CONFIG_TARGET_P1010RDB_PB)
589 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
590 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
591 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
592 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
593 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
594 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
595 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
596 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
597 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
598 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
601 #include <asm/fsl_secure_boot.h>
603 #endif /* __CONFIG_H */