1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
20 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
23 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
26 #ifdef CONFIG_SPIFLASH
27 #ifdef CONFIG_NXP_ESBC
28 #define CONFIG_RAMBOOT_SPIFLASH
29 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
31 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
32 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
35 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
39 #ifdef CONFIG_MTD_RAW_NAND
40 #ifdef CONFIG_NXP_ESBC
41 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
42 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
45 #ifdef CONFIG_TPL_BUILD
46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
48 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
49 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
50 #elif defined(CONFIG_SPL_BUILD)
51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
52 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
53 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
55 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
62 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
63 #define CONFIG_RAMBOOT_NAND
64 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
67 #ifndef CONFIG_RESET_VECTOR_ADDRESS
68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
71 /* High Level Configuration Options */
73 #if defined(CONFIG_PCI)
74 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
75 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
79 * Memory space is mapped 1-1, but I/O space must start from 0.
81 /* controller 1, Slot 1, tgtid 1, Base address a000 */
82 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
83 #ifdef CONFIG_PHYS_64BIT
84 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
86 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
88 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
89 #ifdef CONFIG_PHYS_64BIT
90 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
92 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
95 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
96 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
97 #ifdef CONFIG_PHYS_64BIT
98 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
100 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
102 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
103 #ifdef CONFIG_PHYS_64BIT
104 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
106 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
109 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
112 #define CONFIG_HWCONFIG
114 * These can be toggled for performance analysis, otherwise use default.
116 #define CONFIG_L2_CACHE /* toggle L2 cache */
119 #define CONFIG_ENABLE_36BIT_PHYS
122 #define CONFIG_SYS_DDR_RAW_TIMING
123 #define CONFIG_SYS_SPD_BUS_NUM 1
124 #define SPD_EEPROM_ADDRESS 0x52
126 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
129 extern unsigned long get_sdram_size(void);
131 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
132 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
133 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
135 /* DDR3 Controller Settings */
136 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
137 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
138 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
139 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
140 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
141 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
142 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
143 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
144 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
145 #define CONFIG_SYS_DDR_RCW_1 0x00000000
146 #define CONFIG_SYS_DDR_RCW_2 0x00000000
147 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
148 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
149 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
150 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
152 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
153 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
154 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
155 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
156 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
157 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
158 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
159 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
160 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
162 /* settings for DDR3 at 667MT/s */
163 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
164 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
165 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
166 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
167 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
168 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
169 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
170 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
171 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
173 #define CONFIG_SYS_CCSRBAR 0xffe00000
174 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
179 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
180 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
181 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
183 * Localbus non-cacheable
184 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
185 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
186 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
187 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
193 /* NOR Flash on IFC */
195 #define CONFIG_SYS_FLASH_BASE 0xee000000
196 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
198 #ifdef CONFIG_PHYS_64BIT
199 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
201 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
205 CSPR_PORT_SIZE_16 | \
208 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
209 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
210 /* NOR Flash Timing Params */
211 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
212 FTIM0_NOR_TEADC(0x5) | \
214 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
215 FTIM1_NOR_TRAD_NOR(0x0f)
216 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
217 FTIM2_NOR_TCH(0x4) | \
219 #define CONFIG_SYS_NOR_FTIM3 0x0
221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
222 #define CONFIG_SYS_FLASH_QUIET_TEST
223 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
225 #undef CONFIG_SYS_FLASH_CHECKSUM
226 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
227 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
229 /* CFI for NOR Flash */
230 #define CONFIG_SYS_FLASH_EMPTY_INFO
232 /* NAND Flash on IFC */
233 #define CONFIG_SYS_NAND_BASE 0xff800000
234 #ifdef CONFIG_PHYS_64BIT
235 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
237 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
240 #define CONFIG_MTD_PARTITION
242 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
246 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
248 #if defined(CONFIG_TARGET_P1010RDB_PA)
249 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
250 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
251 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
252 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
253 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
254 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
255 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
257 #elif defined(CONFIG_TARGET_P1010RDB_PB)
258 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
259 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
260 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
261 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
262 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
263 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
264 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
267 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
268 #define CONFIG_SYS_MAX_NAND_DEVICE 1
270 #if defined(CONFIG_TARGET_P1010RDB_PA)
271 /* NAND Flash Timing Params */
272 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
273 FTIM0_NAND_TWP(0x0C) | \
274 FTIM0_NAND_TWCHT(0x04) | \
276 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
277 FTIM1_NAND_TWBE(0x1d) | \
278 FTIM1_NAND_TRR(0x07) | \
280 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
281 FTIM2_NAND_TREH(0x05) | \
282 FTIM2_NAND_TWHRE(0x0f)
283 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
285 #elif defined(CONFIG_TARGET_P1010RDB_PB)
286 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
287 /* ONFI NAND Flash mode0 Timing Params */
288 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
289 FTIM0_NAND_TWP(0x18) | \
290 FTIM0_NAND_TWCHT(0x07) | \
291 FTIM0_NAND_TWH(0x0a))
292 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
293 FTIM1_NAND_TWBE(0x39) | \
294 FTIM1_NAND_TRR(0x0e) | \
295 FTIM1_NAND_TRP(0x18))
296 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
297 FTIM2_NAND_TREH(0x0a) | \
298 FTIM2_NAND_TWHRE(0x1e))
299 #define CONFIG_SYS_NAND_FTIM3 0x0
302 #define CONFIG_SYS_NAND_DDR_LAW 11
304 /* Set up IFC registers for boot location NOR/NAND */
305 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
306 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
307 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
308 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
309 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
310 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
311 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
312 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
313 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
314 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
315 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
316 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
317 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
318 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
319 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
321 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
322 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
323 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
324 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
325 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
326 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
327 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
328 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
329 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
330 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
331 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
332 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
333 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
334 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
338 #define CONFIG_SYS_CPLD_BASE 0xffb00000
340 #ifdef CONFIG_PHYS_64BIT
341 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
343 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
346 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
350 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
351 #define CONFIG_SYS_CSOR3 0x0
352 /* CPLD Timing parameters for IFC CS3 */
353 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
354 FTIM0_GPCM_TEADC(0x0e) | \
355 FTIM0_GPCM_TEAHC(0x0e))
356 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
357 FTIM1_GPCM_TRAD(0x1f))
358 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
359 FTIM2_GPCM_TCH(0x8) | \
360 FTIM2_GPCM_TWP(0x1f))
361 #define CONFIG_SYS_CS3_FTIM3 0x0
363 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
364 defined(CONFIG_RAMBOOT_NAND)
365 #define CONFIG_SYS_RAMBOOT
367 #undef CONFIG_SYS_RAMBOOT
370 #define CONFIG_SYS_INIT_RAM_LOCK
371 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
372 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
374 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
376 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
379 * Config the L2 Cache as L2 SRAM
381 #if defined(CONFIG_SPL_BUILD)
382 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
383 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
384 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
385 #define CONFIG_SYS_L2_SIZE (256 << 10)
386 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
387 #elif defined(CONFIG_MTD_RAW_NAND)
388 #ifdef CONFIG_TPL_BUILD
389 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
390 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
391 #define CONFIG_SYS_L2_SIZE (256 << 10)
392 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
394 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
395 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
396 #define CONFIG_SYS_L2_SIZE (256 << 10)
397 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
403 #undef CONFIG_SERIAL_SOFTWARE_FIFO
404 #define CONFIG_SYS_NS16550_SERIAL
405 #define CONFIG_SYS_NS16550_REG_SIZE 1
406 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
407 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
408 #define CONFIG_NS16550_MIN_FUNCTIONS
411 #define CONFIG_SYS_BAUDRATE_TABLE \
412 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
414 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
415 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
418 #define I2C_PCA9557_ADDR1 0x18
419 #define I2C_PCA9557_ADDR2 0x19
420 #define I2C_PCA9557_BUS_NUM 0
423 #if defined(CONFIG_TARGET_P1010RDB_PB)
424 #ifdef CONFIG_ID_EEPROM
425 #define CONFIG_SYS_I2C_EEPROM_NXID
427 #define CONFIG_SYS_EEPROM_BUS_NUM 0
428 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
430 /* enable read and write access to EEPROM */
433 #define CONFIG_RTC_PT7C4338
434 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
437 * SPI interface will not be available in case of NAND boot SPI CS0 will be
440 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
441 /* eSPI - Enhanced SPI */
444 #if defined(CONFIG_TSEC_ENET)
445 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
446 #define CONFIG_TSEC1 1
447 #define CONFIG_TSEC1_NAME "eTSEC1"
448 #define CONFIG_TSEC2 1
449 #define CONFIG_TSEC2_NAME "eTSEC2"
450 #define CONFIG_TSEC3 1
451 #define CONFIG_TSEC3_NAME "eTSEC3"
453 #define TSEC1_PHY_ADDR 1
454 #define TSEC2_PHY_ADDR 0
455 #define TSEC3_PHY_ADDR 2
457 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
458 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
459 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
461 #define TSEC1_PHYIDX 0
462 #define TSEC2_PHYIDX 0
463 #define TSEC3_PHYIDX 0
465 /* TBI PHY configuration for SGMII mode */
466 #define CONFIG_TSEC_TBICR_SETTINGS ( \
468 | TBICR_ANEG_ENABLE \
469 | TBICR_FULL_DUPLEX \
473 #endif /* CONFIG_TSEC_ENET */
476 #define CONFIG_FSL_SATA_V2
478 #ifdef CONFIG_FSL_SATA
480 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
481 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
483 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
484 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
487 #endif /* #ifdef CONFIG_FSL_SATA */
490 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
496 #if defined(CONFIG_SDCARD)
497 #define CONFIG_FSL_FIXED_MMC_LOCATION
498 #elif defined(CONFIG_MTD_RAW_NAND)
499 #ifdef CONFIG_TPL_BUILD
500 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
502 #if defined(CONFIG_TARGET_P1010RDB_PA)
503 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
504 #elif defined(CONFIG_TARGET_P1010RDB_PB)
505 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
510 #define CONFIG_LOADS_ECHO /* echo on for serial download */
511 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
513 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
514 || defined(CONFIG_FSL_SATA)
518 * Miscellaneous configurable options
522 * For booting Linux, the board info and command line data
523 * have to be in the first 64 MB of memory, since this is
524 * the maximum mapped by the Linux kernel during initialization.
526 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
527 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
530 * Environment Configuration
533 #define CONFIG_ROOTPATH "/opt/nfsroot"
534 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
536 #define CONFIG_EXTRA_ENV_SETTINGS \
537 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
539 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
540 "loadaddr=1000000\0" \
541 "consoledev=ttyS0\0" \
542 "ramdiskaddr=2000000\0" \
543 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
544 "fdtaddr=1e00000\0" \
545 "fdtfile=p1010rdb.dtb\0" \
547 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
548 "othbootargs=ramdisk_size=600000\0" \
549 "usbfatboot=setenv bootargs root=/dev/ram rw " \
550 "console=$consoledev,$baudrate $othbootargs; " \
552 "fatload usb 0:2 $loadaddr $bootfile;" \
553 "fatload usb 0:2 $fdtaddr $fdtfile;" \
554 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
555 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
556 "usbext2boot=setenv bootargs root=/dev/ram rw " \
557 "console=$consoledev,$baudrate $othbootargs; " \
559 "ext2load usb 0:4 $loadaddr $bootfile;" \
560 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
561 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
562 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
565 #if defined(CONFIG_TARGET_P1010RDB_PA)
567 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
568 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
569 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
570 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
571 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
572 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
574 #elif defined(CONFIG_TARGET_P1010RDB_PB)
576 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
577 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
578 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
579 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
580 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
581 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
582 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
583 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
584 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
585 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
588 #include <asm/fsl_secure_boot.h>
590 #endif /* __CONFIG_H */